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| to our customers, old company name in catalogs and other documents on april 1 st , 2010, nec electronics corporation merged with renesas technology corporation, and renesas electronics corporation took over all the business of both companies. therefore, although the old company name remains in this document, it is a valid renesas electronics document. we appreciate your understanding. renesas electronics website: http://www.renesas.com april 1 st , 2010 renesas electronics corporation issued by: renesas electronics corporation ( http://www.renesas.com ) send any inquiries to http://www.renesas.com/inquiry .
notice 1. all information included in this document is current as of the date this document is issued. such information, however, is subject to change without any prior notice. before purchasing or using any renesas electronics products listed herein, please confirm the latest product information with a renesas electronics sales office. also, please pay regular and careful attention to additional and different information to be disclosed by renesas electronics such as that disclosed through our website. 2. renesas electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property ri ghts of third parties by or arising from the use of renesas electronics products or technical information described in this document . no license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property right s of renesas electronics or others. 3. you should not alter, modify, copy, or otherwise misappropriate any renesas electronics product, whether in whole or in part . 4. descriptions of circuits, software and other related information in this document are provided only to illustrate the operat ion of semiconductor products and application examples. you are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 5. when exporting the products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. you should not use renesas electronics products or the technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. renesas electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. 6. renesas electronics has used reasonable care in preparing the information included in this document, but renesas electronics does not warrant that such information is error free. renesas electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein. 7. renesas electronics products are classified according to the following three quality grades: ?standard?, ?high quality?, an d ?specific?. the recommended applications for each renesas electronics product depends on the product?s quality grade, as indicated below. you must check the quality grade of each renesas electronics product before using it in a particular application. you may not use any renesas electronics product for any application categorized as ?specific? without the prior written consent of renesas electronics. further, you may not use any renesas electronics product for any application for which it is not intended without the prior written consent of renesas electronics. renesas electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any renesas electronics product for a n application categorized as ?specific? or for which the product is not intended where you have failed to obtain the prior writte n consent of renesas electronics. the quality grade of each renesas electronics product is ?standard? unless otherwise expressly specified in a renesas electronics data sheets or data books, etc. ?standard?: computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots. ?high quality?: transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; an ti- crime systems; safety equipment; and medical equipment not specifically designed for life support. ?specific?: aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life. 8. you should use the renesas electronics products described in this document within the range specified by renesas electronics , especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. renesas electronics shall have no liability for malfunctions o r damages arising out of the use of renesas electronics products beyond such specified ranges. 9. although renesas electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. fur ther, renesas electronics products are not subject to radiation resistance design. please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a renesas electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 10. please contact a renesas electronics sales office for details as to environmental matters such as the environmental compatibility of each renesas electronics product. please use renesas electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the eu rohs directive. renesas electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. 11. this document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of renes as electronics. 12. please contact a renesas electronics sales office if you have any questions regarding the information contained in this document or renesas electronics products, or if you have any other inquiries. (note 1) ?renesas electronics? as used in this document means renesas electronics corporation and also includes its majority- owned subsidiaries. (note 2) ?renesas electronics product(s)? means any product developed or manufactured by or for renesas electronics. regarding the change of names mentioned in the document, such as hitachi electric and hitachi xx, to renesas technology corp. the semiconductor operations of mitsubishi electric and hitachi were transferred to renesas technology corporation on april 1st 2003. these operations include microcomputer, logic, analog and discrete devices, and memory chips other than drams (flash memory, srams etc.) accordingly, although hitachi, hitachi, ltd., hitachi semiconductors, and other hitachi brand names are mentioned in the document, these names have in fact all been changed to renesas technology corp. thank you for your understanding. except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. renesas technology home page: http://www.renesas.com renesas technology corp. customer support dept. april 1, 2003 to all our customers cautions keep safety first in your circuit designs! 1. renesas technology corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. notes regarding these materials 1. these materials are intended as a reference to assist our customers in the selection of the renesas technology corporation product best suited to the customer's application; they do not convey any license under any intellectual property rights, or an y other rights, belonging to renesas technology corporation or a third party. 2. renesas technology corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained i n these materials. 3. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by renesas technology corporation without notice due to product improvements or other reasons. it is therefore recommended that customers contact renesas technology corporation or an authorized renesas technology corporation product distributor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. renesas technology corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by renesas technology corporation by various means, including the renesas technology corporation semiconductor home page (http://www.renesas.com). 4. when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, an d algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. renesas technology corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. renesas technology corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. please contact renesas technology corporation or an authorized renesas technology corporation product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. the prior written approval of renesas technology corporation is necessary to reprint or reproduce in whole or in part these materials. 7. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a lice nse from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is prohibited. 8. please contact renesas technology corporation for further details on these materials or the products contained therein. h8/3397 series h8/3337 series hardware manual 8 users manual rev.6.0 2002.03 renesas singleCchip microcomputer h8/3397 hd6433397 h8/3396 hd6433396 h8/3394 hd6433394 h8/3337y hd6473337y, hd6433337y h8/3336y hd6433336y h8/3334y hd6473334y, hd6433334y h8/3337w hd6433337w h8/3336w hd6433336w h8/3337yf-ztat? hd64f3337y h8/3337sf-ztat? hd64f3337s h8/3334yf-ztat? hd64f3334y cautions 1. hitachi neither warrants nor grants licenses of any rights of hitachi? or any third party? patent, copyright, trademark, or other intellectual property rights for information contained in this document. hitachi bears no responsibility for problems that may arise with third party? rights, including intellectual property rights, in connection with use of the information contained in this document. 2. products and product specifications may be subject to change without notice. confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. hitachi makes every attempt to ensure that its products are of high quality and reliability. however, contact hitachi? sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. design your application so that the product is used within the ranges guaranteed by hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the hitachi product. 5. this product is not designed to be radiation resistant. 6. no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from hitachi. 7. contact hitachi? sales office for any questions regarding this document or hitachi semiconductor products. general precautions on handling of product 1. treatment of nc pins note: do not connect anything to the nc pins. the nc (not connected) pins are either not connected to any of the internal circuitry or are they are used as test pins or to reduce noise. if something is connected to the nc pins, the operation of the lsi is not guaranteed. 2. treatment of unused input pins note: fix all unused input pins to high or low level. generally, the input pins of cmos products are high-impedance input pins. if unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a pass- through current flows internally, and a malfunction may occur. 3. processing before initialization note: when power is first supplied, the product? state is undefined. the states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin. during the period where the states are undefined, the register settings and the output state of each pin are also undefined. design your system so that it does not malfunction because of processing while it is in this undefined state. for those products which have a reset function, reset the lsi immediately after the power supply has been turned on. 4. prohibition of access to undefined or reserved addresses note: access to undefined or reserved addresses is prohibited. the undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these addresses. do not access these registers; the system? operation is not guaranteed if they are accessed. preface the h8/3337 series and h8/3397 series is a high-performance single-chip microcomputer that integrates peripheral functions necessary for system configuration with an h8/300 cpu featuring a 32-bit internal architecture as its core. on-chip peripheral functions include rom, ram, four kinds of timers, a serial communication interface (sci), host interface (hif), keyboard controller, d/a converter, a/d converter, and i/o ports, enabling the h8/3337 series and h8/3397 series to be used as a microcontroller for embedding in high-speed control systems. flash memory (f-ztat * ), prom (ztat * ), and mask rom are available as on-chip rom, enabling users to respond quickly and flexibly to changing application specifications and the demands of the transition from initial to full-fledged volume production. note: * f-ztat is a trademark of hitachi, ltd. ztat is a registered trademark of hitachi, ltd. intended readership: this manual is intended for users undertaking the design of an application system using a h8/3337 series and h8/3397 series microcomputer. readers using this manual require a basic knowledge of electrical circuits, logic circuits, and microcomputers. purpose: the purpose of this manual is to give users an understanding of the hardware functions and electrical characteristics of the h8/3337 series and h8/3397 series. details of execution instructions can be found in the h8/300 series programming manual, which should be read in conjunction with the present manual. using this manual: ? for an overall understanding of the h8/3337 series?and h8/3397 series?functions follow the table of contents. this manual is broadly divided into sections on the cpu, system control functions, peripheral functions, and electrical characteristics. ? for a detailed understanding of cpu functions refer to the separate publication h8/300 series programming manual. ? for a detailed description of a register? function when the register name is known. information on addresses, bit contents, and initialization is summarized in appendix b, internal i/o register. note on bit notation: bits are shown in high-to-low order from left to right. related material: the latest information is available at our web site. please make sure that you have the most up-to-date information available. http://www.hitachisemiconductor.com/ user's manuals on the h8/3337 series and h8/3397 series: manual title ade no. h8/3337 series and h8/3397 series hardware manual this manual h8/300 series programming manual ade-602-025 users manuals for development tools: manual title ade no. c/c++ compiler, assembler, optimized linkage editor user's manual ade-702-247 simulator debugger users manual ade-702-282 hitachi debugging interface users manual ade-702-161 hitachi embedded workshop users manual ade-702-201 h8s, h8/300 series hitachi embedded workshop, hitachi debugging interface users manual ade-702-231 notes on s-mask model (single-power-supply specification) there are two versions of the h8/3337f with on-chip flash memory: a dual-power-supply version and a single-power-supply (s-mask) version. points to be noted when using the h8/3337f single- power-supply s-mask model are given below. 1. notes on voltage application 12 v must not be applied to the s-mask model (single-power-supply specification), as this may permanently damage the device. the flash memory programming power supply for the s-mask model (single-power-supply specification) is v cc . the programming power supply for the dual-power-supply model is the fv pp pin (12 v), but the single-power-supply model (s-mask model) does not have an fv pp pin. also, in boot mode, 12 v has to be applied to the md 1 pin in the dual-power-supply model, but 12 v application is not necessary in the single-power-supply model (s-mask model). the maximum rating of the md 1 pin is v cc +0.3 v. applying a voltage in excess of the maximum rating will permanently damage the device. do not select the hn28f101 programmer setting for the s-mask model (single-power-supply specification). if this setting is made by mistake, 12 v will be applied to the stby pin, possibly causing permanent damage to the device. when using a prom programmer to program the on-chip flash memory in the s-mask model (single-power-supply specification), use a prom programmer that supports hitachi microcomputer devices with 64-kbyte on-chip flash memory. also, only use the specified socket adapter. using the wrong prom programmer or socket adapter may damage the device. the following prom programmers support the s-mask model (single-power-supply specification). data i/o: unisite, 2900, 3900, etc. minato: 1892, 1891, 1890, etc. 2. product type names and markings table 1 shows examples of product type names and markings for the h8/3337yf (dual-power- supply specification) and h8/3337sf (single-power-supply specification), and the differences in flash memory programming power supply. table 1 differences in h8/3337yf and h8/3337f s-mask model markings dual-power-supply model: h8/3337yf single-power-supply model: h8/3337f s-mask model product type name hd64f3337yf16/tf16 hd64f3337sf16/tf16 sample markings h8/3337 hd 64f3337f16 8m3 japan h8/3337 hd s 64f3337f16 8m3 japan ??is printed above the type name flash memory programming power supply v pp power supply (12.0 v 0.6 v) v cc power supply (5.0 v 10%) 3. differences in s-mask model table 2 shows the differences between the h8/3337f (dual-power-supply specification) and h8/3337sf (single-power-supply specification). table 2 differences between h8/3337f and h8/3337f s-mask model item dual-power-supply model: h8/3337f single-power-supply model: h8/3337f s-mask model program/ erase voltage 12 v must be applied from off-chip v pp (12.0 v 0.6 v) 12 v application not required v cc single-power-supply programming v cc (5.0 v 10%) fv pp (fwe) pin function dual function as fv pp power supply and stby function no programming control pin programming modes ? writer mode ? on-board ? boot mode ? user programming mode (see section 21 for the use of these modes) operating modes allowing on-board programming ? writer mode ? boot mode ? user programming mode (see section 21 for the use of these modes) on-board programming unit 1-byte-unit programming 32-byte-unit programming programming with prom programmer select hitachi stand-alone flash memory hn28f101 setting special programming mode setting required. use of prom programmer that supports hitachi microcomputer device types with 64-kbyte on-chip flash memory. (128-byte-unit fast page programming) boot mode setting method reset release after md 1 = fv pp /stby = 12 v application md 1 0 md 0 0 p9 2 1 p9 1 1 p9 0 1 pin setting level reset release after above pin settings user program mode setting method fv pp = 12 v application control bits set by software item dual-power-supply model: h8/3337f single-power-supply model: h8/3337f s-mask model programming mode timing res md 0 md 1 12 v 12 v min 0 s tmds tmds: 4tcyc (min.) v pp res md 1 , md 1 p9 2 , p9 1 , p9 0 tmds tmds: 4tcyc (min.) prewrite processing required before erasing not required programming processing block corresponding to programming address must be set in ebr1/ebr2 registers before programming settings at left not required ebr register configuration ebr1, ebr2 ebr2 memory map (block configuration) lb0 (4 kbytes) lb1(8 kbytes) lb2 (8 kbytes) lb3 (8 kbytes) lb4 (8 kbytes) lb5 (8 kbytes) lb6 (12 kbytes) lb7 (2 kbytes) sb0 (128 bytes) sb1 (128 bytes) sb2 (128 bytes) sb3 (128 bytes) sb4 (512 bytes) sb5 (1 kbyte) sb6 (1 kbyte) sb7 (1 kbyte) 60 kbytes eb4 (24 kbytes) eb5 (16 kbytes) eb6 (12 kbytes) eb7 (2 kbytes) eb0 (1 kbyte) eb1 (1 kbyte) eb2 (1 kbyte) eb3 (1 kbyte) 60 kbytes reset during operation drive res pin low for at least 10 system clock cycles (10 ). ( res pulse width t resw = min. 10t cyc ) drive res pin low for at least 20 system clock cycles (20 ). ( res pulse width t resw = min. 20t cyc ) item dual-power-supply model: h8/3337f single-power-supply model: h8/3337f s-mask model mdcr 76 321 mds1 0 mds0 5 4 76 321 mds1 0 mds0 5 expe 4 bit 7: expanded mode enable (expe) wscr 76 321 wc1 0 wc0 5 rams ram0 ckdbl 4 wms1wms0 76 321 wc1 0 wc0 5 ckdbl 4 flshe wms1 wms0 bit 4: flash memory control register enable (flshe) flmcr1 7 v pp 63 ev 2 pv 1 e 0 p 5 4 7 fwe swe 63 ev 2 pv 1 e 0 p 5 4 bit 7: flash write enable (fwe) bit 6: software write enable (swe) flmcr2 7 fler 6321 esu 0 psu 5 4 bit 7: flash memory error (fler) bit 1: erase setup (esu) bit 0: program setup (psu) ebr1 76 3210 54 lb7 lb6 lb5 lb4 lb3 lb2 lb1 lb0 this address is not used. ebr2 76 3210 54 sb7 sb6 sb5 sb4 sb3 sb2 sb1 sb0 76 3210 54 eb7 eb6 eb5 eb4 eb3 eb2 eb1 eb0 erase block register (ebr2) eb0 (1 kbyte): h'0000 to h'03ff eb1 (1 kbyte): h'0400 to h'07ff eb2 (1 kbyte): h'0800 to h'0bff eb3 (1 kbyte): h'0c00 to h'0fff eb4 (28 kbytes): h'1000 to h'7fff eb5 (16 kbytes): h'8000 to h'bfff eb6 (12 kbytes): h'c000 to h'ef7f eb7 (2 kbytes): h'ef00 to h'f77f details concerning flash memory see section 20, rom (dual-power- supply 60-kbyte flash memory version) see section 21, rom (single-power- supply 60-kbyte flash memory version) electrical characteristics see section 23, electrical characteristics see section 23, electrical characteristics registers see appendix b, registers see appendix b, registers table 3 shows differences in the development environments of the h8/3337yf (dual-power- supply specification) and h8/3337sf (single-power-supply specification). table 3 h8/3337yf and h8/3337f s-mask model development environments item dual-power-supply model: h8/3337yf single-power-supply model: h8/3337f s-mask model e6000 emulator emulator unit hitachi hs3008epi60h hitachi hs3008epi60h user cable hitachi hs3437ech61h hitachi hs3437ech61h programming socket adapter hitachi hs3434eshf1h minato data i/o adapter board hitachi hs0008easf1h/2h hitachi hs0008easf3h windows interface software hitachi hs6400fwiw2sf hitachi hs6400fwiw2sf table 4 shows differences in the pin settings of the h8/3337yf (dual-power-supply specification) and h8/3337sf (single-power-supply specification). table 4 h8/3337yf and h8/3337f s-mask model pin settings item dual-power-supply model: h8/3337yf single-power-supply model: h8/3337f s-mask model boot mode 8 12 v h8/3337yf fv pp / stby md 1 5 23 24 25 5 6 v cc (5 v) v ss (gnd) h8/3337sf p9 2 p9 1 p9 0 md 1 md 0 user programming mode 8 12 v h8/3337yf fv pp / stby there are no state transitions due to pin states. transitions should be implemented by means of register settings by software. list of items revised or added for this version section page item description (see manual for details) notes on s-mask model (single-power-supply specification) table 1 differences in h8/3337yf and h8/3337f s- mask model markings single-power-supply model: h8/3337f s- mask model sample marking amended 1.1 overview 1 comment added to note 3 table 1.1 features ?ther features specifications amended. 4 h8/3337y ztat hd6473337ycg16 deleted from series lineup item 5 h8/3334f-ztat rom amended in ?eries lineup?specifications. notes 1, 3 deleted 1.3.1 pin arrangement 8 figure 1.2 (a) pin arrangement for h8/3337 series (fp-80a, tfp-80c, top view) rotated 90 degrees to the left, so that pin 1 is at the bottom left. 9 figure 1.2 (b) pin arrangement for h8/3397 series (fp-80a, tfp-80c, top view) 10 figure 1.3 (a) pin arrangement for h8/3337 series (cp-84, cg-84, top view) 11 figure 1.3 (b) pin arrangement for h8/3397 series (cp-84, top view) 4.3.1 overview 75 table 4.2 interrupts note numbers amended 6.2.2 oscillator circuit (h8/3337sf) 101 to 105 added 12.3.2 asynchronous mode 263 figure 12.5 sample flowchart for transmitting serial data flowchart amended. procedure 1 description added. section 13 i 2 c bus interface (h8/3337 series 281 descriptions 1 and 3 deleted section page item description (see manual for details) only) [option] 13.4 application notes 309 4. note on issuance of retransmission start condition 5. note on issuance of stop condition 6. countermeasure 7. additional note 8. precautions when clearing the iric flag when using the wait function added 15.6.6 effect on absolute accuracy 352 figure 15.10 example of analog input circuit figure amended 18.3.2 notes on programming 371 (1) description added. 21.1.7 flash memory operating modes 500 figure 21.2 flash memory related state transitions ?we?amended to ?lshe? 501 figure 21.3 boot mode procedure 2 amended. 502 figure 21.4 user programming mode (example) procedure 2 amended. 21.2.3 erase block register 2 (ebr2) 507 bit 7 * and note description added. 21.3.1 boot mode 512 ram area allocation in boot mode description amended. 513 figure 21.9 ram areas in boot mode amended notes on use of boot mode 5 description amended. 21.4 to 21.4.4 516 to 520 entire description amended. 21.5.1 writer mode setting 524 * and note description added. 21.5.3 operation in writer mode 534 figure 21.22 status read mode timing waveforms table 21.19 status read mode return codes note amended 21.6 flash memory programming and erasing 536 (1) program with the specified voltage and timing description amended. precautions 537 table 21.22 area accessed in each mode with flshe = 0 flshe = 1 mode 2 amended section page item description (see manual for details) and flshe = 1 22.3.5 application notes 546 2 description deleted. 23 electrical characteristics 549 to 596 heading number amended 23.3 absolute maximum ratings (h8/3337sf low- voltage version 573 newly added 23.4 electrical characteristics (h8/3337sf low-voltage version) 574 to 586 newly added b.2 function 661 i 2 c bus control register bit 2 to 0: i 2 c transfer rate select table amended and note added i contents section 1 overview ........................................................................................................... 1 1.1 overview.................................................................................................................... ........ 1 1.2 block diagram............................................................................................................... .... 6 1.3 pin assignments and functions......................................................................................... 8 1.3.1 pin arrangement .................................................................................................. 8 1.3.2 pin functions........................................................................................................ 12 section 2 cpu ....................................................................................................................... 25 2.1 overview.................................................................................................................... ........ 25 2.1.1 features ................................................................................................................ 25 2.1.2 address space ...................................................................................................... 26 2.1.3 register configuration ......................................................................................... 26 2.2 register descriptions....................................................................................................... .. 27 2.2.1 general registers.................................................................................................. 27 2.2.2 control registers.................................................................................................. 27 2.2.3 initial register values .......................................................................................... 28 2.3 data formats................................................................................................................ ...... 29 2.3.1 data formats in general registers....................................................................... 30 2.3.2 memory data formats.......................................................................................... 31 2.4 addressing modes ............................................................................................................ .32 2.4.1 addressing mode.................................................................................................. 32 2.4.2 calculation of effective address.......................................................................... 34 2.5 instruction set............................................................................................................. ....... 38 2.5.1 data transfer instructions .................................................................................... 40 2.5.2 arithmetic operations .......................................................................................... 42 2.5.3 logic operations .................................................................................................. 43 2.5.4 shift operations.................................................................................................... 43 2.5.5 bit manipulations ................................................................................................. 45 2.5.6 branching instructions.......................................................................................... 50 2.5.7 system control instructions ................................................................................. 52 2.5.8 block data transfer instruction ........................................................................... 53 2.6 cpu states .................................................................................................................. ....... 55 2.6.1 overview .............................................................................................................. 55 2.6.2 program execution state ...................................................................................... 56 2.6.3 exception-handling state .................................................................................... 56 2.6.4 power-down state................................................................................................ 57 2.7 access timing and bus cycle........................................................................................... 57 2.7.1 access to on-chip memory (ram and rom) ................................................... 57 2.7.2 access to on-chip supporting modules and external devices .......................... 59 ii section 3 mcu operating modes and address space ............................................. 63 3.1 overview.................................................................................................................... ........ 63 3.1.1 mode selection..................................................................................................... 63 3.1.2 mode and system control registers ................................................................... 63 3.2 system control register (syscr).................................................................................... 64 3.3 mode control register (mdcr) ....................................................................................... 66 3.4 address space map in each operating mode................................................................... 66 section 4 exception handling .......................................................................................... 71 4.1 overview.................................................................................................................... ........ 71 4.2 reset ....................................................................................................................... ........... 71 4.2.1 overview .............................................................................................................. 71 4.2.2 reset sequence..................................................................................................... 71 4.2.3 disabling of interrupts after reset ....................................................................... 74 4.3 interrupts.................................................................................................................. .......... 74 4.3.1 overview .............................................................................................................. 74 4.3.2 interrupt-related registers .................................................................................. 76 4.3.3 external interrupts................................................................................................ 80 4.3.4 internal interrupts ................................................................................................. 80 4.3.5 interrupt handling ................................................................................................ 81 4.3.6 interrupt response time ...................................................................................... 86 4.3.7 precaution ............................................................................................................. 86 4.4 note on stack handling..................................................................................................... 8 7 section 5 wait-state controller ....................................................................................... 89 5.1 overview.................................................................................................................... ........ 89 5.1.1 features ................................................................................................................ 89 5.1.2 block diagram...................................................................................................... 89 5.1.3 input/output pins.................................................................................................. 90 5.1.4 register configuration ......................................................................................... 90 5.2 register description ........................................................................................................ .. 90 5.2.1 wait-state control register (wscr) .................................................................. 90 5.3 wait modes.................................................................................................................. ...... 92 section 6 clock pulse generator ..................................................................................... 95 6.1 overview................................................................................................................... ......... 95 6.1.1 block diagram...................................................................................................... 95 6.1.2 wait-state control register (wscr) .................................................................. 96 6.2 oscillator circuit ......................................................................................................... ...... 97 6.2.1 oscillator (generic device).................................................................................. 97 6.2.2 oscillator circuit (h8/3337sf) ............................................................................ 101 6.3 duty adjustment circuit.................................................................................................... 105 6.4 prescaler .................................................................................................................. .......... 105 iii section 7 i/o ports ............................................................................................................... 107 7.1 overview.................................................................................................................... ........ 107 7.2 port 1...................................................................................................................... ............ 112 7.2.1 overview .............................................................................................................. 112 7.2.2 register configuration and descriptions ............................................................. 113 7.2.3 pin functions in each mode ................................................................................ 115 7.2.4 input pull-up transistors ..................................................................................... 117 7.3 port 2...................................................................................................................... ............ 118 7.3.1 overview .............................................................................................................. 118 7.3.2 register configuration and descriptions ............................................................. 119 7.3.3 pin functions in each mode ................................................................................ 121 7.3.4 input pull-up transistors ..................................................................................... 123 7.4 port 3...................................................................................................................... ............ 123 7.4.1 overview .............................................................................................................. 123 7.4.2 register configuration and descriptions ............................................................. 125 7.4.3 pin functions in each mode ................................................................................ 127 7.4.4 input pull-up transistors ..................................................................................... 129 7.5 port 4...................................................................................................................... ............ 129 7.5.1 overview .............................................................................................................. 129 7.5.2 register configuration and descriptions.............................................................. 131 7.5.3 pin functions........................................................................................................ 133 7.6 port 5...................................................................................................................... ............ 135 7.6.1 overview .............................................................................................................. 135 7.6.2 register configuration and descriptions ............................................................. 135 7.6.3 pin functions........................................................................................................ 137 7.7 port 6...................................................................................................................... ............ 138 7.7.1 overview .............................................................................................................. 138 7.7.2 register configuration and descriptions ............................................................. 138 7.7.3 pin functions........................................................................................................ 141 7.7.4 input pull-up transistors ..................................................................................... 143 7.8 port 7...................................................................................................................... ............ 144 7.8.1 overview .............................................................................................................. 144 7.8.2 register configuration and descriptions ............................................................. 144 7.9 port 8...................................................................................................................... ............ 145 7.9.1 overview .............................................................................................................. 145 7.9.2 register configuration and descriptions ............................................................. 146 7.9.3 pin functions........................................................................................................ 148 7.10 port 9..................................................................................................................... ............. 151 7.10.1 overview .............................................................................................................. 151 7.10.2 register configuration and descriptions ............................................................. 152 7.10.3 pin functions........................................................................................................ 154 iv section 8 16-bit free-running timer ......................................................................... 157 8.1 overview.................................................................................................................... ........ 157 8.1.1 features ................................................................................................................ 15 7 8.1.2 block diagram...................................................................................................... 158 8.1.3 input and output pins........................................................................................... 159 8.1.4 register configuration ......................................................................................... 160 8.2 register descriptions....................................................................................................... .. 161 8.2.1 free-running counter (frc)............................................................................... 161 8.2.2 output compare registers a and b (ocra and ocrb).................................... 161 8.2.3 input capture registers a to d (icra to icrd) ................................................ 162 8.2.4 timer interrupt enable register (tier) .............................................................. 164 8.2.5 timer control/status register (tcsr) ................................................................ 166 8.2.6 timer control register (tcr) ............................................................................. 168 8.2.7 timer output compare control register (tocr) .............................................. 170 8.3 cpu interface ............................................................................................................... ..... 172 8.4 operation ................................................................................................................... ........ 175 8.4.1 frc increment timing ........................................................................................ 175 8.4.2 output compare timing ...................................................................................... 177 8.4.3 frc clear timing................................................................................................ 178 8.4.4 input capture timing ........................................................................................... 178 8.4.5 timing of input capture flag (icf) setting ........................................................ 181 8.4.6 setting of output compare flags a and b (ocfa and ocfb) .......................... 181 8.4.7 setting of timer overflow flag (ovf)................................................................ 182 8.5 interrupts.................................................................................................................. .......... 183 8.6 sample application .......................................................................................................... . 184 8.7 application notes........................................................................................................... ... 185 section 9 8-bit timers ..................................................................................................... 191 9.1 overview.................................................................................................................... ........ 191 9.1.1 features ................................................................................................................ 19 1 9.1.2 block diagram...................................................................................................... 192 9.1.3 input and output pins........................................................................................... 193 9.1.4 register configuration ......................................................................................... 193 9.2 register descriptions....................................................................................................... .. 194 9.2.1 timer counter (tcnt) ........................................................................................ 194 9.2.2 time constant registers a and b (tcora and tcorb).................................. 194 9.2.3 timer control register (tcr) ............................................................................. 195 9.2.4 timer control/status register (tcsr) ................................................................ 198 9.2.5 serial/timer control register (stcr) ................................................................ 200 9.3 operation ................................................................................................................... ........ 201 9.3.1 tcnt increment timing...................................................................................... 201 9.3.2 compare-match timing ....................................................................................... 203 9.3.3 external reset of tcnt....................................................................................... 205 v 9.3.4 setting of overflow flag (ovf) .......................................................................... 205 9.4 interrupts.................................................................................................................. .......... 206 9.5 sample application .......................................................................................................... . 206 9.6 application notes........................................................................................................... ... 207 9.6.1 contention between tcnt write and clear ....................................................... 207 9.6.2 contention between tcnt write and increment ............................................... 208 9.6.3 contention between tcor write and compare-match ..................................... 209 9.6.4 contention between compare-match a and compare-match b ......................... 210 9.6.5 increment caused by changing of internal clock source ................................... 210 section 10 pwm timers .................................................................................................... 213 10.1 overview................................................................................................................... ......... 213 10.1.1 features ................................................................................................................ 2 13 10.1.2 block diagram...................................................................................................... 214 10.1.3 input and output pins........................................................................................... 214 10.1.4 register configuration ......................................................................................... 215 10.2 register descriptions...................................................................................................... ... 215 10.2.1 timer counter (tcnt) ........................................................................................ 215 10.2.2 duty register (dtr) ............................................................................................ 216 10.2.3 timer control register (tcr) ............................................................................. 217 10.3 operation .................................................................................................................. ......... 219 10.3.1 timer incrementation ........................................................................................... 219 10.3.2 pwm operation.................................................................................................... 220 10.4 application notes.......................................................................................................... .... 221 section 11 watchdog timer ............................................................................................. 223 11.1 overview................................................................................................................... ......... 223 11.1.1 features ................................................................................................................ 2 23 11.1.2 block diagram...................................................................................................... 224 11.1.3 register configuration ......................................................................................... 224 11.2 register descriptions...................................................................................................... ... 225 11.2.1 timer counter (tcnt) ........................................................................................ 225 11.2.2 timer control/status register (tcsr) ................................................................ 225 11.2.3 system control register (syscr) ...................................................................... 227 11.2.4 register access .................................................................................................... 228 11.3 operation .................................................................................................................. ......... 229 11.3.1 watchdog timer mode ........................................................................................ 229 11.3.2 interval timer mode ............................................................................................ 230 11.3.3 setting the overflow flag .................................................................................... 230 11.4 application notes.......................................................................................................... .... 231 11.4.1 contention between tcnt write and increment ................................................ 231 11.4.2 changing the clock select bits (cks2 to cks0)................................................ 231 11.4.3 recovery from software standby mode .............................................................. 231 vi 11.4.4 switching between watchdog timer mode and interval timer mode................ 232 11.4.5 detection of program runaway ........................................................................... 232 section 12 serial communication interface ................................................................ 233 12.1 overview................................................................................................................... ......... 233 12.1.1 features ................................................................................................................ 2 33 12.1.2 block diagram...................................................................................................... 234 12.1.3 input and output pins........................................................................................... 235 12.1.4 register configuration ......................................................................................... 236 12.2 register descriptions...................................................................................................... ... 237 12.2.1 receive shift register (rsr)............................................................................... 237 12.2.2 receive data register (rdr) .............................................................................. 237 12.2.3 transmit shift register (tsr).............................................................................. 237 12.2.4 transmit data register (tdr) ............................................................................. 238 12.2.5 serial mode register (smr)................................................................................ 238 12.2.6 serial control register (scr).............................................................................. 240 12.2.7 serial status register (ssr)................................................................................. 243 12.2.8 bit rate register (brr)....................................................................................... 246 12.2.9 serial/timer control register (stcr) ................................................................ 256 12.3 operation .................................................................................................................. ......... 257 12.3.1 overview .............................................................................................................. 257 12.3.2 asynchronous mode ............................................................................................ 259 12.3.3 synchronous mode............................................................................................... 272 12.4 interrupts................................................................................................................. ........... 278 12.5 application notes.......................................................................................................... .... 278 section 13 i 2 c bus interface (h8/3337 series only) [option] .............................. 281 13.1 overview.................................................................................................................. .......... 281 13.1.1 features ................................................................................................................ 281 13.1.2 block diagram...................................................................................................... 283 13.1.3 input/output pins.................................................................................................. 284 13.1.4 register configuration ......................................................................................... 284 13.2 register descriptions..................................................................................................... .... 285 13.2.1 i 2 c bus data register (icdr).............................................................................. 285 13.2.2 slave address register (sar) ............................................................................. 285 13.2.3 i 2 c bus mode register (icmr) ........................................................................... 286 13.2.4 i 2 c bus control register (iccr) ......................................................................... 287 13.2.5 i 2 c bus status register (icsr)............................................................................ 290 13.2.6 serial/timer control register (stcr) ................................................................ 294 13.3 operation ................................................................................................................. .......... 295 13.3.1 i 2 c bus data format............................................................................................. 295 13.3.2 master transmit operation .................................................................................. 296 13.3.3 master receive operation .................................................................................... 298 vii 13.3.4 slave transmit operation..................................................................................... 300 13.3.5 slave receive operation ...................................................................................... 302 13.3.6 iric set timing and scl control....................................................................... 303 13.3.7 noise canceler...................................................................................................... 304 13.3.8 sample flowcharts ............................................................................................... 305 13.4 application notes......................................................................................................... ..... 309 section 14 host interface (h8/3337 series only) ...................................................... 315 14.1 overview.................................................................................................................. .......... 315 14.1.1 block diagram...................................................................................................... 316 14.1.2 input and output pins........................................................................................... 317 14.1.3 register configuration ......................................................................................... 318 14.2 register descriptions..................................................................................................... .... 319 14.2.1 system control register (syscr) ...................................................................... 319 14.2.2 host interface control register (hicr) .............................................................. 319 14.2.3 input data register 1 (idr1) ............................................................................... 320 14.2.4 output data register 1 (odr1) ........................................................................... 321 14.2.5 status register 1 (str1)...................................................................................... 321 14.2.6 input data register 2 (idr2) ............................................................................... 322 14.2.7 output data register 2 (odr2) ........................................................................... 323 14.2.8 status register 2 (str2)...................................................................................... 323 14.2.9 serial/timer control register (stcr) ................................................................ 325 14.3 operation ................................................................................................................. .......... 326 14.3.1 host interface operation ...................................................................................... 326 14.3.2 control states ....................................................................................................... 326 14.3.3 a 20 gate ................................................................................................................ 327 14.4 interrupts................................................................................................................ ............ 330 14.4.1 ibf1, ibf2............................................................................................................ 33 0 14.4.2 hirq 11 , hirq 1 , and hirq 12 ................................................................................ 330 14.5 application note.......................................................................................................... ...... 331 section 15 a/d converter ................................................................................................. 333 15.1 overview.................................................................................................................. .......... 333 15.1.1 features ................................................................................................................ 333 15.1.2 block diagram...................................................................................................... 334 15.1.3 input pins.............................................................................................................. 335 15.1.4 register configuration ......................................................................................... 336 15.2 register descriptions..................................................................................................... .... 337 15.2.1 a/d data registers a to d (addra to addrd).............................................. 337 15.2.2 a/d control/status register (adcsr)................................................................ 338 15.2.3 a/d control register (adcr)............................................................................. 340 15.3 cpu interface ............................................................................................................. ....... 340 15.4 operation ................................................................................................................. .......... 342 viii 15.4.1 single mode (scan = 0) ..................................................................................... 342 15.4.2 scan mode (scan = 1) ....................................................................................... 344 15.4.3 input sampling and a/d conversion time.......................................................... 346 15.4.4 external trigger input timing ............................................................................. 347 15.5 interrupts................................................................................................................ ............ 348 15.6 useage notes .............................................................................................................. ....... 348 15.6.1 setting ranges of analog power supply pins, etc. ............................................. 348 15.6.2 notes on board design ........................................................................................ 348 15.6.3 notes on noise ..................................................................................................... 348 15.6.4 a/d conversion accuracy definitions ................................................................ 349 15.6.5 allowable signal-source impedance ................................................................... 351 15.6.6 effect on absolute accuracy................................................................................ 352 section 16 d/a converter (h8/3337 series only) .................................................... 353 16.1 overview.................................................................................................................. .......... 353 16.1.1 features ................................................................................................................ 353 16.1.2 block diagram...................................................................................................... 354 16.1.3 input and output pins........................................................................................... 355 16.1.4 register configuration ......................................................................................... 355 16.2 register descriptions ..................................................................................................... ... 356 16.2.1 d/a data registers 0 and 1 (dadr0, dadr1).................................................. 356 16.2.2 d/a control register (dacr)............................................................................. 356 16.3 operation ................................................................................................................. .......... 358 section 17 ram ................................................................................................................... 359 17.1 overview.................................................................................................................. .......... 359 17.1.1 block diagram...................................................................................................... 359 17.1.2 ram enable bit (rame) in system control register (syscr) ....................... 360 17.2 operation ................................................................................................................. .......... 360 17.2.1 expanded modes (modes 1 and 2)....................................................................... 360 17.2.2 single-chip mode (mode 3) ................................................................................ 360 section 18 rom (mask rom version/ztat version) .......................................... 361 18.1 overview.................................................................................................................. .......... 361 18.1.1 block diagram...................................................................................................... 362 18.2 writer mode (h8/3337y, h8/3334y) ............................................................................... 362 18.2.1 writer mode setup ............................................................................................... 362 18.2.2 socket adapter pin assignments and memory map ........................................... 363 18.3 prom programming ......................................................................................................... 3 66 18.3.1 programming and verification ............................................................................. 366 18.3.2 notes on programming......................................................................................... 371 18.3.3 reliability of programmed data .......................................................................... 371 18.3.4 erasing data ......................................................................................................... 372 ix section 19 rom (32-kbyte dual-power-supply flash memory version) ........ 373 19.1 flash memory overview ................................................................................................... 37 3 19.1.1 flash memory operating principle ...................................................................... 373 19.1.2 mode programming and flash memory address space...................................... 374 19.1.3 features ................................................................................................................ 374 19.1.4 block diagram...................................................................................................... 375 19.1.5 input/output pins.................................................................................................. 376 19.1.6 register configuration ......................................................................................... 376 19.2 flash memory register descriptions ................................................................................ 377 19.2.1 flash memory control register (flmcr).......................................................... 377 19.2.2 erase block register 1 (ebr1)............................................................................ 378 19.2.3 erase block register 2 (ebr2)............................................................................ 379 19.2.4 wait-state control register (wscr) .................................................................. 380 19.3 on-board programming modes ........................................................................................ 383 19.3.1 boot mode............................................................................................................ 384 19.3.2 user programming mode ..................................................................................... 390 19.4 programming and erasing flash memory......................................................................... 392 19.4.1 program mode...................................................................................................... 392 19.4.2 program-verify mode .......................................................................................... 393 19.4.3 programming flowchart and sample program .................................................... 394 19.4.4 erase mode........................................................................................................... 396 19.4.5 erase-verify mode ............................................................................................... 396 19.4.6 erasing flowchart and sample program .............................................................. 397 19.4.7 prewrite verify mode........................................................................................... 410 19.4.8 protect modes....................................................................................................... 410 19.4.9 interrupt handling during flash memory programming and erasing ................. 411 19.5 flash memory emulation by ram ................................................................................... 413 19.6 flash memory writer mode (h8/3334yf) ....................................................................... 416 19.6.1 writer mode setting ............................................................................................. 416 19.6.2 socket adapter and memory map ....................................................................... 416 19.6.3 operation in writer mode .................................................................................... 418 19.7 flash memory programming and erasing precautions ..................................................... 426 section 20 rom (60-kbyte dual-power-supply flash memory version) ........ 433 20.1 flash memory overview ................................................................................................... 43 3 20.1.1 flash memory operating principle ...................................................................... 433 20.1.2 mode programming and flash memory address space...................................... 434 20.1.3 features ................................................................................................................ 434 20.1.4 block diagram...................................................................................................... 435 20.1.5 input/output pins.................................................................................................. 436 20.1.6 register configuration ......................................................................................... 436 20.2 flash memory register descriptions ................................................................................ 437 20.2.1 flash memory control register (flmcr).......................................................... 437 x 20.2.2 erase block register 1 (ebr1)............................................................................ 438 20.2.3 erase block register 2 (ebr2)............................................................................ 439 20.2.4 wait-state control register (wscr) .................................................................. 440 20.3 on-board programming modes ........................................................................................ 443 20.3.1 boot mode............................................................................................................ 444 20.3.2 user programming mode ..................................................................................... 450 20.4 programming and erasing flash memory......................................................................... 452 20.4.1 program mode...................................................................................................... 452 20.4.2 program-verify mode .......................................................................................... 453 20.4.3 programming flowchart and sample program .................................................... 454 20.4.4 erase mode........................................................................................................... 456 20.4.5 erase-verify mode ............................................................................................... 456 20.4.6 erasing flowchart and sample program .............................................................. 457 20.4.7 prewrite verify mode........................................................................................... 470 20.4.8 protect modes....................................................................................................... 470 20.4.9 interrupt handling during flash memory programming and erasing ................. 471 20.5 flash memory emulation by ram ................................................................................... 473 20.6 flash memory writer mode (h8/3337yf) ....................................................................... 476 20.6.1 writer mode setting ............................................................................................. 476 20.6.2 socket adapter and memory map ....................................................................... 476 20.6.3 operation in writer mode .................................................................................... 478 20.7 flash memory programming and erasing precautions ..................................................... 486 section 21 rom (60-kbyte single-power-supply flash memory version) ..... 495 21.1 flash memory overview ................................................................................................... 49 5 21.1.1 mode pin settings and rom space ..................................................................... 495 21.1.2 features ................................................................................................................ 496 21.1.3 block diagram...................................................................................................... 497 21.1.4 input/output pins.................................................................................................. 498 21.1.5 register configuration ......................................................................................... 498 21.1.6 mode control register (mdcr).......................................................................... 499 21.1.7 flash memory operating modes.......................................................................... 500 21.2 flash memory register descriptions ................................................................................ 504 21.2.1 flash memory control register 1 (flmcr1)..................................................... 504 21.2.2 flash memory control register 2 (flmcr2)..................................................... 506 21.2.3 erase block register 2 (ebr2)............................................................................ 507 21.2.4 wait-state control register (wscr) .................................................................. 508 21.3 on-board programming modes ........................................................................................ 509 21.3.1 boot mode............................................................................................................ 509 21.3.2 user programming mode ..................................................................................... 515 21.4 programming/erasing flash memory................................................................................ 516 21.4.1 program mode...................................................................................................... 516 21.4.2 program-verify mode .......................................................................................... 517 xi 21.4.3 erase mode........................................................................................................... 519 21.4.4 erase-verify mode ............................................................................................... 519 21.4.5 protect modes....................................................................................................... 521 21.4.6 interrupt handling during flash memory programming and erasing ................. 523 21.5 flash memory writer mode (h8/3337sf)........................................................................ 524 21.5.1 writer mode setting ............................................................................................. 524 21.5.2 socket adapter and memory map ....................................................................... 524 21.5.3 operation in writer mode .................................................................................... 525 21.6 flash memory programming and erasing precautions ..................................................... 536 section 22 power-down state .......................................................................................... 539 22.1 overview.................................................................................................................. .......... 539 22.1.1 system control register (syscr) ...................................................................... 540 22.2 sleep mode................................................................................................................ ........ 542 22.2.1 transition to sleep mode ..................................................................................... 542 22.2.2 exit from sleep mode .......................................................................................... 542 22.3 software standby mode .................................................................................................... 5 43 22.3.1 transition to software standby mode.................................................................. 543 22.3.2 exit from software standby mode....................................................................... 543 22.3.3 clock settling time for exit from software standby mode................................ 544 22.3.4 sample application of software standby mode.................................................. 545 22.3.5 application notes................................................................................................. 546 22.4 hardware standby mode ................................................................................................... 54 7 22.4.1 transition to hardware standby mode ................................................................ 547 22.4.2 recovery from hardware standby mode............................................................. 547 22.4.3 timing relationships in hardware standby mode .............................................. 548 section 23 electrical characteristics .............................................................................. 549 23.1 absolute maximum ratings.............................................................................................. 549 23.2 electrical characteristics ................................................................................................ ... 550 23.2.1 dc characteristics................................................................................................ 550 23.2.2 ac characteristics................................................................................................ 561 23.2.3 a/d converter characteristics ............................................................................. 569 23.2.4 d/a converter characteristics (h8/3337 series only)........................................ 570 23.2.5 flash memory characteristics (h8/3337sf only)............................................... 571 23.3 absolute maximum ratings (h8/3337sf low-voltage version).................................... 573 23.4 electrical characteristics (h8/3337sf low-voltage version) ......................................... 574 23.4.1 dc characteristics................................................................................................ 574 23.4.2 ac characteristics................................................................................................ 578 23.4.3 a/d converter characteristics ............................................................................. 583 23.4.4 d/a converter characteristics (h8/3337 series only)........................................ 584 23.4.5 flash memory characteristics.............................................................................. 585 23.5 mcu operational timing.................................................................................................. 58 7 xii 23.5.1 bus timing ........................................................................................................... 587 23.5.2 control signal timing.......................................................................................... 588 23.5.3 16-bit free-running timer timing ..................................................................... 590 23.5.4 8-bit timer timing .............................................................................................. 591 23.5.5 pulse width modulation timer timing ............................................................... 592 23.5.6 serial communication interface timing.............................................................. 593 23.5.7 i/o port timing .................................................................................................... 594 23.5.8 host interface timing (h8/3337 series only) ..................................................... 594 23.5.9 i 2 c bus timing (option) (h8/3337 series only)................................................. 595 23.5.10 external clock output timing ............................................................................. 596 appendix a cpu instruction set ................................................................................... 597 a.1 instruction set list ....................................................................................................... ..... 597 a.2 operation code map......................................................................................................... . 605 a.3 number of states required for execution......................................................................... 607 appendix b interrupt i/o register ................................................................................ 613 b.1 addresses.................................................................................................................. ......... 613 b.1.1 addresses for h8/3337 series .............................................................................. 613 b.1.2 addresses for h8/3397 series .............................................................................. 618 b.2 function ................................................................................................................... .......... 623 appendix c i/o port block diagrams .......................................................................... 680 c.1 port 1 block diagram....................................................................................................... . 680 c.2 port 2 block diagram....................................................................................................... . 681 c.3 port 3 block diagram....................................................................................................... . 682 c.4 port 4 block diagrams ...................................................................................................... 683 c.5 port 5 block diagrams ...................................................................................................... 687 c.6 port 6 block diagrams ...................................................................................................... 690 c.7 port 7 block diagrams ...................................................................................................... 694 c.8 port 8 block diagrams ...................................................................................................... 695 c.9 port 9 block diagrams ...................................................................................................... 701 appendix d port states in each processing state ..................................................... 707 appendix e timing of transition to and recovery from hardware standby mode ............................................................... 709 appendix f option list .................................................................................................... 710 appendix g product code lineup ................................................................................. 712 appendix h package dimensions .................................................................................. 714 1 section 1 overview 1.1 overview the h8/3337 series and the h8/3397 series of single-chip microcomputers feature an h8/300 cpu core and a complement of on-chip supporting modules implementing a variety of system functions. the h8/300 cpu is a high-speed processor with an architecture featuring powerful bit- manipulation instructions, ideally suited for realtime control applications. the on-chip supporting modules implement peripheral functions needed in system configurations. these include rom, ram, four types of timers (a 16-bit free-running timer, 8-bit timers, pwm timers, and a watchdog timer), a serial communication interface (sci), an i 2 c bus interface (option), a host interface (hif), an a/d converter, a d/a converter, and i/o ports. the h8/3397 series is a subset of the h8/3337 series and does not include an i 2 c bus interface, host interface, and d/a converter. the h8/3337 series can operate in single-chip mode or in two expanded modes, depending on the requirements of the application. besides the mask-rom versions of the h8/3337 series, there are ztat versions with on-chip prom, and f-ztat versions with on-chip flash memory. the f-ztat version can be programmed or reprogrammed on-board in application systems. notes: 1. ztat (zero turn-around time) is a trademark of hitachi, ltd. 2. f-ztat (flexible-ztat) is a trademark of hitachi, ltd. the h8/3397 series is only available in a mask-rom version. for applications with ztat, f-ztat, and emulator versions, use the h8/3337 series instead. in such cases, do not access registers of deleted functions. also, do not write 1 to the following bits: hie bit of syscr; iics, iicd, iicx, iice and stac bits of stcr; rams and ram0 bits of wscr. the guaranteed voltage range is different for the f-ztat lh version. lh version general version v cc av cc 3.0 v to 5.5 v 2.7 v to 5.5 v table 1.1 lists the features of the h8/3337 series. 2 table 1.1 features item specification cpu two-way general register configuration ? eight 16-bit registers, or ? sixteen 8-bit registers high-speed operation ? maximum clock rate (?clock): 16 mhz at 5 v, 12mhz at 4 v or 10 mhz at 3 v ? 8- or 16-bit register-register add/subtract: 125 ns (16 mhz), 167 ns (12mhz), 200 ns (10 mhz) ? 8 8-bit multiply: 875 ns (16 mhz), 1167 ns (12mhz), 1400 ns (10 mhz) ? 16 8-bit divide: 875 ns (16 mhz), 1167 ns (12mhz), 1400 ns (10 mhz) streamlined, concise instruction set ? instruction length: 2 or 4 bytes ? register-register arithmetic and logic operations ? mov instruction for data transfer between registers and memory instruction set features ? multiply instruction (8 bits 8 bits) ? divide instruction (16 bits 8 bits) ? bit-accumulator instructions ? register-indirect specification of bit positions memory ? h8/3337y, h8/3397: 60-kbyte rom; 2-kbyte ram ? h8/3336y, h8/3396: 48-kbyte rom; 2-kbyte ram ? h8/3334y, h8/3394: 32-kbyte rom; 1-kbyte ram 16-bit free-running timer (1 channel) ? one 16-bit free-running counter (can also count external events) ? two output-compare lines ? four input capture lines (can be buffered) 8-bit timer (2 channels) each channel has ? one 8-bit up-counter (can also count external events) ? two time constant registers pwm timer (2 channels) ? duty cycle can be set from 0 to 100% ? resolution: 1/250 watchdog timer (wdt) (1 channel) ? overflow can generate a reset or nmi interrupt ? also usable as interval timer 3 item specification serial communication interface (sci) (2 channels) ? asynchronous or synchronous mode (selectable) ? full duplex: can transmit and receive simultaneously ? on-chip baud rate generator i 2 c bus interface (1 channel) [option] ? conforms to philips i 2 c bus interface ? includes single master mode and slave mode host interface (hif) ? 8-bit host interface port ? three host interrupt requests (hirq 1 , hirq 11 , hirq 12 ) ? regular and fast a 20 gate output ? two register sets, each with two data registers and a status register keyboard controller ? controls a matrix-scan keyboard by providing a keyboard scan function with wake-up interrupts and sense ports a/d converter ? 10-bit resolution ? eight channels: single or scan mode (selectable) ? start of a/d conversion can be externally triggered ? sample-and-hold function d/a converter ? 8-bit resolution ? two channels i/o ports ? 74 input/output lines (16 of which can drive leds) ? 8 input-only lines interrupts ? nine external interrupt lines: nmi , irq 0 to irq 7 ? 26 on-chip interrupt sources wait control ? three selectable wait modes operating modes ? expanded mode with on-chip rom disabled (mode 1) ? expanded mode with on-chip rom disabled (mode 1) ? single-chip mode (mode 3) power-down modes ? sleep mode ? software standby mode ? hardware standby mode other features ? on-chip clock pulse generator 4 item specification series lineup part number product name 5-v version (16 mhz) 4-v version (12 mhz) 3-v version (10 mhz) package rom h8/3337y f-ztat hd64f3337yf16 hd64f3337yflh16 hd64f3337yf16 hd64f3337yflh16 80-pin qfp (fp-80a) flash memory (dual-power- hd64f3337ytf16 hd64f3337ytflh16 hd64f3337ytf16 hd64f3337ytflh16 80-pin tqfp (tfp-80c) supply product) hd64f3337ycp16 hd64f3337ycp16 84-pin plcc (cp-84) hd64f3337sf16 hd64f3337sf16 80-pin qfp (fp-80a) flash memory (single-power- hd64f3337stf16 hd64f3337stf16 80-pin tqfp (tfp-80c) supply product) h8/3337y ztat hd6473337yf16 hd6473337yf16 80-pin qfp (fp-80a) prom hd6473337ytf16 hd6473337ytf16 80-pin tqfp (tfp-80c) hd6473337ycp16 hd6473337ycp16 84-pin plcc (cp-84) h8/3337y h8/3397 hd6433337yf16 hd6433337yf12 hd6433397f16 hd6433397f12 hd6433337yvf10 hd6433397vf10 80-pin qfp (fp-80a) mask rom hd6433337ytf16 hd6433337ytf12 hd6433397tf16 hd6433397tf12 hd6433337yvtf10 hd6433397vtf10 80-pin tqfp (tfp-80c) hd6433337ycp16 hd6433337ycp12 hd6433397cp16 hd6433397cp12 hd6433337yvcp10 hd6433397vcp10 84-pin plcc (cp-84) h8/3336y h8/3396 hd6433336yf16 hd6433336yf12 hd6433396f16 hd6433396f12 hd6433336yvf10 hd6433396vf10 80-pin qfp (fp-80a) mask rom hd6433336ytf16 hd6433336ytf12 hd6433396tf16 hd6433396tf12 hd6433336yvtf10 hd6433396vtf10 80-pin tqfp (tfp-80c) hd6433336ycp16 hd6433336ycp12 hd6433396cp16 hd6433396c12 hd6433336yvcp10 hd6433396vcp10 84-pin plcc (cp-84) 5 item specification series lineup part number product name 5-v version (16 mhz) 4-v version (12 mhz) 3-v version (10 mhz) package rom h8/3334y f-ztat hd64f3334yf16 hd64f3334yflh16 hd64f3334yf16 hd64f3334yflh16 80-pin qfp (fp-80a) flash memory (dual-power- hd64f3334ytf16 hd64f3334ytflh16 hd64f3334ytf16 hd64f3334ytflh16 80-pin tqfp (tfp-80c) supply product) hd64f3334ycp16 hd64f3334ycp16 84-pin plcc (cp-84) h8/3334y ztat hd6473334yf16 hd6473334yf16 80-pin qfp (fp-80a) prom hd6473334ytf16 hd6473334ytf16 80-pin tqfp (tfp-80c) hd6473334ycp16 hd6473334ycp16 84-pin plcc (cp-84) h8/3334y h8/3394 hd6433334yf16 hd6433334yf12 hd6433394f16 hd6433394f12 hd6433334yvf10 hd6433394vf10 80-pin qfp (fp-80a) mask rom hd6433334ytf16 hd6433334ytf12 hd6433394tf16 hd6433394tf12 hd6433334yvtf10 hd6433394vtf10 80-pin tqfp (tfp-80c) hd6433334ycp16 hd6433334ycp12 hd6433394cp16 hd6433394cp12 hd6433334yvcp10 hd6433394vcp10 84-pin plcc (cp-84) note: the i 2 c bus interface is an available option. please note the following points regarding this option. in mask rom versions, the y in the part number becomes a w in products in which this optional function is used. example: hd6433337wf, hd6433334wf 6 1.2 block diagram figure 1.1 (a) shows a block diagram of the h8/3337 series. figure 1.1 (b) shows a block diagram of the h8/3397 series. p9 0 / adtrg irq ecs irq eiow irq rd wr as p9 7 / wait cs ior irq iow irq cs irq keyin keyin keyin keyin keyin keyin irq keyin irq keyin res stby nmi figure 1.1 (a) block diagram for h8/3337 series 7 p9 0 / adtrg irq irq irq rd wr as p9 7 / wait irq irq irq keyin keyin keyin keyin keyin keyin irq keyin irq keyin res stby nmi figure 1.1 (b) block diagram for h8/3397 series 8 1.3 pin assignments and functions 1.3.1 pin arrangement figure 1.2 (a) shows the pin arrangement of the fp-80a and tfp-80c packages for the h8/3337 series, and figure 1.2 (b) shows the packages for the h8/3397 series. figure 1.3 (a) shows the pin arrangement of the cp-84 and cg-84 packages for the h8/3337 series, and figure 1.3 (b) shows the packages for the h8/3397 series. p1 4 /a 4 p1 5 /a 5 p1 6 /a 6 p1 7 /a 7 v ss p2 0 /a 8 p2 1 /a 9 p2 2 /a 10 p2 3 /a 11 p2 4 /a 12 p2 5 /a 13 p2 6 /a 14 p2 7 /a 15 v cc p4 7 /pw 1 p4 6 /pw 0 p4 5 /tmri 1 /hirq 12 p4 4 /tmo 1 /hirq 1 p4 3 /tmci 1 /hirq 11 p4 2 /tmri 0 res nmi stby wait /p9 6 as wr rd irq eiow irq adtrg ecs irq cs ior irq iow irq cs irq keyin irq keyin irq keyin keyin keyin keyin keyin keyin stby figure 1.2 (a) pin arrangement for h8/3337 series (fp-80a, tfp-80c, top view) 9 p1 4 /a 4 p1 5 /a 5 p1 6 /a 6 p1 7 /a 7 v ss p2 0 /a 8 p2 1 /a 9 p2 2 /a 10 p2 3 /a 11 p2 4 /a 12 p2 5 /a 13 p2 6 /a 14 p2 7 /a 15 v cc p4 7 /pw 1 p4 6 /pw 0 p4 5 /tmri 1 p4 4 /tmo 1 p4 3 /tmci 1 p4 2 /tmri 0 res nmi stby wait /p9 6 as wr rd irq irq a dtrg irq irq irq irq keyin irq keyin irq keyin keyin keyin keyin keyin keyin figure 1.2 (b) pin arrangement for h8/3397 series (fp-80a, tfp-80c, top view) 10 p1 4 /a 4 p1 5 /a 5 p1 6 /a 6 p1 7 /a 7 v ss p2 0 /a 8 p2 1 /a 9 p2 2 /a 10 p2 3 /a 11 p2 4 /a 12 v ss p2 5 /a 13 p2 6 /a 14 p2 7 /a 15 v cc p4 7 /pw 1 p4 6 /pw 0 p4 5 /tmri 1 /hirq 12 p4 4 /tmo 1 /hirq 1 p4 3 /tmci 1 /hirq 11 p4 2 /tmri 0 res nmi stby wait /p9 6 as wr rd irq eiow irq adtrg ecs irq cs ior irq iow irq cs irq keyin irq keyin irq keyin keyin keyin keyin keyin keyin stby figure 1.3 (a) pin arrangement for h8/3337 series (cp-84, cg-84, top view) 11 p1 4 /a 4 p1 5 /a 5 p1 6 /a 6 p1 7 /a 7 v ss p2 0 /a 8 p2 1 /a 9 p2 2 /a 10 p2 3 /a 11 p2 4 /a 12 v ss p2 5 /a 13 p2 6 /a 14 p2 7 /a 15 v cc p4 7 /pw 1 p4 6 /pw 0 p4 5 /tmri 1 p4 4 /tmo 1 p4 3 /tmci 1 p4 2 /tmri 0 res nmi stby wait /p9 6 as wr rd irq irq a dtrg irq keyin irq keyin irq keyin keyin keyin keyin keyin keyin irq irq irq figure 1.3 (b) pin arrangement for h8/3397 series (cp-84, top view) 12 1.3.2 pin functions pin assignments in each operating mode: table 1.2 (a) and table 1.2 (b) lists the assignments of the pins of the fp-80a, tfp-80, cp-84, and cg-84 packages in each operating mode. table 1.2 (a) pin assignments for h8/3337 series in each operating mode pin no. expanded modes single-chip mode flash mode 3 eprom memory fp-80a, tfp-80c cp-84, cg-84 mode 1 mode 2 hif disabled hif enabled writer mode writer mode 112 res res res res res nmi nmi nmi nmi stby stby stby stby 24 v ss v ss v ss v ss v ss v ss 13 25 p9 7 / wait wait p9 6 / p9 6 / nc nc 15 27 as as wr wr rd rd we irq irq irq irq pgm irq eiow irq irq adtrg ecs irq keyin keyin keyin keyin 13 pin no. expanded modes single-chip mode flash mode 3 eprom memory fp-80a, tfp-80c cp-84, cg-84 mode 1 mode 2 hif disabled hif enabled writer mode writer mode 22 34 p6 1 /ftoa/ keyin keyin keyin keyin keyin keyin keyin keyin keyin keyin keyin keyin keyin keyin keyin keyin keyin keyin keyin keyin irq keyin irq keyin irq keyin irq keyin irq keyin irq keyin irq keyin irq keyin 41 v ss v ss v ss v ss v ss v ss 29 42 av cc av cc av cc av cc v cc v cc 30 43 p7 0 /an 0 p7 0 /an 0 p7 0 /an 0 p7 0 /an 0 nc nc 31 44 p7 1 /an 1 p7 1 /an 1 p7 1 /an 1 p7 1 /an 1 nc nc 32 45 p7 2 /an 2 p7 2 /an 2 p7 2 /an 2 p7 2 /an 2 nc nc 33 46 p7 3 /an 3 p7 3 /an 3 p7 3 /an 3 p7 3 /an 3 nc nc 34 47 p7 4 /an 4 p7 4 /an 4 p7 4 /an 4 p7 4 /an 4 nc nc 35 48 p7 5 /an 5 p7 5 /an 5 p7 5 /an 5 p7 5 /an 5 nc nc 36 49 p7 6 /an 6 /da 0 p7 6 /an 6 /da 0 p7 6 /an 6 /da 0 p7 6 /an 6 /da 0 nc nc 37 50 p7 7 /an 7 /da 1 p7 7 /an 7 /da 1 p7 7 /an 7 /da 1 p7 7 /an 7 /da 1 nc nc 38 51 av ss av ss av ss av ss v ss v ss 39 52 p4 0 /tmci 0 p4 0 /tmci 0 p4 0 /tmci 0 p4 0 /tmci 0 nc nc 40 53 p4 1 /tmo 0 p4 1 /tmo 0 p4 1 /tmo 0 p4 1 /tmo 0 nc nc 41 54 p4 2 /tmri 0 p4 2 /tmri 0 p4 2 /tmri 0 p4 2 /tmri 0 nc nc 42 55 p4 3 /tmci 1 / hirq 11 * p4 3 /tmci 1 / hirq 11 * p4 3 /tmci 1 hirq 11 / tmci 1 nc nc 14 pin no. expanded modes single-chip mode flash mode 3 eprom memory fp-80a, tfp-80c cp-84, cg-84 mode 1 mode 2 hif disabled hif enabled writer mode writer mode 43 56 p4 4 /tmo 1 / hirq 1 * p4 4 /tmo 1 / hirq 1 * p4 4 /tmo 1 hirq 1 /tmo 1 nc nc 44 57 p4 5 /tmri 1 / hirq 12 * p4 5 /tmri 1 / hirq 12 * p4 5 /tmri 1 hirq 12 / tmri 1 nc nc 45 58 p4 6 /pw 0 p4 6 /pw 0 p4 6 /pw 0 p4 6 /pw 0 nc nc 46 59 p4 7 /pw 1 p4 7 /pw 1 p4 7 /pw 1 p4 7 /pw 1 nc nc 47 60 v cc v cc v cc v cc v cc v cc 48 61 a 15 p2 7 /a 15 p2 7 p2 7 ce ce 64 v ss v ss v ss v ss v ss v ss 51 65 a 12 p2 4 /a 12 p2 4 p2 4 ea 12 fa 12 52 66 a 11 p2 3 /a 11 p2 3 p2 3 ea 11 fa 11 53 67 a 10 p2 2 /a 10 p2 2 p2 2 ea 10 fa 10 54 68 a 9 p2 1 /a 9 p2 1 p2 1 oe oe 15 pin no. expanded modes single-chip mode flash mode 3 eprom memory fp-80a, tfp-80c cp-84, cg-84 mode 1 mode 2 hif disabled hif enabled writer mode writer mode 69 83 d 4 d 4 p3 4 hdb 4 eo 4 fo 4 70 84 d 5 d 5 p3 5 hdb 5 eo 5 fo 5 71 1 d 6 d 6 p3 6 hdb 6 eo 6 fo 6 2v ss v ss v ss v ss v ss v ss 72 3 d 7 d 7 p3 7 hdb 7 eo 7 fo 7 73 4 v ss v ss v ss v ss v ss v ss 74 5 p8 0 /ha 0 * p8 0 /ha 0 * p8 0 ha 0 nc nc 75 6 p8 1 /ga 20 * p8 1 /ga 20 * p8 1 p8 1 /ga 20 nc nc 76 7 p8 2 /cs 1 * p8 2 /cs 1 * p8 2 cs ior ior ior irq iow irq irq cs irq irq irq irq irq 16 table 1.2 (b) pin assignments for h8/3397 series in each operating mode pin no. expanded modes single-chip mode fp-80a, tfp-80c cp-84, cg-84 mode 1 mode 2 mode 3 112 res res res nmi nmi nmi stby stby stby 24 v ss v ss v ss 13 25 p9 7 / wait wait p9 6 / 15 27 as as wr wr rd rd irq irq irq irq irq irq irq adtrg irq adtrg irq adtrg keyin keyin keyin keyin keyin keyin keyin keyin keyin keyin keyin keyin keyin keyin keyin keyin keyin keyin irq keyin irq keyin irq keyin 17 pin no. expanded modes single-chip mode fp-80a, tfp-80c cp-84, cg-84 mode 1 mode 2 mode 3 28 40 p6 7 / irq keyin irq keyin irq keyin 41 v ss v ss v ss 29 42 av cc av cc av cc 30 43 p7 0 /an 0 p7 0 /an 0 p7 0 /an 0 31 44 p7 1 /an 1 p7 1 /an 1 p7 1 /an 1 32 45 p7 2 /an 2 p7 2 /an 2 p7 2 /an 2 33 46 p7 3 /an 3 p7 3 /an 3 p7 3 /an 3 34 47 p7 4 /an 4 p7 4 /an 4 p7 4 /an 4 35 48 p7 5 /an 5 p7 5 /an 5 p7 5 /an 5 36 49 p7 6 /an 6 p7 6 /an 6 p7 6 /an 6 37 50 p7 7 /an 7 p7 7 /an 7 p7 7 /an 7 38 51 av ss av ss av ss 39 52 p4 0 /tmci 0 p4 0 /tmci 0 p4 0 /tmci 0 40 53 p4 1 /tmo 0 p4 1 /tmo 0 p4 1 /tmo 0 41 54 p4 2 /tmri 0 p4 2 /tmri 0 p4 2 /tmri 0 42 55 p4 3 /tmci 1 p4 3 /tmci 1 p4 3 /tmci 1 43 56 p4 4 /tmo 1 p4 4 /tmo 1 p4 4 /tmo 1 44 57 p4 5 /tmri 1 p4 5 /tmri 1 p4 5 /tmri 1 45 58 p4 6 /pw 0 p4 6 /pw 0 p4 6 /pw 0 46 59 p4 7 /pw 1 p4 7 /pw 1 p4 7 /pw 1 47 60 v cc v cc v cc 48 61 a 15 p2 7 /a 15 p2 7 49 62 a 14 p2 6 /a 14 p2 6 50 63 a 13 p2 5 /a 13 p2 5 64 v ss v ss v ss 51 65 a 12 p2 4 /a 12 p2 4 52 66 a 11 p2 3 /a 11 p2 3 53 67 a 10 p2 2 /a 10 p2 2 54 68 a 9 p2 1 /a 9 p2 1 18 pin no. expanded modes single-chip mode fp-80a, tfp-80c cp-84, cg-84 mode 1 mode 2 mode 3 55 69 a 8 p2 0 /a 8 p2 0 56 70 v ss v ss v ss 57 71 a 7 p1 7 /a 7 p1 7 58 72 a 6 p1 6 /a 6 p1 6 59 73 a 5 p1 5 /a 5 p1 5 60 74 a 4 p1 4 /a 4 p1 4 61 75 a 3 p1 3 /a 3 p1 3 62 76 a 2 p1 2 /a 2 p1 2 63 77 a 1 p1 1 /a 1 p1 1 64 78 a 0 p1 0 /a 0 p1 0 65 79 d 0 d 0 p3 0 66 80 d 1 d 1 p3 1 67 81 d 2 d 2 p3 2 68 82 d 3 d 3 p3 3 69 83 d 4 d 4 p3 4 70 84 d 5 d 5 p3 5 71 1 d 6 d 6 p3 6 2v ss v ss v ss 72 3 d 7 d 7 p3 7 73 4 v ss v ss v ss 74 5 p8 0 p8 0 p8 0 75 6 p8 1 p8 1 p8 1 76 7 p8 2 p8 2 p8 2 77 8 p8 3 p8 3 p8 3 78 9 p8 4 / irq irq irq irq irq irq irq irq irq 19 pin functions: table 1.3 gives a concise description of the function of each pin. table 1.3 pin functions pin no. type symbol fp-80a, tfp-80c cp-84, cg-84 i/o name and function power v cc 8, 47 19, 60 i power: connected to the power supply. connect both v cc pins to the system power supply. v ss 12, 56, 73 2, 4, 23, 24, 41, 64, 70 i ground: connected to ground (0 v). connect all v ss pins to system ground (0 v). clock xtal 2 13 i crystal: connected to a crystal oscillator. the crystal frequency should be the same as the desired system clock frequency. if an external clock is input at the extal pin, a reverse- phase clock should be input at the xtal pin. extal 3 14 i external crystal: connected to a crystal oscillator or external clock. the frequency of the external clock should be the same as the desired system clock frequency. see section 6.2, oscillator circuit, for examples of connections to a crystal and external clock. 14 26 o system clock: supplies the system clock to peripheral devices. system control res reset: a low input causes the chip to reset. stby standby: a transition to the hardware standby mode (a power-down state) occurs when a low input is received at the stby address bus: address output pins. data bus d 7 to d 0 72 to 65 3, 1, 84 to 79 i/o data bus: 8-bit bidirectional data bus. 20 pin no. type symbol fp-80a, tfp-80c cp-84, cg-84 i/o name and function bus control wait wait: requests the cpu to insert wait states into the bus cycle when an external address is accessed. rd read: goes low to indicate that the cpu is reading an external address. wr write: goes low to indicate that the cpu is writing to an external address. as address strobe: goes low to indicate that there is a valid address on the address bus. interrupt signals nmi nonmaskable interrupt: highest- priority interrupt request. the nmieg bit in the system control register (syscr) determines whether the interrupt is recognized at the rising or falling edge of the nmi input. irq irq interrupt request 0 to 7: maskable interrupt request pins. operating control md 1 md 0 4, 5 15, 16 i mode: input pins for setting the mcu mode operating mode according to the table below. md 1 md 0 mode description 0 0 mode 0 illegal setting * 0 1 mode 1 expanded mode with on-chip rom disabled 1 0 mode 2 expanded mode with on-chip rom enabled 1 1 mode 3 single-chip mode note: * in the h8/3337sf (s-mask model, single-power-supply on-chip flash memory version), the settings md 1 = md 0 = 0 are used when boot mode is set. for details, see section 21.3, on-board programming modes. do not change the mode pin settings while the chip is operating. 21 pin no. type symbol fp-80a, tfp-80c cp-84, cg-84 i/o name and function 16-bit free- running timer (frt) ftoa ftob 22 27 34 39 o frt output compare a and b: output pins controlled by comparators a and b of the free-running timer. ftci 21 33 i frt counter clock input: input pin for an external clock signal for the free- running timer. ftia to ftid 23 to 26 35 to 38 i frt input capture a to d: input capture pins for the free-running timer. 8-bit timer tmo 0 tmo 1 40 43 53 56 o 8-bit timer output (channels 0 and 1): compare-match output pins for the 8-bit timers. tmci 0 tmci 1 39 42 52 55 i 8-bit timer counter clock input (channels 0 and 1): external clock input pins for the 8-bit timer counters. tmri 0 tmri 1 41 44 54 57 i 8-bit timer counter reset input (channels 0 and 1): a high input at these pins resets the 8-bit timer counters. pwm timer pw 0 pw 1 45 46 58 59 o pwm timer output (channels 0 and 1): pulse-width modulation timer output pins. serial communi- cation interface (sci) txd 0 txd 1 11 78 22 9 o transmit data (channels 0 and 1): data output pins for the serial communication interface. rxd 0 rxd 1 10 79 21 10 i receive data (channels 0 and 1): data input pins for the serial communication interface. sck 0 sck 1 9 80 20 11 i/o serial clock (channels 0 and 1): input/output pins for the serial clock. 22 pin no. type symbol fp-80a, tfp-80c cp-84, cg-84 i/o name and function host interface (hif) (h8/3337 series only) hdb 0 to hdb 7 65 to 72 79 to 84, 1, 3 i/o host interface data bus: 8-bit bidirectional bus by which a host processor accesses the host interface. cs cs chip select 1 and 2: input pins for selecting host interface channels 1 and 2. ior i/o read: read strobe input pin for the host interface. iow i/o write: write strobe input pin for the host interface. ha 0 74 5 i command/data: input pin indicating data access or command access. ga 20 75 6 o gate a 20 : a 20 gate control signal output pin. hirq 1 hirq 11 hirq 12 43 42 44 56 55 57 o host interrupts 1, 11, and 12: output pins for interrupt request signals to the host processor. keyboard control keyin keyin keyboard input: input pins from a matrix keyboard. (keyboard scan signals are normally output from p1 0 to p1 7 and p2 0 to p2 7 , allowing a maximum 16 ecs host chip select 2: input pin for selecting host interface channel 2. stac bit is 1 in stcr) (h8/3337 series only) eiow i/o write: write strobe input pin for the host interface. a/d converter an 7 to an 0 37 to 30 50 to 43 i analog input: analog signal input pins for the a/d converter. adtrg a/d trigger: external trigger input for starting the a/d converter. d/a converter (h8/3337 series only) da 0 da 1 36 37 49 50 o analog output: analog signal output pins for the d/a converter. 23 pin no. type symbol fp-80a, tfp-80c cp-84, cg-84 i/o name and function a/d and d/a converters av cc 29 42 i analog reference voltage: reference voltage pin for the a/d and d/a converters. if the a/d and d/a converters are not used, connect av cc to the system power supply. av ss 38 51 i analog ground: ground pin for the a/d and d/a converters. connect to system ground (0 v). flash memory [h8/3334yf-ztat] [h8/3337yf-ztat] fv pp 718i programming power supply for on- board programming: connect to a flash memory programming power supply (+12 v). i 2 c bus interface (option) scl 80 11 i/o i 2 c clock i/o: input/output pin for i 2 c clock. features a bus drive function. (h8/3337 series only) sda 13 25 i/o i 2 c data i/o: input/output pin for i 2 c data. features a bus drive function. i/o ports p1 7 to p1 0 57 to 64 71 to 78 i/o port 1: an 8-bit input/output port with programmable mos input pull-ups and led driving capability. the direction of each bit can be selected in the port 1 data direction register (p1ddr). p2 7 to p2 0 48 to 55 61 to 63, 65 to 69 i/o port 2: an 8-bit input/output port with programmable mos input pull-ups and led driving capability. the direction of each bit can be selected in the port 2 data direction register (p2ddr). p3 7 to p3 0 72 to 65 3, 1, 84 to 79 i/o port 3: an 8-bit input/output port with programmable mos input pull-ups. the direction of each bit can be selected in the port 3 data direction register (p3ddr). p4 7 to p4 0 46 to 39 59 to 52 i/o port 4: an 8-bit input/output port. the direction of each bit can be selected in the port 4 data direction register (p4ddr). p5 2 to p5 0 9 to 11 20 to 22 i/o port 5: a 3-bit input/output port. the direction of each bit can be selected in the port 5 data direction register (p5ddr). 24 pin no. type symbol fp-80a, tfp-80c cp-84, cg-84 i/o name and function i/o ports p6 7 to p6 0 28 to 21 40 to 33 i/o port 6: an 8-bit input/output port with programmable mos input pull-ups. the direction of each bit can be selected in the port 6 data direction register (p6ddr). p7 7 to p7 0 37 to 30 50 to 43 i port 7: an 8-bit input port. p8 6 to p8 0 80 to 74 11 to 5 i/o port 8: a 7-bit input/output port. the direction of each bit can be selected in the port 8 data direction register (p8ddr). p9 7 to p9 0 13 to 20 25 to 32 i/o port 9: an 8-bit input/output port. the direction of each bit (except for p9 6 ) can be selected in the port 9 data direction register (p9ddr). note: in this chip, except for the s-mask model (single-power-supply specification), the same pin is used for stby and fv pp . when this pin is driven low, a transition is made to hardware standby mode. this happens not only in the normal operating modes (modes 1, 2, and 3), but also when programming the flash memory with a prom writer. when using a prom programmer to program dual-power-supply flash memory, therefore, the prom programmer specifications should provide for this pin to be held at the v cc level except when programming (fv pp = 12 v). 25 section 2 cpu 2.1 overview the h8/300 cpu is a fast central processing unit with eight 16-bit general registers (also configurable as 16 eight-bit registers) and a concise instruction set designed for high-speed operation. 2.1.1 features the main features of the h8/300 cpu are listed below. ? two-way register configuration ? sixteen 8-bit general registers, or ? eight 16-bit general registers ? instruction set with 57 basic instructions, including: ? multiply and divide instructions ? powerful bit-manipulation instructions ? eight addressing modes ? register direct (rn) ? register indirect (@rn) ? register indirect with displacement (@(d:16, rn)) ? register indirect with post-increment or pre-decrement (@rn+ or @?n) ? absolute address (@aa:8 or @aa:16) ? immediate (#xx:8 or #xx:16) ? pc-relative (@(d:8, pc)) ? memory indirect (@@aa:8) ? maximum 64-kbyte address space ? high-speed operation ? all frequently-used instructions are executed in two to four states ? maximum clock rate (?clock): 16 mhz at 5 v, 12 mhz at 4 v or 10 mhz at 3 v ? 8- or 16-bit register-register add or subtract: 125 ns (16 mhz), 167 ns (12 mhz), 200 ns (10 mhz) ? 8 8-bit multiply: 875 ns (16 mhz), 1167 ns (12 mhz), 1400 ns (10 mhz) ? 16 8-bit divide: 875 ns (16 mhz), 1167 ns (12 mhz), 1400 ns (10 mhz) ? power-down mode ? sleep instruction 26 2.1.2 address space the h8/300 cpu supports an address space with a maximum size of 64 kbytes for program code and data combined. the memory map differs depending on the mode (mode 1, 2, or 3). for details, see section 3.4, address space map in each operating mode. 2.1.3 register configuration figure 2.1 shows the internal register structure of the h8/300 cpu. there are two groups of registers: the general registers and control registers. 7070 15 0 pc r0h r1h r2h r3h r4h r5h r6h r7h r0l r1l r2l r3l r4l r5l r6l r7l (sp) sp: stack pointer pc: program counter ccr: condition code register carry flag overflow flag zero flag negative flag half-carry flag interrupt mask bit user bit user bit ccr i u h u n z v c general registers (rn) control registers 753210 64 figure 2.1 cpu registers 27 2.2 register descriptions 2.2.1 general registers all the general registers can be used as both data registers and address registers. when used as address registers, the general registers are accessed as 16-bit registers (r0 to r7). when used as data registers, they can be accessed as 16-bit registers, or the high and low bytes can be accessed separately as 8-bit registers (r0h to r7h and r0l to r7l). r7 also functions as the stack pointer, used implicitly by hardware in processing interrupts and subroutine calls. in assembly-language coding, r7 can also be denoted by the letters sp. as indicated in figure 2.2, r7 (sp) points to the top of the stack. unused area stack area sp (r7) figure 2.2 stack pointer 2.2.2 control registers the cpu control registers include a 16-bit program counter (pc) and an 8-bit condition code register (ccr). (1) program counter (pc): this 16-bit register indicates the address of the next instruction the cpu will execute. each instruction is accessed in 16 bits (1 word), so the least significant bit of the pc is ignored (always regarded as 0). (2) condition code register (ccr): this 8-bit register contains internal status information, including carry (c), overflow (v), zero (z), negative (n), and half-carry (h) flags and the interrupt mask bit (i). bit 7?nterrupt mask bit (i): when this bit is set to 1, all interrupts except nmi are masked. this bit is set to 1 automatically by a reset and at the start of interrupt handling. bit 6?ser bit (u): this bit can be written and read by software (using the ldc, stc, andc, orc, and xorc instructions). 28 bit 5?alf-carry flag (h): this flag is set to 1 when the add.b, addx.b, sub.b, subx.b, neg.b, or cmp.b instruction causes a carry or borrow out of bit 3, and is cleared to 0 otherwise. similarly, it is set to 1 when the add.w, sub.w, or cmp.w instruction causes a carry or borrow out of bit 11, and cleared to 0 otherwise. it is used implicitly in the daa and das instructions. bit 4?ser bit (u): this bit can be written and read by software (using the ldc, stc, andc, orc, and xorc instructions). bit 3?egative flag (n): this flag indicates the most significant bit (sign bit) of the result of an instruction. bit 2?ero flag (z): this flag is set to 1 to indicate a zero result and cleared to 0 to indicate a nonzero result. bit 1?verflow flag (v): this flag is set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. bit 0?arry flag (c): this flag is used by: ? add and subtract instructions, to indicate a carry or borrow at the most significant bit of the result ? shift and rotate instructions, to store the value shifted out of the most significant or least significant bit ? bit manipulation and bit load instructions, as a bit accumulator the ldc, stc, andc, orc, and xorc instructions enable the cpu to load and store the ccr, and to set or clear selected bits by logic operations. the n, z, v, and c flags are used in conditional branching instructions (bcc). for the action of each instruction on the flag bits, see the h8/300 series programming manual . 2.2.3 initial register values when the cpu is reset, the program counter (pc) is loaded from the vector table and the interrupt mask bit (i) in the ccr is set to 1. the other ccr bits and the general registers are not initialized. in particular, the stack pointer (r7) is not initialized. the stack pointer and ccr should be initialized by software, by the first instruction executed after a reset. 29 2.3 data formats the h8/300 cpu can process 1-bit data, 4-bit (bcd) data, 8-bit (byte) data, and 16-bit (word) data. ? bit manipulation instructions operate on 1-bit data specified as bit n (n = 0, 1, 2, ..., 7) in a byte operand. ? all arithmetic and logic instructions except adds and subs can operate on byte data. ? the daa and das instruction perform decimal arithmetic adjustments on byte data in packed bcd form. each nibble of the byte is treated as a decimal digit. ? the mov.w, add.w, sub.w, cmp.w, adds, subs, mulxu (8 bits 8 bits), and divxu (16 bits 8 bits) instructions operate on word data. 30 2.3.1 data formats in general registers data of all the sizes above can be stored in general registers as shown in figure 2.3. 76543210 don t care data type register no. data format 70 1-bit data rnh 765432 10 don? care 70 1-bit data rnl msb lsb don? care 70 byte data rnh byte data rnl word data rn 4-bit bcd data rnh 4-bit bcd data rnl legend: rnh: rnl: msb: lsb: upper digit of general register lower digit of general register most significant bit least significant bit msb lsb don? care 70 msb lsb 15 0 upper digit lower digit don? care 70 3 4 don? care upper digit lower digit 70 3 4 figure 2.3 register data formats 31 2.3.2 memory data formats figure 2.4 indicates the data formats in memory. word data stored in memory must always begin at an even address. in word access the least significant bit of the address is regarded as 0. if an odd address is specified, no address error occurs but the access is performed at the preceding even address. this rule affects mov.w instructions and branching instructions, and implies that only even addresses should be stored in the vector table. data format 76543210 address data type 70 address n msb lsb msb lsb upper 8 bits lower 8 bits msb lsb ccr ccr * msb lsb msb lsb address n even address odd address even address odd address even address odd address 1-bit data byte data word data byte data (ccr) on stack word data on stack note: * ignored on return legend: ccr: condition code register figure 2.4 memory data formats when the stack is addressed by register r7, it must always be accessed a word at a time. when the ccr is pushed on the stack, two identical copies of the ccr are pushed to make a complete word. when they are restored, the lower byte is ignored. 32 2.4 addressing modes 2.4.1 addressing mode the h8/300 cpu supports eight addressing modes. each instruction uses a subset of these addressing modes. table 2.1 addressing modes no. addressing mode symbol (1) register direct rn (2) register indirect @rn (3) register indirect with displacement @(d:16, rn) (4) register indirect with post-increment register indirect with pre-decrement @rn+ @ rn (5) absolute address @aa:8 or @aa:16 (6) immediate #xx:8 or #xx:16 (7) program-counter-relative @(d:8, pc) (8) memory indirect @@aa:8 (1) register direct?n: the register field of the instruction specifies an 8- or 16-bit general register containing the operand. in most cases the general register is accessed as an 8-bit register. only the mov.w, add.w, sub.w, cmp.w, adds, subs, mulxu (8 bits 8 bits), and divxu (16 bits 8 bits) instructions have 16-bit operands. (2) register indirect?rn: the register field of the instruction specifies a 16-bit general register containing the address of the operand. (3) register indirect with displacement?(d:16, rn): this mode, which is used only in mov instructions, is similar to register indirect but the instruction has a second word (bytes 3 and 4) which is added to the contents of the specified general register to obtain the operand address. for the mov.w instruction, the resulting address must be even. (4) register indirect with post-increment or pre-decrement?rn+ or @?n: ? register indirect with post-increment @rn+ the @rn+ mode is used with mov instructions that load registers from memory. it is similar to the register indirect mode, but the 16-bit general register specified in the register field of the instruction is incremented after the operand is accessed. the size of the increment is 1 or 2 depending on the size of the operand: 1 for mov.b; 2 for mov.w. for mov.w, the original contents of the 16-bit general register must be even. 33 ? register indirect with pre-decrement @ rn the @ rn mode is used with mov instructions that store register contents to memory. it is similar to the register indirect mode, but the 16-bit general register specified in the register field of the instruction is decremented before the operand is accessed. the size of the decrement is 1 or 2 depending on the size of the operand: 1 for mov.b; 2 for mov.w. for mov.w, the original contents of the 16-bit general register must be even. (5) absolute address?aa:8 or @aa:16: the instruction specifies the absolute address of the operand in memory. the mov.b instruction uses an 8-bit absolute address of the form h'ffxx. the upper 8 bits are assumed to be 1, so the possible address range is h'ff00 to h'ffff (65280 to 65535). the mov.b, mov.w, jmp, and jsr instructions can use 16-bit absolute addresses. (6) immediate?xx:8 or #xx:16: the instruction contains an 8-bit operand in its second byte, or a 16-bit operand in its third and fourth bytes. only mov.w instructions can contain 16-bit immediate values. the adds and subs instructions implicitly contain the value 1 or 2 as immediate data. some bit manipulation instructions contain 3-bit immediate data (#xx:3) in the second or fourth byte of the instruction, specifying a bit number. (7) program-counter-relative?(d:8, pc): this mode is used to generate branch addresses in the bcc and bsr instructions. an 8-bit value in byte 2 of the instruction code is added as a sign-extended value to the program counter contents. the result must be an even number. the possible branching range is 126 to +128 bytes ( 63 to +64 words) from the current address. (8) memory indirect?@aa:8: this mode can be used by the jmp and jsr instructions. the second byte of the instruction code specifies an 8-bit absolute address from h'0000 to h'00ff (0 to 255). the word located at this address contains the branch address. the upper 8 bits of the absolute address are 0 (h'00), thus the branch address is limited to values from 0 to 255 (h'0000 to h'00ff). note that some of the addresses in this range are also used in the vector table. refer to section 3.4, address space map in each operating mode. if an odd address is specified as a branch destination or as the operand address of a mov.w instruction, the least significant bit is regarded as 0, causing word access to be performed at the address preceding the specified address. see section 2.3.2, memory data formats, for further information. 34 2.4.2 calculation of effective address table 2.2 shows how the h8/300 calculates effective addresses in each addressing mode. arithmetic, logic, and shift instructions use register direct addressing (1). the add.b, addx.b, subx.b, cmp.b, and.b, or.b, and xor.b instructions can also use immediate addressing (6). the mov instruction uses all the addressing modes except program-counter relative (7) and memory indirect (8). bit manipulation instructions use register direct (1), register indirect (2), or 8-bit absolute (5) addressing to identify a byte operand, and 3-bit immediate addressing to identify a bit within the byte. the bset, bclr, bnot, and btst instructions can also use register direct addressing (1) to identify the bit. 35 table 2.2 effective address calculation no. addressing mode and instruction format effective address calculation effective address 1 register direct, rn operands are contained in registers regm and regn op regm regn 87 3 40 15 regm 30 regn 30 2 op reg 76 3 40 15 register indirect, @rn 16-bit register contents 0 15 0 15 3 register indirect with displacement, @(d:16, rn) op reg 76 3 40 15 disp 0 15 disp 0 15 16-bit register contents 4 op reg 76 3 40 15 register indirect with post-increment, @rn+ op reg 76 3 40 15 register indirect with pre-decrement, @ rn note: * 1 for a byte operand, 2 for a word operand 0 15 1 or 2 * 1 or 2 * 0 15 0 15 0 15 16-bit register contents 16-bit register contents 36 no. addressing mode and instruction format effective address calculation effective address 5 absolute address @aa:8 @aa:16 op 87 0 15 0 15 abs h'ff 87 0 15 0 15 abs op 6 op 0 15 imm #xx:16 op 87 0 15 imm immediate #xx:8 operand is 1- or 2-byte immediate data 7 op disp 70 15 pc-relative @(d:8, pc) pc contents 0 15 0 15 8 sign extension disp 37 no. addressing mode and instruction format effective address calculation effective address 8 memory indirect, @@aa:8 op 87 0 15 memory contents (16 bits) 0 15 abs h'00 87 0 15 legend: reg, regm, regn: register field op: operation field disp: displacement imm: immediate data abs: absolute address 38 2.5 instruction set the h8/300 cpu has 57 types of instructions, which are classified by function in table 2.3. table 2.3 instruction classification function instructions types data transfer mov, movtpe * 3 , movfpe * 3 , push * 1 , pop * 1 3 arithmetic operations add, sub, addx, subx, inc, dec, adds, subs, daa, das, mulxu, divxu, cmp, neg 14 logic operations and, or, xor, not 4 shift shal, shar, shll, shlr, rotl, rotr, rotxl, rotxr 8 bit manipulation bset, bclr, bnot, btst, band, biand, bor, 14 bior, bxor, bixor, bld, bild, bst, bist branch bcc * 2 , jmp, bsr, jsr, rts 5 system control rte, sleep, ldc, stc, andc, orc, xorc, nop 8 block data transfer eepmov 1 total 57 notes: * 1 push rn is equivalent to mov.w rn, @ sp. pop rn is equivalent to mov.w @sp+, rn. * 2 bcc is a conditional branch instruction in which cc represents a condition code. * 3 not supported by the h8/3337 series and h8/3397 series. 39 the following sections give a concise summary of the instructions in each category, and indicate the bit patterns of their object code. the notation used is defined next. operation notation rd general register (destination) rs general register (source) rn general register (ead) destination operand (eas) source operand sp stack pointer pc program counter ccr condition code register n n (negative) flag of ccr z z (zero) flag of ccr v v (overflow) flag of ccr c c (carry) flag of ccr #imm immediate data #xx:3 3-bit immediate data #xx:8 8-bit immediate data #xx:16 16-bit immediate data disp displacement + addition subtraction not (logical complement) 40 2.5.1 data transfer instructions table 2.4 describes the data transfer instructions. figure 2.5 shows their object code formats. table 2.4 data transfer instructions instruction size * function mov b/w (eas) rn, and @rn+ addressing modes are available for byte or word data. the @aa:8 addressing mode is available for byte data only. the @ r7 and @r7+ modes require word operands. do not specify byte size for these two modes. movtpe b not supported by the h8/3337 series and h8/3397 series. movfpe b not supported by the h8/3337 series and h8/3397 series. push w rn sp pushes a 16-bit general register onto the stack. equivalent to mov.w rn, @ sp. pop w @sp+ * size: operand size b: byte w: word 41 15 0 87 op rm rn mov rm rm 15 0 87 op rn abs @aa:8 figure 2.5 data transfer instruction codes 42 2.5.2 arithmetic operations table 2.5 describes the arithmetic instructions. see figure 2.6 in section 2.5.4, shift operations, for their object codes. table 2.5 arithmetic instructions instruction size * function add sub b/w rd rs, rd #imm compares data in a general register with data in another general register or with immediate data. word data can be compared only between two general registers. neg b 0 rd s complement (arithmetic complement) of data in a general register. note: * size: operand size b: byte w: word 43 2.5.3 logic operations table 2.6 describes the four instructions that perform logic operations. see figure 2.6 in section 2.5.4, shift operations, for their object codes. table 2.6 logic operation instructions instruction size * function and b rd (rd) s complement (logical complement) of general register contents. note: * size: operand size b: byte 2.5.4 shift operations table 2.7 describes the eight shift instructions. figure 2.6 shows the object code formats of the arithmetic, logic, and shift instructions. table 2.7 shift instructions instruction size * function shal b rd shift * size: operand size b: byte 44 15 0 87 op rm rn add, sub, cmp, addx, subx (rm) legend: op: rm, rn: imm: operation field register field immediate data 15 0 87 op rn adds, subs, inc, dec, daa, das, neg, not 15 0 87 op rn mulxu, divxu rm 15 0 87 rn imm add, addx, subx, cmp (#xx:8) op 15 0 87 op rn and, or, xor (rm) rm 15 0 87 rn imm and, or, xor (#xx:8) op 15 0 87 rn shal, shar, shll, shlr, rotl, rotr, rotxl, rotxr op figure 2.6 arithmetic, logic, and shift instruction codes 45 2.5.5 bit manipulations table 2.8 describes the bit-manipulation instructions. figure 2.7 shows their object code formats. table 2.8 bit-manipulation instructions instruction size * function bset b 1 ( 46 instruction size * function bixor b c [( 47 before execution of bclr instruction p4 7 p4 6 p4 5 p4 4 p4 3 p4 2 p4 1 p4 0 input/output input input output output output output output output pin state low high low low low low low low ddr 00111111 dr 10000000 execution of bclr instruction bclr #0, @p4ddr ; clear bit 0 in data direction register after execution of bclr instruction p4 7 p4 6 p4 5 p4 4 p4 3 p4 2 p4 1 p4 0 input/output output output output output output output output input pin state low high low low low low low high ddr 1 111111 0 dr 10000000 explanation: to execute the bclr instruction, the cpu begins by reading p4ddr. since p4ddr is a write-only register, it is read as h'ff, even though its true value is h'3f. next the cpu clears bit 0 of the read data, changing the value to h'fe. finally, the cpu writes this value (h'fe) back to p4ddr to complete the bclr instruction. as a result, p4 0 ddr is cleared to 0, making p4 0 an input pin. in addition, p4 7 ddr and p4 6 ddr are set to 1, making p4 7 and p4 6 output pins. 48 15 0 87 op imm rn operand: bit no.: legend: op: rm, rn: abs: imm: operation field register field absolute address immediate data 15 0 87 op rn bset, bclr, bnot, btst register direct (rn) immediate (#xx:3) operand: bit no.: register direct (rn) register direct (rm) rm 15 0 87 op 0 operand: bit no.: register indirect (@rn) immediate (#xx:3) rn 0 0 0 0 0 0 0 imm 15 0 87 op 0 operand: bit no.: register indirect (@rn) register direct (rm) rn 0 0 0 0 0 0 0 rm op 15 0 87 op operand: bit no.: absolute (@aa:8) immediate (#xx:3) abs 0000 imm op op 15 0 87 op operand: bit no.: absolute (@aa:8) register direct (rm) abs 0000 rm op 15 0 87 op imm rn operand: bit no.: register direct (rn) immediate (#xx:3) band, bor, bxor, bld, bst 15 0 87 op 0 operand: bit no.: register indirect (@rn) immediate (#xx:3) rn 0 0 0 0 0 0 0 imm op 15 0 87 op operand: bit no.: absolute (@aa:8) immediate (#xx:3) abs 0000 imm op figure 2.7 bit manipulation instruction codes 49 legend: op: rm, rn: abs: imm: operation field register field absolute address immediate data 15 0 87 op imm rn operand: bit no.: register direct (rn) immediate (#xx:3) biand, bior, bixor, bild, bist 15 0 87 op 0 operand: bit no.: register indirect (@rn) immediate (#xx:3) rn 0 0 0 0 0 0 0 imm op 15 0 87 op operand: bit no.: absolute (@aa:8) immediate (#xx:3) abs 0000 imm op figure 2.7 bit manipulation instruction codes (cont) 50 2.5.6 branching instructions table 2.9 describes the branching instructions. figure 2.8 shows their object code formats. table 2.9 branching instructions instruction size function bcc branches if condition cc is true. mnemonic cc field description condition bra (bt) 0 0 0 0 always (true) always brn (bf) 0 0 0 1 never (false) never bhi 0 0 1 0 high c branches unconditionally to a specified address. jsr branches to a subroutine at a specified address. bsr branches to a subroutine at a specified displacement from the current address. rts returns from a subroutine. 51 legend: op: cc: rm: disp: abs: operation field condition field register field displacement absolute address 15 0 87 op cc disp bcc 15 0 87 op rm 0 jmp (@rm) 000 15 0 87 op jmp (@aa:16) abs 15 0 87 op abs jmp (@@aa:8) 15 0 87 op disp bsr 15 0 87 op rm 0 jsr (@rm) 000 15 0 87 op jsr (@aa:16) abs 15 0 87 op abs jsr (@@aa:8) 15 0 87 op rts figure 2.8 branching instruction codes 52 2.5.7 system control instructions table 2.10 describes the system control instructions. figure 2.9 shows their object code formats. table 2.10 system control instructions instruction size * function rte returns from an exception-handling routine. sleep causes a transition to the power-down state. ldc b rs pc + 2 * size: operand size b: byte legend: op: rn: imm: operation field register field immediate data 15 0 87 op rte, sleep, nop 15 0 87 op rn ldc, stc (rn) 15 0 87 op imm andc, orc, xorc, ldc (#xx:8) figure 2.9 system control instruction codes 53 2.5.8 block data transfer instruction table 2.11 describes the eepmov instruction. figure 2.10 shows its object code format. table 2.11 block data transfer instruction instruction size function eepmov if r4l 1 figure 2.10 block data transfer instruction 54 notes on eepmov instruction 1. the eepmov instruction is a block data transfer instruction. it moves the number of bytes specified by r4l from the address specified by r5 to the address specified by r6. 2. when setting r4l and r6, make sure that the final destination address (r6 + r4l) does not exceed h'ffff. the value in r6 must not change from h'ffff to h'0000 during execution of the instruction. h'ffff not allowed 55 2.6 cpu states 2.6.1 overview the cpu has three states: the program execution state, exception-handling state, and power-down state. the power-down state is further divided into three modes: sleep mode, software standby mode, and hardware standby mode. figure 2.11 summarizes these states, and figure 2.12 shows a map of the state transitions. state program execution state the cpu executes successive program instructions. exception-handling state a transient state triggered by a reset or interrupt. the cpu executes a hardware sequence that includes loading the program counter from the vector table. power-down state a state in which some or all of the chip functions are stopped to conserve power. sleep mode software standby mode hardware standby mode figure 2.11 operating states 56 reset state hardware standby mode interrupt request res stby res res stby figure 2.12 state transitions 2.6.2 program execution state in this state the cpu executes program instructions. 2.6.3 exception-handling state the exception-handling state is a transient state that occurs when the cpu is reset or interrupted and changes its normal processing flow. in interrupt exception handling, the cpu references the stack pointer (r7) and saves the program counter and condition code register on the stack. for further details see section 4, exception handling. 57 2.6.4 power-down state the power-down state includes three modes: sleep mode, software standby mode, and hardware standby mode. sleep mode: is entered when a sleep instruction is executed. the cpu halts, but cpu register contents remain unchanged and the on-chip supporting modules continue to function. software standby mode: is entered if the sleep instruction is executed while the ssby (software standby) bit in the system control register (syscr) is set. the cpu and all on-chip supporting modules halt. the on-chip supporting modules are initialized, but the contents of the on-chip ram and cpu registers remain unchanged as long as a specified voltage is supplied. i/o port outputs also remain unchanged. hardware standby mode: is entered when the input at the stby pin goes low. all chip functions halt, including i/o port output. the on-chip supporting modules are initialized, but on- chip ram contents are held. see section 22, power-down state, for further information. 2.7 access timing and bus cycle the cpu is driven by the system clock ( ). the period from one rising edge of the system clock to the next is referred to as a state. memory access is performed in a two- or three-state bus cycle. on-chip memory, on-chip supporting modules, and external devices are accessed in different bus cycles as described below. 2.7.1 access to on-chip memory (ram and rom) on-chip rom and ram are accessed in a cycle of two states designated t 1 and t 2 . either byte or word data can be accessed, via a 16-bit data bus. figure 2.13 shows the on-chip memory access cycle. figure 2.14 shows the associated pin states. 58 bus cycle internal data bus (read) internal address bus internal read signal internal write signal internal data bus (write) address t 1 state t 2 state write data read data figure 2.13 on-chip memory access cycle bus cycle t 1 state t 2 state address address bus as rd wr figure 2.14 pin states during on-chip memory access cycle 59 2.7.2 access to on-chip supporting modules and external devices the on-chip supporting module registers and external devices are accessed in a cycle consisting of three states: t 1 , t 2 , and t 3 . only one byte of data can be accessed per cycle, via an 8-bit data bus. access to word data or instruction codes requires two consecutive cycles (six states). figure 2.15 shows the access cycle for the on-chip supporting modules. figure 2.16 shows the associated pin states. figures 2.17 (a) and (b) show the read and write access timing for external devices. bus cycle internal data bus (read) internal address bus internal read signal internal write signal internal data bus (write) address write data t 1 state t 2 state t 3 state read data figure 2.15 on-chip supporting module access cycle 60 address bus cycle t 3 state t 2 state t 1 state address bus as rd wr figure 2.16 pin states during on-chip supporting module access cycle read cycle address read data t 1 state t 2 state t 3 state address bus as wr rd figure 2.17 (a) external device access timing (read) 61 write cycle address write data t 1 state t 2 state t 3 state address bus as wr rd figure 2.17 (b) external device access timing (write) 62 63 section 3 mcu operating modes and address space 3.1 overview 3.1.1 mode selection the h8/3397 and h8/3337 series operate in three modes numbered 1, 2, and 3. the mode is selected by the inputs at the mode pins (md 1 and md 0 ). see table 3.1. table 3.1 operating modes mode md 1 md 0 address space on-chip rom on-chip ram mode 0 low low mode 1 low high expanded disabled enabled * mode 2 high low expanded enabled enabled * mode 3 high high single-chip enabled enabled note: * if the rame bit in the system control register (syscr) is cleared to 0, off-chip memory can be accessed instead. modes 1 and 2 are expanded modes that permit access to off-chip memory and peripheral devices. the maximum address space supported by these externally expanded modes is 64 kbytes. in mode 3 (single-chip mode), only on-chip rom and ram and the on-chip register field are used. all ports are available for general-purpose input and output. mode 0 is inoperative in the h8/3397 and h8/3337 series. avoid setting the mode pins to mode 0. avoid setting the mode pins to mode 0, and do not change the mode pin settings while the chip is operating. 3.1.2 mode and system control registers table 3.2 lists the registers related to the chip? operating mode: the system control register (syscr) and mode control register (mdcr). the mode control register indicates the inputs to the mode pins md 1 and md 0 . table 3.2 mode and system control registers name abbreviation read/write address system control register syscr r/w h'ffc4 mode control register mdcr r h'ffc5 64 3.2 system control register (syscr) bit 76543210 ssby sts2 sts1 sts0 xrst nmieg hie rame initial value 0 0 0 0 1 0 0 1 read/write r/w r/w r/w r/w r r/w r/w r/w the system control register (syscr) is an 8-bit register that controls the operation of the chip. bit 7?oftware standby (ssby): enables transition to the software standby mode. for details, see section 22, power-down state. on recovery from software standby mode by an external interrupt, the ssby bit remains set to 1. it can be cleared by writing 0. bit 7: ssby description 0 the sleep instruction causes a transition to sleep mode. (initial value) 1 the sleep instruction causes a transition to software standby mode. bits 6 to 4?tandby timer select 2 to 0 (sts2 to sts0): these bits select the clock settling time when the chip recovers from the software standby mode by an external interrupt. during the selected time the cpu and on-chip supporting modules continue to stand by. these bits should be set according to the clock frequency so that the settling time is at least 8 ms. for specific settings, see section 22.3.3, clock settling time for exit from software standby mode. ztat and mask rom versions bit 6: sts2 bit 5: sts1 bit 4: sts0 description 0 0 0 settling time = 8,192 states (initial value) 1 settling time = 16,384 states 1 0 settling time = 32,768 states 1 settling time = 65,536 states 1 0 settling time = 131,072 states 1 unused 65 f-ztat version bit 6: sts2 bit 5: sts1 bit 4: sts0 description 0 0 0 settling time = 8,192 states (initial value) 1 settling time = 16,384 states 1 0 settling time = 32,768 states 1 settling time = 65,536 states 1 0 0 settling time = 131,072 states 1 settling time = 1,024 states 1 unused note: when 1,024 states (sts2 to sts0 = 101) is selected, the following points should be noted. if a period exceeding ?/1,024 (e.g. ?/2,048) is specified when selecting the 8-bit timer, pwm timer, or watchdog timer clock, the counter in the timer will not count up normally when 1,024 states is specified for the settling time. to avoid this problem, set the sts value just before the transition to software standby mode (before executing the sleep instruction), and re-set the value of sts2 to sts0 to a value from 000 to 100 directly after software standby mode is cleared by an interrupt. bit 3?xternal reset (xrst): indicates the source of a reset. a reset can be generated by input of an external reset signal, or by a watchdog timer overflow when the watchdog timer is used. xrst is a read-only bit. it is set to 1 by an external reset, and cleared to 0 by watchdog timer overflow. bit 3: nmieg description 0 reset was caused by watchdog timer overflow. 1 reset was caused by external input. (initial value) bit 2?mi edge (nmieg): selects the valid edge of the nmi input. bit 2: nmieg description 0 an interrupt is requested on the falling edge of the nmi input. (initial value) 1 an interrupt is requested on the rising edge of the nmi input. bit 1?ost interface enable (hie): enables or disables the host interface function. when enabled, the host interface processes host-slave data transfers, operating in slave mode. bit 1: hie description 0 the host interface is disabled. (initial value) 1 the host interface is enabled (slave mode). 66 bit 0?am enable (rame): enables or disables the on-chip ram. the rame bit is initialized by a reset, but is not initialized in the software standby mode. bit 0: rame description 0 the on-chip ram is disabled. 1 the on-chip ram is enabled. (initial value) 3.3 mode control register (mdcr) bit 76543210 expe * 1 mds1 mds0 initial value * 2 11 00 1 * 2 * 2 read/write r/w * 2 r r notes: * 1 h8/3337sf (s-mask model, single-power-supply on-chip flash memory version) only. otherwise, this is a reserved bit that is always read as 1. * 2 determined by the mode pins (md 1 and md 0 ). the mode control register (mdcr) is an 8-bit register that indicates the operating mode of the chip. bit 7?xpanded mode enable (expe): functions only in the h8/3337sf (s-mask model, single-power-supply on-chip flash memory version). for details, see section 21.1.6, mode control register (mdcr). in models other than the h8/3337sf, this is a reserved bit that cannot be modified and is always read as 1. bits 6 and 5?eserved: these bits cannot be modified and are always read as 1. bits 4 and 3?eserved: these bits cannot be modified and are always read as 0. bit 2?eserved: this bit cannot be modified and is always read as 1. bits 1 and 0?ode select 1 and 0 (mds1 and mds0): these bits indicate the values of the mode pins (md 1 and md 0 ), thereby indicating the current operating mode of the chip. mds1 corresponds to md 1 and mds0 to md 0 . these bits can be read but not written. when the mode control register is read, the levels at the mode pins (md 1 and md 0 ) are latched in these bits. 3.4 address space map in each operating mode figures 3.1 to 3.3 show memory maps of the h8/3337y, h8/3336y, h8/3334y, h8/3397, h8/3396, and h8/3394 in modes 1, 2, and 3. 67 h'ffff h'ff88 h'ff87 h'ff80 h'ff7f h'f780 h'f77f h'004c h'004b h'0000 h'ffff h'ff88 h'ff87 h'ff80 h'ff7f h'f780 h'f77f h'ffff h'ff88 h'ff7f h'f780 h'ef80 h'ef7f h'004c h'004b h'0000 h'004c h'004b h'0000 mode 1 expanded mode without on-chip rom mode 2 expanded mode with on-chip rom mode 3 single-chip mode vector table on-chip rom, 61,312 bytes vector table vector table external address space on-chip ram * , 2,048 bytes on-chip ram, 2,048 bytes external address space external address space external address space on-chip ram * , 2,048 bytes on-chip register field on-chip register field on-chip register field external memory can be accessed at these addresses when the rame bit in the system control register (syscr) is cleared to 0. note: * on-chip rom, 63,360 bytes h'f77f figure 3.1 h8/3337y and h8/3397 address space map 68 h'ffff h'ff88 h'ff87 h'ff80 h'ff7f h'f780 h'f77f h'004c h'004b h'0000 h'ffff h'ff88 h'ff87 h'ff80 h'ff7f h'f780 h'f77f h'ffff h'ff88 h'ff7f h'f780 h'ef80 h'ef7f h'004c h'004b h'0000 h'004c h'004b h'0000 mode 1 expanded mode without on-chip rom mode 2 expanded mode with on-chip rom mode 3 single-chip mode vector table on-chip rom, 49,152 bytes vector table vector table external address space on-chip ram * , 2,048 bytes on-chip ram, 2,048 bytes external address space external address space external address space on-chip ram * , 2,048 bytes on-chip register field on-chip register field on-chip register field * 1 do not access reserved areas. * 2 external memory can be accessed at these addresses when the rame bit in the system control register (syscr) is cleared to 0. notes: on-chip rom, 49,152 bytes h'f77f reserved * 1 2 reserved * 1 2 h'c000 h'c000 h'bfff h'bfff figure 3.2 h8/3336y, h8/3396 address space map 69 h'ffff h'ff88 h'ff87 h'ff80 h'ff7f h'fb80 h'fb7f h'f780 h'f77f h'004c h'004b h'0000 h'ffff h'ff88 h'ff87 h'ff80 h'ff7f h'fb80 h'fb7f h'f780 h'f77f h'ffff h'ff88 h'ff7f h'ef80 h'ef7f h'8000 h'7fff h'8000 h'7fff h'004c h'004b h'0000 h'004c h'004b h'0000 mode 1 expanded mode without on-chip rom mode 2 expanded mode with on-chip rom mode 3 single-chip mode vector table on-chip rom, 32,768 bytes vector table vector table reserved * 1 reserved * 1, * 2 reserved * 1, * 2 external address space on-chip ram * 2 , 1,024 bytes on-chip ram, 1,024 bytes external address space external address space external address space on-chip ram * 2 , 1,024 bytes on-chip register field on-chip register field on-chip register field do not access reserved areas. external memory can be accessed at these addresses when the rame bit in the system control register (syscr) is cleared to 0. notes: * 1 * 2 on-chip rom, 32,768 bytes reserved * 1 reserved * 1 h'f780 h'f77f h'fb80 h'fb7f figure 3.3 h8/3334y, h8/3394 address space map 70 71 section 4 exception handling 4.1 overview the h8/3337 series and h8/3397 series recognize two kinds of exceptions: interrupts and the reset. table 4.1 indicates their priority and the timing of their hardware exception-handling sequence. table 4.1 hardware exception-handling sequences and priority priority type of exception detection timing timing of exception-handling sequence high reset synchronized with clock the hardware exception-handling sequence begins as soon as res changes from low to high. low interrupt end of instruction execution * when an interrupt is requested, the hardware exception-handling sequence begins at the end of the current instruction, or at the end of the current hardware exception-handling sequence. note: * not detected after andc, orc, xorc, and ldc instructions. 4.2 reset 4.2.1 overview a reset has the highest exception-handling priority. when the res pin goes low or when there is a watchdog timer reset (when the reset option is selected for watchdog timer overflow), all current processing stops and the chip enters the reset state. the internal state of the cpu and the registers of the on-chip supporting modules are initialized. the reset exception-handling sequence starts when res returns from low to high, or at the end of a watchdog reset pulse. 4.2.2 reset sequence the reset state begins when res goes low or a watchdog reset is generated. to ensure correct resetting, at power-on the res pin should be held low for at least 20 ms. in a reset during operation, the res pin should be held low for at least 10 system clock cycles. the watchdog reset pulse width is always 518 system clocks. for the pin states during a reset, see appendix d, port states in each mode. 72 the following sequence is carried out when reset exception handling begins. 1. the internal state of the cpu and the registers of the on-chip supporting modules are initialized, and the i bit in the condition code register (ccr) is set to 1. 2. the cpu loads the program counter with the first word in the vector table (stored at addresses h'0000 and h'0001) and starts program execution. the res pin should be held low when power is switched off, as well as when power is switched on. figure 4.1 indicates the timing of the reset sequence in modes 2 and 3. figure 4.2 indicates the timing in mode 1. (1) res /watchdog timer reset (internal) (2) internal address bus internal read signal internal write signal internal data bus (16 bits) (1) reset vector address (h'0000) (2) starting address of program (3) first instruction of program vector fetch internal processing instruction prefetch (2) (3) figure 4.1 reset sequence (mode 2 or 3, program stored in on-chip rom) 73 (1) (3) (5) (7) (1), (3) reset vector address: (1) = h'0000, (3) = h'0001 (2), (4) starting address of program (contents of reset vector): (2) = upper byte, (4) = lower byte (5), (7) starting address of program: (5) = (2) (4), (7) = (2) (4) + 1 (6), (8) first instruction of program: (6) = first byte, (8) = second byte vector fetch internal process- ing instruction prefetch res rd wr figure 4.2 reset sequence (mode 1) 74 4.2.3 disabling of interrupts after reset after a reset, if an interrupt were to be accepted before initialization of the stack pointer (sp: r7), the program counter and condition code register might not be saved correctly, leading to a program crash. to prevent this, all interrupts, including nmi, are disabled immediately after a reset. the first program instruction is therefore always executed. this instruction should initialize the stack pointer (example: mov.w #xx:16, sp). after reset exception handling, in order to initialize the contents of ccr, a ccr manipulation instruction can be executed before an instruction to initialize the stack pointer. immediately after execution of a ccr manipulation instruction, all interrupts including nmi are disabled. use the next instruction to initialize the stack pointer. 4.3 interrupts 4.3.1 overview the interrupt sources include nine external sources from 23 input pins (nmi, irq 0 to irq 7 , and keyin 0 to keyin 7 ), and 26 (h8/3337 series) or 23 (h8/3397 series) internal sources in the on- chip supporting modules. table 4.2 lists the interrupt sources in priority order and gives their vector addresses. when two or more interrupts are requested, the interrupt with highest priority is served first. the features of these interrupts are: ? nmi has the highest priority and is always accepted. all internal and external interrupts except nmi can be masked by the i bit in the ccr. when the i bit is set to 1, interrupts other than nmi are not accepted. ? irq 0 to irq 7 can be sensed on the falling edge of the input signal, or level-sensed. the type of sensing can be selected for each interrupt individually. nmi is edge-sensed, and either the rising or falling edge can be selected. ? all interrupts are individually vectored. the software interrupt-handling routine does not have to determine what type of interrupt has occurred. ? irq 6 is multiplexed with 8 external sources (keyin 0 to keyin 7 ). keyin 0 to keyin 7 can be masked individually by user software. ? the watchdog timer can generate either an nmi or overflow interrupt, depending on the needs of the application. for details, see section 11, watchdog timer. 75 table 4.2 interrupts interrupt source no. vector table address priority nmi irq 0 irq 1 irq 2 irq 3 irq 4 irq 5 irq 6 irq 7 3 4 5 6 7 8 9 10 11 h'0006 to h'0007 h'0008 to h'0009 h'000a to h'000b h'000c to h'000d h'000e to h'000f h'0010 to h'0011 h'0012 to h'0013 h'0014 to h'0015 h'0016 to h'0017 high 16-bit free-running timer icia (input capture a) icib (input capture b) icic (input capture c) icid (input capture d) ocia (output compare a) ocib (output compare b) fovi (overflow) 12 13 14 15 16 17 18 h'0018 to h'0019 h'001a to h'001b h'001c to h'001d h'001e to h'001f h'0020 to h'0021 h'0022 to h'0023 h'0024 to h'0025 8-bit timer 0 cmi0a (compare-match a) cmi0b (compare-match b) ovi0 (overflow) 19 20 21 h'0026 to h'0027 h'0028 to h'0029 h'002a to h'002b 8-bit timer 1 cmi1a (compare-match a) cmi1b (compare-match b) ovi1 (overflow) 22 23 24 h'002c to h'002d h'002e to h'002f h'0030 to h'0031 host interface * 1 ibf1 (idr1 receive end) ibf2 (idr2 receive end) 25 26 h'0032 to h'0033 h'0034 to h'0035 serial communication interface 0 eri0 (receive error) rxi0 (receive end) txi0 (tdr empty) tei0 (tsr empty) 27 28 29 30 h'0036 to h'0037 h'0038 to h'0039 h'003a to h'003b h'003c to h'003d serial communication interface 1 eri1 (receive error) rxi1 (receive end) txi1 (tdr empty) tei1 (tsr empty) 31 32 33 34 h'003e to h'003f h'0040 to h'0041 h'0042 to h'0043 h'0044 to h'0045 a/d converter adi (conversion end) 35 h'0046 to h'0047 watchdog timer wovf (wdt overflow) 36 h'0048 to h'0049 i 2 c bus interface * 2 iici (transfer end) 37 h'004a to h'004b low notes: 1. h'0000 and h'0001 contain the reset vector. 2. h'0002 to h'0005 are reserved in the h8/3337 series and h8/3397 series are not available to the user. * 1 h8/3337 series only. * 2 h8/3337 series only (option). 76 4.3.2 interrupt-related registers the interrupt-related registers are the system control register (syscr), irq sense control register (iscr), irq enable register (ier), and keyboard matrix interrupt mask register (kmimr). table 4.3 registers read by interrupt controller name abbreviation read/write address system control register syscr r/w h'ffc4 irq sense control register iscr r/w h'ffc6 irq enable register ier r/w h'ffc7 keyboard matrix interrupt mask register kmimr r/w h'fff1 system control register (syscr) bit 76543210 ssby sts2 sts1 sts0 xrst nmieg hie rame initial value 0 0 0 0 1 0 0 1 read/write r/w r/w r/w r/w r r/w r/w r/w the valid edge on the nmi line is controlled by bit 2 (nmieg) in the system control register. bit 2?mi edge (nmieg): determines whether a nonmaskable interrupt is generated on the falling or rising edge of the nmi input signal. bit 2: nmieg description 0 an interrupt is generated on the falling edge of nmi nmi see section 3.2, system control register, for information on the other syscr bits. irq sense control register (iscr) bit 76543210 irq7sc irq6sc irq5sc irq4sc irq3sc irq2sc irq1sc irq0sc initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w 77 bits 7 to 0?rq 7 to irq 0 sense control (irq7sc to irq0sc): these bits determine whether irq 7 to irq 0 are level-sensed or sensed on the falling edge. bits 7 to 0: irq7sc to irq0sc description 0 an interrupt is generated when irq irq irq irq irq enable register (ier) bit 76543210 irq7e irq6e irq5e irq4e irq3e irq2e irq1e irq0e initial value 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w bits 7 to 0?rq7 to irq0 enable (irq7e to irq0e): these bits enable or disable the irq 7 to irq 0 interrupts individually. bits 7 to 0: irq0e to irq7e description 0 irq 7 to irq 0 interrupt requests are disabled. (initial state) 1 irq 7 to irq 0 interrupt requests are enabled. when edge sensing is selected (by setting bits irq7sc to irq0sc to 1), it is possible for an interrupt-handling routine to be executed even though the corresponding enable bit (irq7e to irq0e) is cleared to 0 and the interrupt is disabled. if an interrupt is requested while the enable bit (irq7e to irq0e) is set to 1, the request will be held pending until served. if the enable bit is cleared to 0 while the request is still pending, the request will remain pending, although new requests will not be recognized. if the interrupt mask bit (i) in the ccr is cleared to 0, the interrupt-handling routine can be executed even though the enable bit is now 0. if execution of interrupt-handling routines under these conditions is not desired, it can be avoided by using the following procedure to disable and clear interrupt requests. 1. set the i bit to 1 in the ccr, masking interrupts. note that the i bit is set to 1 automatically when execution jumps to an interrupt vector. 2. clear the desired bits from irq7e to irq0e to 0 to disable new interrupt requests. 3. clear the corresponding irq7sc to irq0sc bits to 0, then set them to 1 again. pending irqn interrupt requests are cleared when i = 1 in the ccr, irqnsc = 0, and irqne = 0. 78 keyboard matrix interrupt mask register (kmimr) kmimr is provided as a register for keyboard matrix interrupt masking. this register controls interrupts from the keyin 7 to keyin 0 key sense input pins for a 16 8 matrix keyboard. bits kmimr7 to kmimr0 of kmimr correspond to key sense inputs keyin 7 to keyin 0 . in interrupt mask bit initialization, bit kmimr6 corresponding to the irq 6 / keyin 6 pin is set to enable interrupt requests, while the other mask bits are set to disable interrupts. kmimr is an 8-bit readable/writable register used in keyboard matrix scan/sense. this register initializes to a state in which only the input at the irq 6 pin is enabled. to enable key sense input interrupts from two or more pins in keyboard matrix scanning and sensing, clear the corresponding mask bits to 0. figure 4.3 shows the relationship between the irq 6 interrupt, kmimr, and kmimra. bit 76543210 kmimr7 kmimr6 kmimr5 kmimr4 kmimr3 kmimr2 kmimr1 kmimr0 initial value 1 0 1 1 1 1 1 1 read/write r/w r/w r/w r/w r/w r/w r/w r/w bits 7 to 0?eyboard matrix interrupt mask (kmimr7 to kmimr0): these bits control key sense input interrupt requests keyin 7 to keyin 0 . bits 7 to 0: kmimr7 to kmimr0 description 0 key sense input interrupt request is enabled. 1 key sense input interrupt request is disabled. (initial value) * note: * except kmimr6, which is initially 0. 79 irq 6 e irq 6 sc kmimr0 (1) p6 0 / keyin keyin keyin irq irq figure 4.3 kmimr and irq 6 interrupt 80 4.3.3 external interrupts the nine external interrupts are nmi and irq 0 to irq 7 . nmi, irq 0 , irq 1 , irq 2 , and irq 6 can be used to recover from software standby mode. nmi: a nonmaskable interrupt is generated on the rising or falling edge of the nmi input signal regardless of whether the i (interrupt mask) bit is set in the ccr. the valid edge is selected by the nmieg bit in the system control register. the nmi vector number is 3. in the nmi hardware exception-handling sequence the i bit in the ccr is set to 1. irq 0 to irq 7 : these interrupt signals are level-sensed or sensed on the falling edge of the input, as selected by iscr bits irq0sc to irq7sc. these interrupts can be masked collectively by the i bit in the ccr, and can be enabled and disabled individually by setting and clearing bits irq0e to irq7e in the irq enable register. the irq 6 input signal can be logically ored internally with the key sense input signals. when keyin 0 to keyin 7 pins (p6 0 to p6 7 ) are used for key sense input, the corresponding kmimr bits should be cleared to 0 to enable the corresponding key sense input interrupts. kmimr bits corresponding to unused key sense inputs should be set to 1 to disable the interrupts. all 8 key sense input interrupts are combined into a single irq 6 interrupt. when one of these interrupts is accepted, the i bit is set to 1. irq 0 to irq 7 have interrupt vector numbers 4 to 11. they are prioritized in order from irq 7 (low) to irq 0 (high). for details, see table 4.2. interrupts irq 0 to irq 7 do not depend on whether pins irq 0 to irq 7 are input or output pins. when using external interrupts irq 0 to irq 7 , clear the corresponding ddr bits to 0 to set these pins to the input state, and do not use these pins as input or output pins for the timers, serial communication interface, or a/d converter. 4.3.4 internal interrupts twenty-six (h8/3337 series) or twenty-three (h8/3397 series) internal interrupts can be requested by the on-chip supporting modules. each interrupt source has its own vector number, so the interrupt-handling routine does not have to determine which interrupt has occurred. all internal interrupts are masked when the i bit in the ccr is set to 1. when one of these interrupts is accepted, the i bit is set to 1 to mask further interrupts (except nmi ). the vector numbers are 12 to 37. for the priority order, see table 4.2. 81 4.3.5 interrupt handling interrupts are controlled by an interrupt controller that arbitrates between simultaneous interrupt requests, commands the cpu to start the hardware interrupt exception-handling sequence, and furnishes the necessary vector number. figure 4.4 shows a block diagram of the interrupt controller. irq0 flag irq0e iric ieic cpu i (ccr) nmi interrupt interrupt controller priority decision irq0 interrupt interrupt request vector number iici interrupt note: * * for edge-sensed interrupts, these and gates change to the circuit shown below. irq0 edge irq0e sq irq0 flag irq0 interrupt figure 4.4 block diagram of interrupt controller the irq interrupts and interrupts from the on-chip supporting modules (except for reset selected for a watchdog timer overflow) all have corresponding enable bits. when the enable bit is cleared to 0, the interrupt signal is not sent to the interrupt controller, so the interrupt is ignored. these interrupts can also all be masked by setting the cpu? interrupt mask bit (i) to 1. accordingly, these interrupts are accepted only when their enable bit is set to 1 and the i bit is cleared to 0. the nonmaskable interrupt (nmi) is always accepted, except in the reset state and hardware standby mode. 82 when an nmi or another enabled interrupt is requested, the interrupt controller transfers the interrupt request to the cpu and indicates the corresponding vector number. (when two or more interrupts are requested, the interrupt controller selects the vector number of the interrupt with the highest priority.) when notified of an interrupt request, at the end of the current instruction or current hardware exception-handling sequence, the cpu starts the hardware exception-handling sequence for the interrupt and latches the vector number. figure 4.5 shows the interrupt operation flow. 1. an interrupt request is sent to the interrupt controller when an nmi interrupt occurs, and when an interrupt occurs on an irq input line or in an on-chip supporting module provided the enable bit of that interrupt is set to 1. 2. the interrupt controller checks the i bit in ccr and accepts the interrupt request if the i bit is cleared to 0. if the i bit is set to 1 only nmi requests are accepted; other interrupt requests remain pending. 3. among all accepted interrupt requests, the interrupt controller selects the request with the highest priority and passes it to the cpu. other interrupt requests remain pending. 4. when it receives the interrupt request, the cpu waits until completion of the current instruction or hardware exception-handling sequence, then starts the hardware exception- handling sequence for the interrupt and latches the interrupt vector number. 5. in the hardware exception-handling sequence, the cpu first pushes the pc and ccr onto the stack. see figure 4.6. the stacked pc indicates the address of the first instruction that will be executed on return from the software interrupt-handling routine. 6. next the i bit in ccr is set to 1, masking all further interrupts except nmi. 7. the vector address corresponding to the vector number is generated, the vector table entry at this vector address is loaded into the program counter, and execution branches to the software interrupt-handling routine at the address indicated by that entry. figure 4.7 shows the interrupt timing sequence for the case in which the software interrupt- handling routine is in on-chip rom and the stack is in on-chip ram. 83 program execution no no no yes no yes yes yes no yes nmi? i = 0? irq 0 ? irq 1 ? iici? reset i figure 4.5 hardware interrupt-handling sequence 84 sp(r7) sp 4 sp 3 sp 2 sp 1 sp (r7) sp + 1 sp + 2 sp + 3 sp + 4 even address ccr ccr * pc h before interrupt is accepted after interrupt is accepted pushed onto stack upper byte of progam counter lower byte of progam counter condition code register stack pointer pc h : pc l : ccr: sp: the pc contains the address of the first instruction executed after return. registers must be saved and restored by word access at an even address. notes: 1. 2. * ignored on return. stack area pc l figure 4.6 usage of stack in interrupt handling the ccr is comprised of one byte, but when it is saved to the stack, it is treated as one word of data. during interrupt processing, two identical bytes of ccr data are saved to the stack to create one word of data. when the rte instruction is executed to restore the value from the stack, the byte located at the even address is loaded into ccr, and the byte located at the odd address is ignored. 85 (3) (5) (6) (8) (9) (1) interrupt priority decision. wait for end of instruction. interrupt accepted internal process- ing stack vector fetch internal process- ing instruction prefetch (first instruction of interrupt-handling routine) interrupt request signal internal address bus internal write signal internal read signal internal 16-bit data bus (1) (2) (4) (7) (9) (10) instruction prefetch (1) (2) (4) (3) (5) (6) (7) (8) (9) (10) instruction prefetch address (pushed on stack. instruction is executed on return from interrupt-handling routine.) instruction code (not executed) instruction prefetch address (not executed) sp 2 sp 4 ccr address of vector table entry vector table entry (address of first instruction of interrupt-handling routine) first instruction of interrupt-handlin g routine figure 4.7 timing of interrupt sequence 86 4.3.6 interrupt response time table 4.4 indicates the number of states that elapse from an interrupt request signal until the first instruction of the software interrupt-handling routine is executed. since on-chip memory is accessed 16 bits at a time, very fast interrupt service can be obtained by placing interrupt-handling routines in on-chip rom and the stack in on-chip ram. table 4.4 number of states before interrupt service number of states no. reason for wait on-chip memory external memory 1 interrupt priority decision 2 * 3 2 * 3 2 wait for completion of current instruction * 1 1 to 13 5 to 17 * 2 3 save pc and ccr 4 12 * 2 4 fetch vector 2 6 * 2 5 fetch instruction 4 12 * 2 6 internal processing 4 4 total 17 to 29 41 to 53 * 2 notes: * 1 these values do not apply if the current instruction is eepmov. * 2 if wait states are inserted in external memory access, add the number of wait states. * 3 1 for internal interrupts. 4.3.7 precaution note that the following type of contention can occur in interrupt handling. when software clears the enable bit of an interrupt to 0 to disable the interrupt, the interrupt becomes disabled after execution of the clearing instruction. if an enable bit is cleared by a bclr or mov instruction, for example, and the interrupt is requested during execution of that instruction, at the instant when the instruction ends the interrupt is still enabled, so after execution of the instruction, the hardware exception-handling sequence is executed for the interrupt. if a higher-priority interrupt is requested at the same time, however, the hardware exception-handling sequence is executed for the higher-priority interrupt and the interrupt that was disabled is ignored. similar considerations apply when an interrupt request flag is cleared to 0. 87 figure 4.8 shows an example in which the ociae bit is cleared to 0. internal address bus ociae ocia exception handling ocia interrupt signal ocfa cpu write cycle to tier internal write signal tier address figure 4.8 contention between interrupt and disabling instruction the above contention does not occur if the enable bit or flag is cleared to 0 while the interrupt mask bit (i) is set to 1. 4.4 note on stack handling in word access, the least significant bit of the address is always assumed to be 0. the stack is always accessed by word access. care should be taken to keep an even value in the stack pointer (general register r7). use the push rn and pop rn (or mov.w rn, @ sp and mov.w @sp+, rn) instructions to push and pop registers on the stack. setting the stack pointer to an odd value can cause programs to crash. figure 4.9 shows an example of damage caused when the stack pointer contains an odd address. 88 pc h sp pc l h'fecd h'fecf h'fecc bsr instruction mov.b r1l, @ r7 pc is improperly stored beyond top of stack h'fecf set in sp pc h is lost pc h : pc l : r1l: sp: upper byte of program counter lower byte of program counter general register stack pointer sp r1l sp pc l figure 4.9 example of damage caused by setting an odd address in sp 89 section 5 wait-state controller 5.1 overview the h8/3337 series and h8/3397 series have an on-chip wait-state controller that enables insertion of wait states into bus cycles for interfacing to low-speed external devices. 5.1.1 features features of the wait-state controller are listed below. ? three selectable wait modes: programmable wait mode, pin auto-wait mode, and pin wait mode ? automatic insertion of zero to three wait states 5.1.2 block diagram figure 5.1 shows a block diagram of the wait-state controller. wait wait-state controller (wsc) wscr internal data bus wait request signal legend: wscr: wait-state control register figure 5.1 block diagram of wait-state controller 90 5.1.3 input/output pins table 5.1 summarizes the wait-state controller? input pin. table 5.1 wait-state controller pins name abbreviation i/o function wait wait input wait request signal for access to external addresses 5.1.4 register configuration table 5.2 summarizes the wait-state controller? register. table 5.2 register configuration address name abbreviation r/w initial value h'ffc2 wait-state control register wscr r/w h'08 5.2 register description 5.2.1 wait-state control register (wscr) wscr is an 8-bit readable/writable register that selects the wait mode for the wait-state controller (wsc) and specifies the number of wait states. it also controls ram area setting for dual-power- supply flash memory, selection/non-selection of single-power-supply flash memory control registers, and frequency division of the clock signals supplied to the supporting modules. bit 76543210 rams * 1 ram0 * 1 ckdbl flshe * 2 wms1 wms0 wc1 wc0 initial value 0 0 0 0 1 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w notes: * 1 these bits are valid only in the h8/3337yf (dual-power-supply on-chip flash memory versions). * 2 this bit is valid only in the h8/3337sf (s-mask model, single-power-supply on-chip flash memory version). wscr is initialized to h'08 by a reset and in hardware standby mode. it is not initialized in software standby mode. 91 bit 7?am select (rams) bit 6?am area select (ram0) bits 7 and 6 select a ram area for emulation of dual-power-supply flash memory updates. for details, see the flash memory description in section 19 and 20, rom. bit 5?lock double (ckdbl): controls frequency division of clock signals supplied to supporting modules. for details, see section 6, clock pulse generator. bit 4?lash memory control register enable (flshe): controls selection/non-selection of single-power-supply flash memory control registers. for details, see the description of flash memory in section 21, rom. in models other than the h8/3337sf, this bit is reserved, but it can be written and read; its initial value is 0. bits 3 and 2?ait mode select 1 and 0 (wms1/0): these bits select the wait mode. bit 3: wms1 bit 2: wms0 description 0 0 programmable wait mode 1 no wait states inserted by wait-state controller 1 0 pin wait mode (initial value) 1 pin auto-wait mode bits 1 and 0?ait count 1 and 0 (wc1/0): these bits select the number of wait states inserted in access to external address areas. bit 1: wc1 bit 0: wc0 description 0 0 no wait states inserted by wait-state controller (initial value) 1 1 state inserted 1 0 2 states inserted 1 3 states inserted 92 5.3 wait modes programmable wait mode: the number of wait states (t w ) selected by bits wc1 and wc0 are inserted in all accesses to external addresses. figure 5.2 shows the timing when the wait count is 1 (wc1 = 0, wc0 = 1). t 1 t 2 t w t 3 address bus as rd wr data bus data bus external address read data write data read access write access figure 5.2 programmable wait mode 93 pin wait mode: in all accesses to external addresses, the number of wait states (t w ) selected by bits wc1 and wc0 are inserted. if the wait pin is low at the fall of the system clock (? in the last of these wait states, an additional wait state is inserted. if the wait pin remains low, wait states continue to be inserted until the wait signal goes high. pin wait mode is useful for inserting four or more wait states, or for inserting different numbers of wait states for different external devices. figure 5.3 shows the timing when the wait count is 1 (wc1 = 0, wc0 = 1) and one additional wait state is inserted by wait input. address bus data bus as rd wr * read data * read access write access note: arrows indicate time of sampling of the pin. * wait pin wait wait figure 5.3 pin wait mode 94 pin auto-wait mode: if the wait pin is low, the number of wait states (t w ) selected by bits wc1 and wc0 are inserted. in pin auto-wait mode, if the wait pin is low at the fall of the system clock ( ) in the t 2 state, the number of wait states (t w ) selected by bits wc1 and wc0 are inserted. no additional wait states are inserted even if the wait pin remains low. pin auto-wait mode can be used for an easy interface to low-speed memory, simply by routing the chip select signal to the wait pin. figure 5.4 shows the timing when the wait count is 1. address bus data bus as rd wr * * read data read data write data write data read access write access note: arrows indicate time of sampling of the pin. * wait wait figure 5.4 pin auto-wait mode 95 section 6 clock pulse generator 6.1 overview the h8/3337 series and h8/3397 series have a built-in clock pulse generator (cpg) consisting of an oscillator circuit, a duty adjustment circuit, and a divider and a prescaler that generates clock signals for the on-chip supporting modules. 6.1.1 block diagram figure 6.1 shows a block diagram of the clock pulse generator. xtal extal oscillator circuit duty adjustment circuit frequency divider (1/2) ckdbl (system clock) p (for sup- porting modules) prescaler p /2 to p /4096 figure 6.1 block diagram of clock pulse generator input an external clock signal to the extal pin, or connect a crystal resonator to the xtal and extal pins. the system clock frequency (? will be the same as the input frequency. this same system clock frequency ( p ) can be supplied to timers and other supporting modules, or it can be divided by two. the selection is made by software, by controlling the ckdbl bit. 96 6.1.2 wait-state control register (wscr) wscr is an 8-bit readable/writable register that controls frequency division of the clock signals supplied to the supporting modules. it also controls wait state controller wait settings, ram area setting for dual-power-supply flash memory, and selection/non-selection of single-power-supply flash memory control registers. wscr is initialized to h'08 by a reset and in hardware standby mode. it is not initialized in software standby mode. bit 76543210 rams * 1 ram0 * 1 ckdbl flshe * 2 wms1 wms0 wc1 wc0 initial value 0 0 0 0 1 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w notes: * 1 these bits are valid only in the h8/3337yf (dual-power-supply on-chip flash memory versions). * 2 this bit is valid only in the h8/3337sf (s-mask model, single-power-supply on-chip flash memory version). bit 7?am select (rams) bit 6?am area select (ram0) bits 7 and 6 select a ram area for emulation of dual-power-supply flash memory updates. for details, see the flash memory description in section 18, rom. bit 5?lock double (ckdbl): controls the frequency division of clock signals supplied to supporting modules. bit 5: ckdbl description 0 the undivided system clock (? is supplied as the clock ( p ) for supporting modules. (initial value) 1 the system clock (? is divided by two and supplied as the clock ( p ) for supporting modules. bit 4?lash memory control register enable (flshe): controls selection/non-selection of single-power-supply flash memory control registers. for details, see the description of flash memory in section 21, rom. in models other than the h8/3337sf, this bit is reserved, but it can be written and read; its initial value is 0. bits 3 and 2?ait mode select 1 and 0 (wms1/0) bits 1 and 0?ait count 1 and 0 (wc1/0) these bits control wait-state insertion. for details, see section 5, wait-state controller. 97 6.2 oscillator circuit 6.2.1 oscillator (generic device) if an external crystal is connected across the extal and xtal pins, the on-chip oscillator circuit generates a system clock signal. alternatively, an external clock signal can be applied to the extal pin. connecting an external crystal circuit configuration: an external crystal can be connected as in the example in figure 6.2. table 6.1 indicates the appropriate damping resistance rd. an at-cut parallel resonance crystal should be used. extal xtal c l1 c l2 c = c = 10 pf to 22 pf l1 l2 rd figure 6.2 connection of crystal oscillator (example) table 6.1 damping resistance frequency (mhz) 248101216 rd max ( ? crystal oscillator: figure 6.3 shows an equivalent circuit of the crystal resonator. the crystal resonator should have the characteristics listed in table 6.2. 98 xtal lrs c l c 0 extal at-cut parallel resonating crystal figure 6.3 equivalent circuit of external crystal table 6.2 external crystal parameters frequency (mhz) 248101216 rd max ( ? use a crystal with the same frequency as the desired system clock frequency (?. note on board design: when an external crystal is connected, other signal lines should be kept away from the crystal circuit to prevent induction from interfering with correct oscillation. see figure 6.4. the crystal and its load capacitors should be placed as close as possible to the xtal and extal pins. xtal extal c l2 c l1 not allowed signal a signal b figure 6.4 board design around external crystal 99 input of external clock signal circuit configuration: an external clock signal can be input as shown in the examples in figure 6.5. in example (b) in figure 6.5, the external clock signal should be kept high during standby. if the xtal pin is left open, make sure the stray capacitance does not exceed 10 pf. extal xtal extal xtal 74hc04 external clock input open external clock input (a) connections with xtal pin left open (b) connections with inverted clock input at xtal pin figure 6.5 external clock input (example) 100 external clock input: the external clock signal should have the same frequency as the desired system clock (?. clock timing parameters are given in table 6.3 and figure 6.6. table 6.3 clock timing v cc = 2.7 to 5.5 v v cc = 4.0 to 5.5 v v cc = 5.0 v 10% item symbol min max min max min max unit test conditions low pulse width of external clock input t exl 40 30 20 ns figure 6.6 high pulse width of external clock input t exh 40 30 20 ns external clock rise time t exr 10 10 5ns external clock fall time t exf 10 10 5ns clock pulse t cl 0.3 0.7 0.3 0.7 0.3 0.7 t cyc < 5 mhz 20-4 clock pulse t ch 0.3 0.7 0.3 0.7 0.3 0.7 t cyc < 5 mhz t exh t exl t ext t exr v cc figure 6.6 external clock input timing table 6.4 shows the external clock output settling delay time. figure 6.7 shows the timing for the external clock output settling delay time. the oscillator and duty correction circuit have the function of regulating the waveform of the external clock input to the extal pin. when the specified clock signal is input to the extal pin, internal clock signal output is confirmed after the elapse of the external clock output settling delay time (t dext ). as clock signal output is not confirmed during the t dext period, the reset signal should be driven low and the reset state maintained during this time. 101 table 6.4 external clock output settling delay time conditions: v cc = 2.7 to 5.5 v, av cc = 2.7 to 5.5 v, v ss = av ss = 0 v item symbol min max unit notes external clock output settling delay time t dext * 500 * t dext includes a 10 t cyc res stby (internal or external) res res figure 6.7 external clock output settling delay time 6.2.2 oscillator circuit (h8/3337sf) if an external crystal is connected across the extal and xtal pins, the on-chip oscillator circuit generates a system clock signal. alternatively, an external clock signal can be applied to the extal pin. connecting an external crystal circuit configuration: an external crystal can be connected as in the example in figure 6.8. table 6.5 indicates the appropriate damping resistance rd. an at-cut parallel resonance crystal should be used. 102 extal xtal c l1 c l2 c l1 = c l2 = 10 pf to 22 pf rd figure 6.8 connection of crystal oscillator (example) table 6.5 damping resistance frequency (mhz) 2 4 8 10 rd max ( ? crystal oscillator: figure 6.9 shows an equivalent circuit of the crystal resonator. the crystal resonator should have the characteristics listed in table 6.6. xtal lrs c l c 0 extal at-cut parallel resonating crystal figure 6.9 equivalent circuit of external crystal table 6.6 external crystal parameters frequency (mhz) 2 4 8 10 rs max ( ? ). note on board design: when an external crystal is connected, other signal lines should be kept away from the crystal circuit to prevent induction from interfering with correct oscillation. see figure 6.10. the crystal and its load capacitors should be placed as close as possible to the xtal and extal pins. 103 xtal extal c l2 c l1 not allowed signal a signal b figure 6.10 notes on board design around external crystal input of external clock signal circuit configuration: an external clock signal can be input as shown in the examples in figure 6.11. in example (b) in figure 6.11, the external clock signal should be kept high during standby. if the xtal pin is left open, make sure the stray capacitance does not exceed 10 pf. extal xtal extal xtal 74hc04 external clock input open external clock input (a) connections with xtal pin left open (b) connections with inverted clock input at xtal pin figure 6.11 external clock input (example) 104 external clock input: the external clock signal should have the same frequency as the desired system clock ( ). clock timing parameters are given in table 6.7 and figure 6.12. table 6.7 clock timing v cc = 3.0 to 5.5 v item symbol min max unit test conditions low pulse width of external clock input t exl 40 ns figure 6.12 high pulse width of external clock input t exh 40 ns external clock rise time t exr 10 ns external clock fall time t exf 10 ns clock pulse t cl 0.3 0.7 t cyc < 5 mhz clock pulse t ch 0.3 0.7 t cyc < 5 mhz t exh t exl t ext t exr v cc figure 6.12 external clock input timing table 6.8 lists the external clock output stabilization delay time. figure 6.13 shows the timing for the external clock output stabilization delay time. the oscillator and duty correction circuit have the function of regulating the waveform of the external clock input to the extal pin. when the specified clock signal is input to the extal pin, internal clock signal output is confirmed after the elapse of the external clock output stabilization delay time (t dext ). as clock signal output is not confirmed during the t dext period, the reset signal should be driven low and the reset state maintained during this time. 105 table 6.8 external clock output stabilization delay time conditions: v cc = 3.0 to 5.5 v, av cc = 2.7 to 5.5 v, v ss = av ss = 0 v item symbol min max unit notes external clock output stabilization delay time t dext * 500 res stby (internal and external) res res figure 6.13 external clock output stabilization delay time 6.3 duty adjustment circuit when the clock frequency is 5 mhz or above, the duty adjustment circuit adjusts the duty cycle of the signal from the oscillator circuit to generate the system clock ( ). 6.4 prescaler the clock for the on-chip supporting modules ( p ) has either the same frequency as the system clock ( ) or this frequency divided by two, depending on the ckdbl bit. the prescaler divides the frequency of p to generate internal clock signals with frequencies from p /2 to p /4096. 106 107 section 7 i/o ports 7.1 overview the h8/3337 series and h8/3397 series have six 8-bit input/output ports, one 7-bit input/output port, and one 3-bit input/output port, and one 8-bit dedicated input port. table 7.1 lists the functions of each port in each operating mode. as table 7.1 indicates, the port pins are multiplexed, and the pin functions differ depending on the operating mode. each port has a data direction register (ddr) that selects input or output, and a data register (dr) that stores output data. if bit manipulation instructions will be executed on the port data direction registers, see ?otes on bit manipulation instructions?in section 2.5.5, bit manipulation instructions. ports 1, 2, 3, 4, 6, and 9 can drive one ttl load and a 90-pf capacitive load. ports 5 and 8 can drive one ttl load and a 30-pf capacitive load. ports 1 and 2 can drive leds (with 10-ma current sink). ports 1 to 6, 8, and 9 can drive a darlington pair. ports 1 to 3, and 6 have built-in mos pull-up transistors. for block diagrams of the ports, see appendix c, i/o port block diagrams. pin p8 6 of port 8 and pin p9 7 of port 9 can drive a bus buffer. for details of bus buffer drive, see section 13, i 2 c bus interface. 108 table 7.1 (a) port functions for h8/3337 series expanded modes single-chip mode port description pins mode 1 mode 2 mode 3 port 1 ? 8-bit i/o port ? can drive leds ? built-in input pull-ups p1 7 to p1 0 /a 7 to a 0 lower address output (a 7 to a 0 ) lower address output (a 7 to a 0 ) or general input general input/output (can also be used as key- scan output port) port 2 ? 8-bit i/o port ? can drive leds ? built-in input pull-ups p2 7 to p2 0 /a 15 to a 8 upper address output (a 15 to a 8 ) upper address output (a 15 to a 8 ) or general input general input/output (can also be used as key- scan output port) port 3 ? 8-bit i/o port ? built-in input pull-ups ? hif data bus p3 7 to p3 0 / hdb 7 to hdb 0 / d 7 to d 0 data bus (d 7 to d 0 ) data bus (d 7 to d 0 ) hif data bus (hdb 7 to hdb 0 ) or general input/ output port 4 ? 8-bit i/o port p4 7 /pw 1 p4 6 /pw 0 pwm timer 0/1 output (pw 0 , pw 1 ), or general input/ output p4 5 /tmri 1 /hirq 12 p4 4 /tmo 1 /hirq 1 p4 3 /tmci 1 /hirq 11 8-bit timer 1 input/output (tmci 1 , tmo 1 , tmri 1 ), host processor interrupt request output from hif (hirq 11 , hirq 1 , hirq 12 ), or general input/output p4 2 /tmri 0 p4 1 /tmo 0 p4 0 /tmci 0 8-bit timer 0 input/output (tmci 0 , tmo 0 , tmri 0 ) or general input/output port 5 ? 3-bit i/o port p5 2 /sck 0 p5 1 /rxd 0 p5 0 /txd 0 serial communication interface 0 input/output (txd 0 , rxd 0 , sck 0 ) or general input/output port 6 ? 8-bit i/o port ? built-in input pull-ups ? key sense interrupt input p6 7 / irq 7 / keyin 7 p6 6 /ftob/ irq 6 / keyin 6 p6 5 /ftid/ keyin 5 p6 4 /ftic/ keyin 4 p6 3 /ftib/ keyin 3 p6 2 /ftia/ keyin 2 p6 1 /ftoa/ keyin 1 p6 0 /ftci/ keyin 0 16-bit free-running timer input/output (ftci, ftoa, ftia, ftib, ftic, ftid, ftob), key sense interrupt input ( keyin 7 to keyin 0 ), external interrupt input ( irq 7 , irq 6 ), or general input/output 109 expanded modes single-chip mode port description pins mode 1 mode 2 mode 3 port 7 ? 8-bit input port p7 7 /an 7 /da 1 p7 6 /an 6 /da 0 a/d converter analog input (an 7 , an 6 ), d/a converter analog output (da 1 , da 0 ), or general input p7 5 to p7 0 an 5 to an 0 a/d converter analog input (an 5 to an 0 ) or general input port 8 ? 7-bit i/o port ? bus buffer drive capability (p8 6 ) p8 6 / irq 5 /sck 1 /scl p8 5 / cs 2 / irq 4 /rxd 1 p8 4 / iow / irq 3 /txd 1 serial communication interface 1 input/output (txd 1 , rxd 1 , sck 1 ), hif control input/output ( cs 2 / iow ), i 2 c clock input/output (scl), external interrupt input ( irq 5 , irq 4 , irq 3 ) or general input/output p8 3 / ior p8 2 / cs 1 p8 1 /ga 20 p8 0 /ha 0 hif control input/output (ha 0 , ga 20 , cs 1 , ior), or general input/output port 9 ? 8-bit i/o port ? bus buffer drive capability (p9 7 ) p9 7 / wait /sda expanded data bus control input ( wait ), i 2 c data input/output (sda), or general input/output i 2 c data input/output (sda) or general input/ output p9 6 / system clock (? output system clock (? output ?output or general input p9 5 / as p9 4 / wr p9 3 / rd expanded data bus ( rd , wr , as ) expanded data bus ( rd , wr , as ) general input/output p9 2 / irq 0 p9 1 / irq 1 / eiow p9 0 / adtrg / irq 2 / ecs 2 hif control input/output ( ecs 2 , eiow ), a/d converter trigger input ( adtrg ), external interrupt ( irq 2 to irq 0 ), or general input/output 110 table 7.1 (b) port functions for h8/3397 series expanded modes single-chip mode mode 3 port description pins mode 1 mode 2 master mode port 1 ? 8-bit i/o port ? can drive leds ? built-in input pull- ups p1 7 to p1 0 /a 7 to a 0 lower address output (a 7 to a 0 ) lower address output (a 7 to a 0 ) or general input general input/output (can also be used as key- scan output port) port 2 ? 8-bit i/o port ? can drive leds ? built-in input pull-ups p2 7 to p2 0 /a 15 to a 8 upper address output (a 15 to a 8 ) upper address output (a 15 to a 8 ) or general input general input/output (can also be used as key- scan output port) port 3 ? 8-bit i/o port ? built-in input pull-ups p3 7 to p3 0 /d 7 to d 0 data bus (d 7 to d 0 ) data bus (d 7 to d 0 ) general input/output port 4 ? 8-bit i/o port p4 7 /pw 1 p4 6 /pw 0 pwm timer 0/1 output (pw 0 , pw 1 ), or general input/output p4 5 /tmri 1 p4 4 /tmo 1 p4 3 /tmci 1 8-bit timer 1 input/output (tmci 1 , tmo 1 , tmri 1 ), or general input/output p4 2 /tmri 0 p4 1 /tmo 0 p4 0 /tmci 0 8-bit timer 0 input/output (tmci 0 , tmo 0 , tmri 0 ) or general input/output port 5 ? 3-bit i/o port p5 2 /sck 0 p5 1 /rxd 0 p5 0 /txd 0 serial communication interface 0 input/output (txd 0 , rxd 0 , sck 0 ) or general input/output port 6 ? 8-bit i/o port ? built-in input pull-ups p6 7 / irq 7 / keyin 7 p6 6 /ftob/ irq 6 / keyin 6 p6 5 /ftid/ keyin 5 p6 4 /ftic/ keyin 4 p6 3 /ftib/ keyin 3 p6 2 /ftia/ keyin 2 p6 1 /ftoa/ keyin 1 p6 0 /ftci/ keyin 0 16-bit free-running timer input/output (ftci, ftoa, ftia, ftib, ftic, ftid, ftob), key sense interrupt input ( keyin 7 to keyin 0 ), external interrupt input ( irq 7 , irq 6 ), or general input/output port 7 ? 8-bit input port p7 7 to p7 0 /an 7 to an 0 a/d converter analog input (an 7 to an 0 ) or general input 111 expanded modes single-chip mode mode 3 port description pins mode 1 mode 2 master mode port 8 ? 7-bit i/o port p8 6 / irq 5 /sck 1 p8 5 / irq 4 /rxd 1 p8 4 / irq 3 /txd 1 serial communication interface 1 input/output (txd 1 , rxd 1 , sck 1 ), external interrupt input ( irq 5 , irq 4 , irq 3 ), or general input/output p8 3 p8 2 p8 1 p8 0 general input/output general input/output general input/output port 9 ? 8-bit i/o port p9 7 / wait expanded data bus control input ( wait ), or general input/output general input/output p9 6 / system clock (? output system clock (? output ?output or general input p9 5 / as p9 4 / wr p9 3 / rd expanded data bus control output ( rd , wr , as ) expanded data bus control output ( rd , wr , as ) general input/output p9 2 / irq 0 p9 1 / irq 1 external interrupt ( irq 0 , irq 1 ) or general input/output p9 0 / adtrg / irq 2 a/d converter external trigger input ( adtrg ), external interrupt input ( irq 2 ), or general input/output 112 7.2 port 1 7.2.1 overview port 1 is an 8-bit input/output port with the pin configuration shown in figure 7.1. the pin functions differ depending on the operating mode. port 1 has built-in, software-controllable mos input pull-up transistors that can be used in modes 2 and 3. pins in port 1 can drive one ttl load and a 90-pf capacitive load. they can also drive leds and darlington transistors. p1 7 /a 7 p1 6 /a 6 p1 5 /a 5 p1 4 /a 4 p1 3 /a 3 p1 2 /a 2 p1 1 /a 1 p1 0 /a 0 port 1 port 1 pins a 7 (output) a 6 (output) a 5 (output) a 4 (output) a 3 (output) a 2 (output) a 1 (output) a 0 (output) pin configuration in mode 1 (expanded mode with on-chip rom disabled) a 7 (output)/p1 7 (input) a 6 (output)/p1 6 (input) a 5 (output)/p1 5 (input) a 4 (output)/p1 4 (input) a 3 (output)/p1 3 (input) a 2 (output)/p1 2 (input) a 1 (output)/p1 1 (input) a 0 (output)/p1 0 (input) pin configuration in mode 2 (expanded mode with on-chip rom enabled) p1 7 (input/output) p1 6 (input/output) p1 5 (input/output) p1 4 (input/output) p1 3 (input/output) p1 2 (input/output) p1 1 (input/output) p1 0 (input/output) pin configuration in mode 3 (single-chip mode) figure 7.1 port 1 pin configuration 113 7.2.2 register configuration and descriptions table 7.2 summarizes the port 1 registers. table 7.2 port 1 registers name abbreviation read/write initial value address port 1 data direction register p1ddr w h'ff (mode 1) h'00 (modes 2 and 3) h'ffb0 port 1 data register p1dr r/w h'00 h'ffb2 port 1 input pull-up control register p1pcr r/w h'00 h'ffac port 1 data direction register (p1ddr) bit 76543210 p1 7 ddr p1 6 ddr p1 5 ddr p1 4 ddr p1 3 ddr p1 2 ddr p1 1 ddr p1 0 ddr mode 1 initial value 1 1 1 1 1 1 1 1 read/write modes 2 and 3 initial value 0 0 0 0 0 0 0 0 read/write w w w w w w w w p1ddr controls the input/output direction of each pin in port 1. mode 1: the p1ddr values are fixed at 1. port 1 consists of lower address output pins. p1ddr values cannot be modified and are always read as 1. in hardware standby mode, the address bus is in the high-impedance state. mode 2: a pin in port 1 is used for address output if the corresponding p1ddr bit is set to 1, and for general input if this bit is cleared to 0. mode 3: a pin in port 1 is used for general output if the corresponding p1ddr bit is set to 1, and for general input if this bit is cleared to 0. in modes 2 and 3, p1ddr is a write-only register. read data is invalid. if read, all bits always read 1. p1ddr is initialized to h'00 by a reset and in hardware standby mode. in software standby mode it retains its existing values, so if a transition to software standby mode occurs while a p1ddr bit is set to 1, the corresponding pin remains in the output state. 114 port 1 data register (p1dr) bit 76543210 p1 7 p1 6 p1 5 p1 4 p1 3 p1 2 p1 1 p1 0 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w p1dr is an 8-bit register that stores data for pins p1 7 to p1 0 . when a p1ddr bit is set to 1, if port 1 is read, the value in p1dr is obtained directly, regardless of the actual pin state. when a p1ddr bit is cleared to 0, if port 1 is read the pin state is obtained. p1dr is initialized to h'00 by a reset and in hardware standby mode. in software standby mode it retains its existing values. port 1 input pull-up control register (p1pcr) bit 76543210 p1 7 pcr p1 6 pcr p1 5 pcr p1 4 pcr p1 3 pcr p1 2 pcr p1 1 pcr p1 0 pcr initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w p1pcr is an 8-bit readable/writable register that controls the input pull-up transistors in port 1. if a p1ddr bit is cleared to 0 (designating input) and the corresponding p1pcr bit is set to 1, the input pull-up transistor is turned on. p1pcr is initialized to h'00 by a reset and in hardware standby mode. in software standby mode it retains its existing values. 115 7.2.3 pin functions in each mode port 1 has different pin functions in different modes. a separate description for each mode is given below. pin functions in mode 1: in mode 1 (expanded mode with on-chip rom disabled), port 1 is automatically used for lower address output (a 7 to a 0 ). figure 7.2 shows the pin functions in mode 1. a 7 (output) a 6 (output) a 5 (output) a 4 (output) a 3 (output) a 2 (output) a 1 (output) a 0 (output) port 1 figure 7.2 pin functions in mode 1 (port 1) 116 mode 2: in mode 2 (expanded mode with on-chip rom enabled), port 1 can provide lower address output pins and general input pins. each pin becomes a lower address output pin if its p1ddr bit is set to 1, and a general input pin if this bit is cleared to 0. following a reset, all pins are input pins. to be used for address output, their p1ddr bits must be set to 1. figure 7.3 shows the pin functions in mode 2. a 7 (output) a 6 (output) a 5 (output) a 4 (output) a 3 (output) a 2 (output) a 1 (output) a 0 (output) when p1ddr = 1 p1 7 (input) p1 6 (input) p1 5 (input) p1 4 (input) p1 3 (input) p1 2 (input) p1 1 (input) p1 0 (input) when p1ddr = 0 port 1 figure 7.3 pin functions in mode 2 (port 1) mode 3: in mode 3 (single-chip mode), the input or output direction of each pin can be selected individually. a pin becomes a general input pin when its p1ddr bit is cleared to 0 and a general output pin when this bit is set to 1. figure 7.4 shows the pin functions in mode 3. p1 7 (input/output) p1 6 (input/output) p1 5 (input/output) p1 4 (input/output) p1 3 (input/output) p1 2 (input/output) p1 1 (input/output) p1 0 (input/output) port 1 figure 7.4 pin functions in mode 3 (port 1) 117 7.2.4 input pull-up transistors port 1 has built-in programmable input pull-up transistors that are available in modes 2 and 3. the pull-up for each bit can be turned on and off individually. to turn on an input pull-up in mode 2 or 3, set the corresponding p1pcr bit to 1 and clear the corresponding p1ddr bit to 0. p1pcr is cleared to h'00 by a reset and in hardware standby mode, turning all input pull-ups off. in software standby mode, the previous state is maintained. table 7.3 indicates the states of the input pull-up transistors in each operating mode. table 7.3 states of input pull-up transistors (port 1) mode reset hardware standby software standby other operating modes 1 off off off off 2 off off on/off on/off 3 off off on/off on/off notes: off: the input pull-up transistor is always off. on/off: the input pull-up transistor is on if p1pcr = 1 and p1ddr = 0, but off otherwise. 118 7.3 port 2 7.3.1 overview port 2 is an 8-bit input/output port with the pin configuration shown in figure 7.5. the pin functions differ depending on the operating mode. port 2 has built-in, software-controllable mos input pull-up transistors that can be used in modes 2 and 3. pins in port 2 can drive one ttl load and a 90-pf capacitive load. they can also drive leds and darlington transistors. p2 7 /a 15 p2 6 /a 14 p2 5 /a 13 p2 4 /a 12 p2 3 /a 11 p2 2 /a 10 p2 1 /a 9 p2 0 /a 8 port 2 port 2 pins a 15 (output) a 14 (output) a 13 (output) a 12 (output) a 11 (output) a 10 (output) a 9 (output) a 8 (output) pin configuration in mode 1 (expanded mode with on-chip rom disabled) a 15 (output)/p2 7 (input) a 14 (output)/p2 6 (input) a 13 (output)/p2 5 (input) a 12 (output)/p2 4 (input) a 11 (output)/p2 3 (input) a 10 (output)/p2 2 (input) a 9 (output)/p2 1 (input) a 8 (output)/p2 0 (input) pin configuration in mode 2 (expanded mode with on-chip rom enabled) p2 7 (input/output) p2 6 (input/output) p2 5 (input/output) p2 4 (input/output) p2 3 (input/output) p2 2 (input/output) p2 1 (input/output) p2 0 (input/output) pin configuration in mode 3 (single-chip mode) figure 7.5 port 2 pin configuration 119 7.3.2 register configuration and descriptions table 7.4 summarizes the port 2 registers. table 7.4 port 2 registers name abbreviation read/write initial value address port 2 data direction register p2ddr w h'ff (mode 1) h'00 (modes 2 and 3) h'ffb1 port 2 data register p2dr r/w h'00 h'ffb3 port 2 input pull-up control register p2pcr r/w h'00 h'ffad port 2 data direction register (p2ddr) bit 76543210 p2 7 ddr p2 6 ddr p2 5 ddr p2 4 ddr p2 3 ddr p2 2 ddr p2 1 ddr p2 0 ddr mode 1 initial value 1 1 1 1 1 1 1 1 read/write modes 2 and 3 initial value 0 0 0 0 0 0 0 0 read/write w w w w w w w w p2ddr controls the input/output direction of each pin in port 2. mode 1: the p2ddr values are fixed at 1. port 2 consists of upper address output pins. p2ddr values cannot be modified and are always read as 1. in hardware standby mode, the address bus is in the high-impedance state. mode 2: a pin in port 2 is used for address output if the corresponding p2ddr bit is set to 1, and for general input if this bit is cleared to 0. mode 3: a pin in port 2 is used for general output if the corresponding p2ddr bit is set to 1, and for general input if this bit is cleared to 0. in modes 2 and 3, p2ddr is a write-only register. read data is invalid. if read, all bits always read 1. p2ddr is initialized to h'00 by a reset and in hardware standby mode. in software standby mode it retains its existing values, so if a transition to software standby mode occurs while a p2ddr bit is set to 1, the corresponding pin remains in the output state. 120 port 2 data register (p2dr) bit 76543210 p2 7 p2 6 p2 5 p2 4 p2 3 p2 2 p2 1 p2 0 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w p2dr is an 8-bit register that stores data for pins p2 7 to p2 0 . when a p2ddr bit is set to 1, if port 2 is read, the value in p2dr is obtained directly, regardless of the actual pin state. when a p2ddr bit is cleared to 0, if port 2 is read the pin state is obtained. p2dr is initialized to h'00 by a reset and in hardware standby mode. in software standby mode it retains its existing values. port 2 input pull-up control register (p2pcr) bit 76543210 p2 7 pcr p2 6 pcr p2 5 pcr p2 4 pcr p2 3 pcr p2 2 pcr p2 1 pcr p1 0 pcr initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w p2pcr is an 8-bit readable/writable register that controls the input pull-up transistors in port 2. if a p2ddr bit is cleared to 0 (designating input) and the corresponding p2pcr bit is set to 1, the input pull-up transistor is turned on. p2pcr is initialized to h'00 by a reset and in hardware standby mode. in software standby mode it retains its existing values. 121 7.3.3 pin functions in each mode port 2 has different pin functions in different modes. a separate description for each mode is given below. pin functions in mode 1: in mode 1 (expanded mode with on-chip rom disabled), port 2 is automatically used for upper address output (a 15 to a 8 ). figure 7.6 shows the pin functions in mode 1. a 15 (output) a 14 (output) a 13 (output) a 12 (output) a 11 (output) a 10 (output) a 9 (output) a 8 (output) port 2 figure 7.6 pin functions in mode 1 (port 2) 122 mode 2: in mode 2 (expanded mode with on-chip rom enabled), port 2 can provide upper address output pins and general input pins. each pin becomes an upper address output pin if its p2ddr bit is set to 1, and a general input pin if this bit is cleared to 0. following a reset, all pins are input pins. to be used for address output, their p2ddr bits must be set to 1. figure 7.7 shows the pin functions in mode 2. a 15 (output) a 14 (output) a 13 (output) a 12 (output) a 11 (output) a 10 (output) a 9 (output) a 8 (output) when p2ddr = 1 p2 7 (input) p2 6 (input) p2 5 (input) p2 4 (input) p2 3 (input) p2 2 (input) p2 1 (input) p2 0 (input) when p2ddr = 0 port 2 figure 7.7 pin functions in mode 2 (port 2) mode 3: in mode 3 (single-chip mode), the input or output direction of each pin can be selected individually. a pin becomes a general input pin when its p2ddr bit is cleared to 0, and a general output pin when this bit is set to 1. figure 7.8 shows the pin functions in mode 3. p2 7 (input/output) p2 6 (input/output) p2 5 (input/output) p2 4 (input/output) p2 3 (input/output) p2 2 (input/output) p2 1 (input/output) p2 0 (input/output) port 2 figure 7.8 pin functions in mode 3 (port 2) 123 7.3.4 input pull-up transistors port 2 has built-in programmable input pull-up transistors that are available in modes 2 and 3. the pull-up for each bit can be turned on and off individually. to turn on an input pull-up in mode 2 or 3, set the corresponding p2pcr bit to 1 and clear the corresponding p2ddr bit to 0. p2pcr is cleared to h'00 by a reset and in hardware standby mode, turning all input pull-ups off. in software standby mode, the previous state is maintained. table 7.5 indicates the states of the input pull-up transistors in each operating mode. table 7.5 states of input pull-up transistors (port 2) mode reset hardware standby software standby other operating modes 1 off off off off 2 off off on/off on/off 3 off off on/off on/off notes: off: the input pull-up transistor is always off. on/off: the input pull-up transistor is on if p2pcr = 1 and p2ddr = 0, but off otherwise. 7.4 port 3 7.4.1 overview port 3 is an 8-bit input/output port that is multiplexed with the data bus and host interface data bus. figure 7.9 shows the pin configuration of port 3. the pin functions differ depending on the operating mode. port 3 has built-in, software-controllable mos input pull-up transistors that can be used in mode 3. pins in port 3 can drive one ttl load and a 90-pf capacitive load. they can also drive a darlington pair. 124 p3 7 /d 7 (input/output) p3 6 /d 6 (input/output) p3 5 /d 5 (input/output) p3 4 /d 4 (input/output) p3 3 /d 3 (input/output) p3 2 /d 2 (input/output) p3 1 /d 1 (input/output) p3 0 /d 0 (input/output) port 3 port 3 pins d 7 (input/output) d 6 (input/output) d 5 (input/output) d 4 (input/output) d 3 (input/output) d 2 (input/output) d 1 (input/output) d 0 (input/output) pin configuration in mode 1 (expanded mode with on-chip rom disabled) and mode 2 (expanded mode with on-chip rom enabled) p3 7 (input/output) p3 6 (input/output) p3 5 (input/output) p3 4 (input/output) p3 3 (input/output) p3 2 (input/output) p3 1 (input/output) p3 0 (input/output) pin configuration in mode 3 (single-chip mode) master mode hdb 7 (input/output) * hdb 6 (input/output) * hdb 5 (input/output) * hdb 4 (input/output) * hdb 3 (input/output) * hdb 2 (input/output) * hdb 1 (input/output) * hdb 0 (input/output) * slave mode note: * the hdb 7 to hdb 0 pin functions apply to the h8/3337 series only.the h8/3397 series does not support a host interface, and therefore has no hdb 7 to hdb 0 pin functions. figure 7.9 port 3 pin configuration 125 7.4.2 register configuration and descriptions table 7.6 summarizes the port 3 registers. table 7.6 port 3 registers name abbreviation read/write initial value address port 3 data direction register p3ddr w h'00 h'ffb4 port 3 data register p3dr r/w h'00 h'ffb6 port 3 input pull-up control register p3pcr r/w h'00 h'ffae port 3 data direction register (p3ddr) bit 76543210 p3 7 ddr p3 6 ddr p3 5 ddr p3 4 ddr p3 3 ddr p3 2 ddr p3 1 ddr p3 0 ddr initial value 0 0 0 0 0 0 0 0 read/write w w w w w w w w p3ddr is an 8-bit readable/writable register that controls the input/output direction of each pin in port 3. p3ddr is a write-only register. read data is invalid. if read, all bits always read 1. modes 1 and 2: in mode 1 (expanded mode with on-chip rom disabled) and mode 2 (expanded mode with on-chip rom enabled), the input/output directions designated by p3ddr are ignored. port 3 automatically consists of the input/output pins of the 8-bit data bus (d 7 to d 0 ). the data bus is in the high-impedance state during reset, and during hardware and software standby. mode 3: a pin in port 3 is used for general output if the corresponding p3ddr bit is set to 1, and for general input if this bit is cleared to 0. p3ddr is initialized to h'00 by a reset and in hardware standby mode. in software standby mode it retains its existing values, so if a transition to software standby mode occurs while a p3ddr bit is set to 1, the corresponding pin remains in the output state. 126 port 3 data register (p3dr) bit 76543210 p3 7 p3 6 p3 5 p3 4 p3 3 p3 2 p3 1 p3 0 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w p3dr is an 8-bit register that stores data for pins p3 7 to p3 0 . when a p3ddr bit is set to 1, if port 3 is read, the value in p3dr is obtained directly, regardless of the actual pin state. when a p3ddr bit is cleared to 0, if port 3 is read the pin state is obtained. p3dr is initialized to h'00 by a reset and in hardware standby mode. in software standby mode it retains its existing values. port 3 input pull-up control register (p3pcr) bit 76543210 p3 7 pcr p3 6 pcr p3 5 pcr p3 4 pcr p3 3 pcr p3 2 pcr p3 1 pcr p3 0 pcr initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w p3pcr is an 8-bit readable/writable register that controls the input pull-up mostransistors in port 3. if a p3ddr bit is cleared to 0 (designating input) and the corresponding p3pcr bit is set to 1, the input pull-up transistor is turned on. p3pcr is initialized to h'00 by a reset and in hardware standby mode. in software standby mode it retains its existing values. the input pull-ups cannot be used in slave mode (when the host interface is enabled). 127 7.4.3 pin functions in each mode port 3 has different pin functions in different modes. a separate description for each mode is given below. pin functions in modes 1 and 2: in mode 1 (expanded mode with on-chip rom disabled) and mode 2 (expanded mode with on-chip rom enabled), port 3 is automatically used for the input/output pins of the 8-bit data bus (d 7 to d 0 ). figure 7.10 shows the pin functions in modes 1 and 2. d 7 (input/output) d 6 (input/output) d 5 (input/output) d 4 (input/output) d 3 (input/output) d 2 (input/output) d 1 (input/output) d 0 (input/output) port 3 modes 1 and 2 figure 7.10 pin functions in modes 1 and 2 (port 3) 128 mode 3: in mode 3 (single-chip mode), when the host interface enable bit (hie) is cleared to 0 in the system control register (syscr), port 3 is a general-purpose input/output port. a pin becomes an output pin when its p3ddr bit is set to 1, and an input pin when this bit is cleared to 0. when the hie bit is set to 1, selecting slave mode, port 3 becomes the host interface data bus (hdb 7 to hdb 0 ). for details, see section 14, host interface. figure 7.11 shows the pin functions in mode 3. p3 7 (input/output)/hdb 7 (input/output) * p3 6 (input/output)/hdb 6 (input/output) * p3 5 (input/output)/hdb 5 (input/output) * p3 4 (input/output)/hdb 4 (input/output) * p3 3 (input/output)/hdb 3 (input/output) * p3 2 (input/output)/hdb 2 (input/output) * p3 1 (input/output)/hdb 1 (input/output) * p3 0 (input/output)/hdb 0 (input/output) * port 3 note: * the hdb 7 to hdb 0 pin functions apply to the h8/3337 series only. the h8/3397 series does not support a host interface, and therefore has no hdb 7 to hdb 0 pin functions. figure 7.11 pin functions in mode 3 (port 3) 129 7.4.4 input pull-up transistors port 3 has built-in programmable input pull-up transistors that are available in mode 3. the pull-up for each bit can be turned on and off individually. to turn on an input pull-up in mode 3, set the corresponding p3pcr bit to 1 and clear the corresponding p3ddr bit to 0. p3pcr is cleared to h'00 by a reset and in hardware standby mode, turning all input pull-ups off. in software standby mode, the previous state is maintained. table 7.7 indicates the states of the input pull-up transistors in each operating mode. table 7.7 states of input pull-up transistors (port 3) mode reset hardware standby software standby other operating modes 1 off off off off 2 off off off off 3 off off on/off on/off notes: off: the input pull-up transistor is always off. on/off: the input pull-up transistor is on if p3pcr = 1 and p3ddr = 0, but off otherwise. 7.5 port 4 7.5.1 overview port 4 is an 8-bit input/output port that is multiplexed with input/output pins (tmri 0 , tmri 1 , tmci 0 , tmci 1 , tmo 0 , tmo 1 ) of 8-bit timers 0 and 1 and output pins (pw 0 , pw 1 ) of pwm timers 0 and 1. in slave mode, p4 3 to p4 5 output host interrupt requests. pins not used by timers or for host interrupt requests are available for general input/output. figure 7.12 shows the pin configuration of port 4. pins in port 4 can drive one ttl load and a 90-pf capacitive load. they can also drive a darlington pair. 130 p4 7 (input/output)/pw 1 (output) p4 6 (input/output)/pw 0 (output) p4 5 (input/output)/tmri 1 (input) p4 4 (input/output)/tmo 1 (output) p4 3 (input/output)/tmci 1 (input) p4 2 (input/output)/tmri 0 (input) p4 1 (input/output)/tmo 0 (output) p4 0 (input/output)/tmci 0 (input) port 4 port 4 pins p4 7 (input/output)/pw 1 (output) p4 6 (input/output)/pw 0 (output) p4 5 (input/output)/tmri 1 (input) p4 4 (input/output)/tmo 1 (output) p4 3 (input/output)/tmci 1 (input) p4 2 (input/output)/tmri 0 (input) p4 1 (input/output)/tmo 0 (output) p4 0 (input/output)/tmci 0 (input) pin configuration in mode 3 (single-chip mode) pin configuration in mode 1 (expanded mode with on-chip rom disabled) and mode 2 (expanded mode with on-chip rom enabled) master mode p4 7 (input/output)/pw 1 (output) p4 6 (input/output)/pw 0 (output) p4 5 (input)/hirq 12 (output) * /tmri 1 (input) p4 4 (input)/hirq 1 (output) * /tmo 1 (output) p4 3 (input)/hirq 11 (output) * /tmci 1 (input) p4 2 (input/output)/tmri 0 (input) p4 1 (input/output)/tmo 0 (output) p4 0 (input/output)/tmci 0 (input) slave mode note: * the hirq 12 , hirq 1 , and hirq 11 pin functions apply to the h8/3337 series only. the h8/3397 series does not support a host interface, and therefore does not have these pin functions. figure 7.12 port 4 pin configuration 131 7.5.2 register configuration and descriptions table 7.8 summarizes the port 4 registers. table 7.8 port 4 registers name abbreviation read/write initial value address port 4 data direction register p4ddr w h'00 h'ffb5 port 4 data register p4dr r/w h'00 h'ffb7 port 4 data direction register (p4ddr) bit 76543210 p4 7 ddr p4 6 ddr p4 5 ddr p4 4 ddr p4 3 ddr p4 2 ddr p4 1 ddr p4 0 ddr initial value 0 0 0 0 0 0 0 0 read/write w w w w w w w w p4ddr is an 8-bit readable/writable register that controls the input/output direction of each pin in port 4. a pin functions as an output pin if the corresponding p4ddr bit is set to 1, and as an input pin if this bit is cleared to 0. p4ddr is a write-only register. read data is invalid. if read, all bits always read 1. p4ddr is initialized to h'00 by a reset and in hardware standby mode. in software standby mode it retains its existing values, so if a transition to software standby mode occurs while a p4ddr bit is set to 1, the corresponding pin remains in the output state. if a transition to software standby mode occurs while port 4 is being used by an on-chip supporting module (for example, for 8-bit timer output), the on-chip supporting module will be initialized, so the pin will revert to general-purpose input/output, controlled by p4ddr and p4dr. 132 port 4 data register (p4dr) bit 76543210 p4 7 p4 6 p4 5 p4 4 p4 3 p4 2 p4 1 p4 0 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w p4dr is an 8-bit register that stores data for pins p4 7 to p4 0 . when a p4ddr bit is set to 1, if port 4 is read, the value in p4dr is obtained directly, regardless of the actual pin state. when a p4ddr bit is cleared to 0, if port 4 is read the pin state is obtained. this also applies to pins used by on- chip supporting modules. p4dr is initialized to h'00 by a reset and in hardware standby mode. in software standby mode it retains its existing values. 133 7.5.3 pin functions port 4 has different pin functions depending on whether the chip is or is not operating in slave mode. table 7.9 indicates the pin functions of port 4. table 7.9 port 4 pin functions pin pin functions and selection method p4 7 /pw 1 bit oe in tcr of pwm timer 1 and bit p4 7 ddr select the pin function as follows oe 0 1 p4 7 ddr 0101 pin function p4 7 input p4 7 output pw 1 output p4 6 /pw 0 bit oe in tcr of pwm timer 0 and bit p4 6 ddr select the pin function as follows oe 0 1 p4 6 ddr 0101 pin function p4 6 input p4 6 output pw 0 output p4 5 /tmri 1 / bit p4 5 ddr and the operating mode select the pin function as follows hirq 12 * p4 5 ddr 0 1 operating mode not slave mode slave mode pin function p4 5 input p4 5 output hirq 12 output * tmri 1 input tmri 1 input is usable when bits cclr1 and cclr0 are both set to 1 in tcr of 8-bit timer 1 note: * h8/3337 series only. h8/3397 series ics have no hirq 12 pin function. p4 4 /tmo 1 / hirq 1 * bits os3 to os0 in tcsr of 8-bit timer 1, bit p4 4 ddr, and the operating mode select the pin function as follows os3 to 0 all 0 not all 0 p4 4 ddr 0 1 operating mode not slave mode slave mode pin function p4 4 input p4 4 output hirq 1 output * tmo 1 output note: * h8/3337 series only. h8/3397 series ics have no hirq 1 pin function. 134 pin pin functions and selection method p4 3 /tmci 1 / bit p4 3 ddr and the operating mode select the pin function as follows hirq 11 * p4 3 ddr 0 1 operating mode not slave mode slave mode pin function p4 3 input p4 3 output hirq 11 output * tmci 1 input tmci 1 input is usable when bits cks2 to cks0 in tcr of 8-bit timer 1 select an external clock source note: * h8/3337 series only. h8/3397 series ics have no hirq 11 pin function. p4 2 /tmri 0 p4 2 ddr 0 1 pin function p4 2 input p4 2 output tmri 0 input tmri 0 input is usable when bits cclr1 and cclr0 are both set to 1 in tcr of 8-bit timer 0 p4 1 /tmo 0 bits os3 to os0 in tcsr of 8-bit timer 0 and bit p4 1 ddr select the pin function as follows os3 to 0 all 0 not all 0 p4 1 ddr 0101 pin function p4 1 input p4 1 output tmo 0 output p4 0 /tmci 0 p4 0 ddr 0 1 pin function p4 0 input p4 0 output tmci 0 input tmci 0 input is usable when bits cks2 to cks0 in tcr of 8-bit timer 0 select an external clock source 135 7.6 port 5 7.6.1 overview port 5 is a 3-bit input/output port that is multiplexed with input/output pins (txd 0 , rxd 0 , sck 0 ) of serial communication interface 0. the port 5 pin functions are the same in all operating modes. figure 7.13 shows the pin configuration of port 5. pins in port 5 can drive one ttl load and a 30-pf capacitive load. they can also drive a darlington pair. p5 2 (input/output)/sck 0 (input/output) p5 1 (input/output)/rxd 0 (input) p5 0 (input/output)/txd 0 (output) port 5 pins port 5 figure 7.13 port 5 pin configuration 7.6.2 register configuration and descriptions table 7.10 summarizes the port 5 registers. table 7.10 port 5 registers name abbreviation read/write initial value address port 5 data direction register p5ddr w h'f8 h'ffb8 port 5 data register p5dr r/w h'f8 h'ffba 136 port 5 data direction register (p5ddr) bit 76543210 p5 2 ddr p5 1 ddr p5 0 ddr initial value 1 1 1 1 1 0 0 0 read/write r/w r/w r/w p5ddr is an 8-bit register that controls the input/output direction of each pin in port 5. a pin functions as an output pin if the corresponding p5ddr bit is set to 1, and as an input pin if this bit is cleared to 0. p5ddr is a write-only register. read data is invalid. bits 7 to 3 are reserved. if read, these bits always read 1. p5ddr is initialized to h'f8 by a reset and in hardware standby mode. in software standby mode it retains its existing values, so if a transition to software standby mode occurs while a p5ddr bit is set to 1, the corresponding pin remains in the output state. if a transition to software standby mode occurs while port 5 is being used by the sci, the sci will be initialized, so the pin will revert to general-purpose input/output, controlled by p5ddr and p5dr. port 5 data register (p5dr) bit 76543210 p5 2 p5 1 p5 0 initial value 1 1 1 1 1 0 0 0 read/write r/w r/w r/w p5dr is an 8-bit register that stores data for pins p5 2 to p5 0 . bits 7 to 3 are reserved. they cannot be modified, and are always read as 1. when a p5ddr bit is set to 1, if port 5 is read, the value in p5dr is obtained directly, regardless of the actual pin state. when a p5ddr bit is cleared to 0, if port 5 is read the pin state is obtained. this also applies to pins used as sci pins. p5dr is initialized to h'f8 by a reset and in hardware standby mode. in software standby mode it retains its existing values. 137 7.6.3 pin functions port 5 has the same pin functions in each operating mode. all pins can also be used as sci input/output pins. table 7.11 indicates the pin functions of port 5. table 7.11 port 5 pin functions pin pin functions and selection method p5 2 /sck 0 bit c/ a in smr of sci0, bits cke0 and cke1 in scr of sci0, and bit p5 2 ddr select the pin function as follows cke1 0 1 c/ a 01 cke0 0 1 p5 2 ddr 0 1 pin function p5 2 input p5 2 output sck 0 output sck 0 output sck 0 input p5 1 /rxd 0 bit re in scr of sci0 and bit p5 1 ddr select the pin function as follows re 0 1 p5 1 ddr 0 1 pin function p5 1 input p5 1 output rxd 0 input p5 0 /txd 0 bit te in scr of sci0 and bit p5 0 ddr select the pin function as follows te 0 1 p5 0 ddr 0 1 pin function p5 0 input p5 0 output txd 0 output 138 7.7 port 6 7.7.1 overview port 6 is an 8-bit input/output port that is multiplexed with input/output pins (ftoa, ftob, ftia to ftid, ftci) of the 16-bit free-running timer (frt), with key-sense input pins, and with irq irq p6 7 (input/output)/ irq 7 (input)/ keyin 7 (input) p6 6 (input/output)/ftob (output)/ irq 6 (input)/ keyin 6 (input) p6 5 (input/output)/ftid (input)/ keyin 5 (input) p6 4 (input/output)/ftic (input)/ keyin 4 (input) p6 3 (input/output)/ftib (input)/ keyin 3 (input) p6 2 (input/output)/ftia (input)/ keyin 2 (input) p6 1 (input/output)/ftoa (output)/ keyin 1 (input) p6 0 (input/output)/ftci (input)/ keyin 0 (input) port 6 port 6 pins figure 7.14 port 6 pin configuration 7.7.2 register configuration and descriptions table 7.12 summarizes the port 6 registers. table 7.12 port 6 registers name abbreviation read/write initial value address port 6 data direction register p6ddr w h'00 h'ffb9 port 6 data register p6dr r/w h'00 h'ffbb port 6 input pull-up control register kmpcr r/w h'00 h'fff2 139 port 6 data direction register (p6ddr) bit 76543210 p6 7 ddr p6 6 ddr p6 5 ddr p6 4 ddr p6 3 ddr p6 2 ddr p6 1 ddr p6 0 ddr initial value 0 0 0 0 0 0 0 0 read/write w w w w w w w w p6ddr is an 8-bit readable/writable register that controls the input/output direction of each pin in port 6. a pin functions as an output pin if the corresponding p6ddr bit is set to 1, and as an input pin if this bit is cleared to 0. p6ddr is a write-only register. read data is invalid. if read, all bits always read 1. p6ddr is initialized to h'00 by a reset and in hardware standby mode. in software standby mode it retains its existing values, so if a transition to software standby mode occurs while a p6ddr bit is set to 1, the corresponding pin remains in the output state. if a transition to software standby mode occurs while port 6 is being used by the free-running timer, the timer will be initialized, so the pin will revert to general-purpose input/output, controlled by p6ddr and p6dr. port 6 data register (p6dr) bit 76543210 p6 7 p6 6 p6 5 p6 4 p6 3 p6 2 p6 1 p6 0 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w p6dr is an 8-bit register that stores data for pins p6 7 to p6 0 . when a p6ddr bit is set to 1, if port 6 is read, the value in p6dr is obtained directly, regardless of the actual pin state. when a p6ddr bit is cleared to 0, if port 6 is read the pin state is obtained. this also applies to pins used as frt pins. p6dr is initialized to h'00 by a reset and in hardware standby mode. in software standby mode it retains its existing values. 140 port 6 input pull-up control register (kmpcr) bit 76543210 km 7 pcr km 6 pcr km 5 pcr km 4 pcr km 3 pcr km 2 pcr km 1 pcr km 0 pcr initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w kmpcr is an 8-bit readable/writable register that controls the input pull-up transistors in port 6. if a p6ddr bit is cleared to 0 (designating input) and the corresponding kmpcr bit is set to 1, the input pull-up transistor is turned on. kmpcr is initialized to h'00 by a reset and in hardware standby mode. in software standby mode it retains its existing values. 141 7.7.3 pin functions port 6 has the same pin functions in all operating modes. the pins are multiplexed with frt input/output, irq 6 and irq 7 input, and key-sense input. table 7.13 indicates the pin functions of port 6. table 7.13 port 6 pin functions pin pin functions and selection method p6 7 / irq 7 / keyin 7 p6 7 ddr 0 1 pin function p6 7 input p6 7 output irq 7 input or keyin 7 input irq 7 input is usable when bit irq7e is set to 1 in ier p6 6 /ftob/ bit oeb in tocr of the frt and bit p6 6 ddr select the pin function as follows irq 6 / keyin 6 oeb 0 1 p6 6 ddr 0101 pin function p6 6 input p6 6 output ftob output irq 6 input or keyin 6 input irq 6 input is usable when bit irq6e is set to 1 in ier p6 5 /ftid/ keyin 5 p6 5 ddr 0 1 pin function p6 5 input p6 5 output ftid input or keyin 5 input p6 4 /ftic/ keyin 4 p6 4 ddr 0 1 pin function p6 4 input p6 4 output ftic input or keyin 4 input 142 pin pin functions and selection method p6 3 /ftib/ keyin 3 p6 3 ddr 0 1 pin function p6 3 input p6 3 output ftib input or keyin 3 input p6 2 /ftia/ keyin 2 p6 2 ddr 0 1 pin function p6 2 input p6 2 output ftia input or keyin 2 input p6 1 /ftoa/ bit oea in tocr of the frt and bit p6 1 ddr select the pin function as follows keyin 1 oea 0 1 p6 1 ddr 0101 pin function p6 1 input p6 1 output ftoa output keyin 1 input p6 0 /ftci/ keyin 0 p6 0 ddr 0 1 pin function p6 0 input p6 0 output ftci input or keyin 0 input ftci input is usable when bits cks1 and cks0 in tcr of the frt select an external clock source 143 7.7.4 input pull-up transistors port 6 has built-in programmable input pull-up transistors. the pull-up for each bit can be turned on and off individually. to turn on an input pull-up, set the corresponding kmpcr bit to 1 and clear the corresponding p6ddr bit to 0. kmpcr is cleared to h'00 by a reset and in hardware standby mode, turning all input pull-ups off. in software standby mode, the previous state is maintained. table 7.14 indicates the states of the input pull-up transistors in each operating mode. table 7.14 states of input pull-up transistors (port 6) mode reset hardware standby software standby other operating modes 1 off off on/off on/off 2 off off on/off on/off 3 off off on/off on/off notes: off: the input pull-up transistor is always off. on/off: the input pull-up transistor is on if kmpcr = 1 and p6ddr = 0, but off otherwise. 144 7.8 port 7 7.8.1 overview port 7 is an 8-bit input port that also provides the analog input pins for the a/d converter and analog output pins for the d/a converter. the pin functions are the same in all modes. figure 7.15 shows the pin configuration of port 7. p7 7 (input)/an 7 (input)/da 1 (output) * p7 6 (input)/an 6 (input)/da 0 (output) * p7 5 (input)/an 5 (input) p7 4 (input)/an 4 (input) p7 3 (input)/an 3 (input) p7 2 (input)/an 2 (input) p7 1 (input)/an 1 (input) p7 0 (input)/an 0 (input) port 7 port 7 pins note: * the da 1 and da 0 pin functions apply to the h8/3337 series only. the h8/3397 series does not have an on-chip d/a converter, and therefore has no da 1 and da 0 pin functions. figure 7.15 port 7 pin configuration 7.8.2 register configuration and descriptions table 7.15 summarizes the port 7 registers. port 7 is a dedicated input port, and has no data direction register. table 7.15 port 7 register name abbreviation read/write initial value address port 7 input data register p7pin r undetermined h'ffbe 145 port 7 input data register (p7pin) bit 76543210 p7 7 p7 6 p7 5 p7 4 p7 3 p7 2 p7 1 p7 0 initial value * * * * * * * * read/write r r r r r r r r note: * depends on the levels of pins p77 to p70. when p7pin is read, the pin states are always read. p7pin is a read-only register and cannot be modified. 7.9 port 8 7.9.1 overview port 8 is a 7-bit input/output port that is multiplexed with host interface (hif) input pins (ha 0 , ga 20 , cs ior iow cs irq irq 146 p8 6 /sck 1 / irq 5 /scl * 1 * 2 * 2 p8 5 /rxd 1 / irq 4 / cs 2 p8 4 /txd 1 / irq 3 / iow p8 3 / ior 2 p8 2 /cs 1 * 2 p8 1 /ga 20 * 2 p8 0 /ha 0 * 2 port 8 port 8 port 8 pins p8 6 (input/output)/ irq 5 (input)/sck 1 (input/output) p8 5 (input/output)/ irq 4 (input)/rxd 1 (input) p8 4 (input/output)/ irq 3 (input)/txd 1 (output) p8 3 (input/output) p8 2 (input/output) p8 1 (input/output) p8 0 (input/output) pin configuration in master mode or when stac bit is 1 pin configuration in slave mode when stac bit is 0 p8 6 (input/output)/ irq 5 (input)/sck 1 (input/output)/scl * 1 irq 4 (input)/ cs 2 (input) * 2 irq 3 (input)/ iow (input) * 2 ior (input) * 2 cs 1 (input) * 2 p8 1 (input/output)/ga 20 (output) * 2 ha 0 (input) * 2 notes: * 1 the scl pin function applies to the h8/3337 series only. the h8/3397 series does not support an i 2 c bus interface, and therefore has no scl pin function. * 2 the cs 2 , iow , ior , cs 1 , ga 20 , and ha 0 pin functions apply to the h8/3337 series only. the h8/3397 series does not support a host interface, and theref ore does not have these pin functions. figure 7.16 port 8 pin configuration 7.9.2 register configuration and descriptions table 7.16 summarizes the port 8 registers. table 7.16 port 8 registers name abbreviation read/write initial value address port 8 data direction register p8ddr w h'80 h'ffbd port 8 data register p8dr r/w h'80 h'ffbf 147 port 8 data direction register (p8ddr) bit 76543210 p8 6 ddr p8 5 ddr p8 4 ddr p8 3 ddr p8 2 ddr p8 1 ddr p8 0 ddr initial value 1 0 0 0 0 0 0 0 read/write ww ww ww w p8ddr is an 8-bit readable/writable register that controls the input/output direction of each pin in port 8. a pin functions as an output pin if the corresponding p8ddr bit is set to 1, and as an input pin if this bit is cleared to 0. p8ddr is a write-only register. read data is invalid. if read, all bits always read 1. bit 7 is a reserved bit that always reads 1. p8ddr is initialized to h'80 by a reset and in hardware standby mode. in software standby mode p8ddr retains its existing values, so if a transition to software standby mode occurs while a p8ddr bit is set to 1, the corresponding pin remains in the output state. port 8 data register (p8dr) bit 76543210 p8 6 p8 5 p8 4 p8 3 p8 2 p8 1 p8 0 initial value 1 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w p8dr is an 8-bit register that stores data for pins p8 6 to p8 0 . bit 7 is a reserved bit that always reads 1. when a p8ddr bit is set to 1, if port 8 is read, the value in p8dr is obtained directly, regardless of the actual pin state. when a p8ddr bit is cleared to 0, if port 8 is read the pin state is obtained. this also applies to pins used by on-chip supporting modules. p8dr is initialized to h'80 by a reset and in hardware standby mode. in software standby mode it retains its existing values. 148 7.9.3 pin functions pins p8 6 to p8 0 are multiplexed with hif input/output, sci1 input/output, i 2 c clock input/output, and irq irq table 7.17 port 8 pin functions pin pin functions and selection method p8 6 / irq 5 / sck 1 /scl * bit c/ a in smr of sci1, bits cke0 and cke1 in scr of sci1, bit ice in iccr, and bit p8 6 ddr select the pin function as follows ice 0 1 cke1 0 1 c/ a 01 cke0 0 1 p8 6 ddr 0 1 pin function p8 6 input p8 6 output sck 1 output sck 1 output sck 1 intput scl input/ output * irq 5 input irq 5 input is usable when bit irq5e is set to 1 in ier note: * h8/3337 series only. h8/3397 series ics have no scl pin function. p8 5 / irq 4 / cs 2 * /rxd 1 bit re in scr of sci1, bit stac in stcr, bit p8 5 ddr, and the operating mode select the pin function as follows operating mode slave mode not slave mode stac 0 1 re 01 01 p8 5 ddr 01 01 pin function cs 2 input * p8 5 input p8 5 output rxd 1 input p8 5 input p8 5 output rxd 1 input irq 4 input irq 4 input is usable when bit irq4e is set to 1 in ier note: * h8/3337 series only. h8/3397 series ics have no cs 2 pin function. 149 pin pin functions and selection method p8 4 / irq 3 / iow /txd 1 bit te in scr of sci1, bit stac in stcr, bit p8 4 ddr, and the operating mode select the pin function as follows operating mode slave mode not slave mode stac 0 1 te 01 01 p8 4 ddr 01 01 pin function iow input * p8 4 input p8 4 output txd 1 output p8 4 input p8 4 output txd 1 output irq 3 input irq 3 input is usable when bit irq3e is set to 1 in ier note: * h8/3337 series only. h8/3397 series ics have no iow pin function. p8 3 / ior bit p8 3 ddr and the operating mode select the pin function as follows operating mode slave mode not slave mode p8 3 ddr 01 pin function ior input * p8 3 input p8 3 output note: * h8/3337 series only. h8/3397 series ics have no ior pin function. p8 2 / cs 1 * bit p8 2 ddr and the operating mode select the pin function as follows operating mode slave mode not slave mode p8 2 ddr 01 pin function cs 1 input * p8 2 input p8 2 output note: * h8/3337 series only. h8/3397 series ics have no cs 1 pin function. p8 1 /ga 20 * bit p8 1 ddr and the operating mode select the pin function as follows p8 1 ddr 0 1 fga20e 01 operating mode not slave mode slave mode pin function p8 1 input p8 1 output ga 20 output * note: * h8/3337 series only. h8/3397 series ics have no ga 20 pin function. 150 pin pin functions and selection method p8 0 /ha 0 * bit p8 0 ddr and the operating mode select the pin function as follows operating mode slave mode not slave mode p8 0 ddr 01 pin function ha 0 input * p8 0 input p8 0 output note: * h8/3337 series only. h8/3397 series ics have no ha 0 pin function. 151 7.10 port 9 7.10.1 overview port 9 is an 8-bit input/output port that is multiplexed with interrupt input pins ( irq irq rd wr as wait adtrg ) for the system clock, host interface (hif) input pins ( ecs eiow p9 7 / wait /sda * 1 p9 6 / p9 5 / as p9 4 / wr p9 3 / rd p9 2 / irq 0 port 9 port 9 pins p9 7 (input/output)/ wait (input)/sda (input/output) (output) as (output) wr (output) rd (output) p9 2 (input/output)/ irq 0 (input) pin configuration in mode 1 (expanded mode with on-chip rom disabled) and mode 2 (expanded mode with on-chip rom enabled) p9 7 (input/output)/sda * 1 (input/output) p9 6 (input)/ (output) p9 5 (input/output) p9 4 (input/output) p9 3 (input/output) p9 2 (input/output)/ irq 0 (input) pin configuration in mode 3 (single-chip mode) note: * 1 the sda pin functions applies to the h8/3337 series only. the h8/3397 series does not support a i 2 c bus interface, and therefore has no sda pin functions. figure 7.17 port 9 pin configuration 152 p9 1 / irq 1 / eiow 2 p9 0 / irq 2 / adtrg / ecs 2 * 2 port 9 p9 1 (input/output)/ irq 1 (input) p9 0 (input/output)/ irq 2 (input)/ adtrg (input) pin configuration in master mode, or in slave mode when stac bit is 0 pin configuration in slave mode when stac bit is 1 irq 1 (input)/ eiow 2 (input) irq 2 (input)/ ecs 2 * 2 (input) note: * 2 the eiow and ecs 2 pin functions apply to the h8/3337 series only. the h8/3397 series does not support a host interface, and therefore does not have these pin functions. figure 7.17 port 9 pin configuration (cont) 7.10.2 register configuration and descriptions table 7.18 summarizes the port 9 registers. table 7.18 port 9 registers name abbreviation read/write initial value address port 9 data direction register p9ddr w h'40 (modes 1 and 2) h'00 (mode 3) h'ffc0 port 9 data register p9dr r/w * 1 undetermined * 2 h'ffc1 notes: * 1 bit 6 is read-only. * 2 bit 6 is undetermined. other bits are initially 0. 153 port 9 data direction register (p9ddr) bit 76543210 p9 7 ddr p9 6 ddr p9 5 ddr p9 4 ddr p9 3 ddr p9 2 ddr p9 1 ddr p9 0 ddr modes 1 and 2 initial value 0 1 0 0 0 0 0 0 read/write w wwwwww mode 3 initial value 0 0 0 0 0 0 0 0 read/write w w w w w w w w p9ddr is an 8-bit readable/writable register that controls the input/output direction of each pin in port 9. a pin functions as an output pin if the corresponding p9ddr bit is set to 1, and as an input pin if this bit is cleared to 0. in modes 1 and 2, p9 6 ddr is fixed at 1 and cannot be modified. p9ddr is a write-only register. read data is invalid. if read, all bits always read 1. p9ddr is initialized by a reset and in hardware standby mode. the initial value is h'40 in modes 1 and 2, and h'00 in mode 3. in software standby mode p9ddr retains its existing values, so if a transition to software standby mode occurs while a p9ddr bit is set to 1, the corresponding pin remains in the output state. port 9 data register (p9dr) bit 76543210 p9 7 p9 6 p9 5 p9 4 p9 3 p9 2 p9 1 p9 0 initial value 0 * 000000 read/write r/w r r/w r/w r/w r/w r/w r/w note: * determined by the level at pin p9 6 . p9dr is an 8-bit register that stores data for pins p9 7 to p9 0 . when a p9ddr bit is set to 1, if port 9 is read, the value in p9dr is obtained directly, regardless of the actual pin state, except for p9 6 . when a p9ddr bit is cleared to 0, if port 9 is read the pin state is obtained. this also applies to pins used by on-chip supporting modules and for bus control signals. p9 6 always returns the pin state. except for bit p9 6 , p9dr bits are initialized to 0 by a reset and in hardware standby mode. in software standby mode it retains its existing values. 154 7.10.3 pin functions port 9 has one set of pin functions in modes 1 and 2, and a different set of pin functions in mode 3. the pins are multiplexed with irq irq ) output, host interface input ( ecs eiow table 7.19 port 9 pin functions pin pin functions and selection method p9 7 / wait /sda * bit ice in iccr, bit p9 7 ddr, the wait mode as determined by wscr, and the operating mode select the pin function as follows operating mode modes 1 and 2 mode 3 wait mode wait used wait not used ice 01 01 p9 7 ddr 01 01 pin function wait input pin p9 7 input pin p9 7 output pin sda input/ output pin * p9 7 input pin p9 7 output pin sda input/ output pin * note: * h8/3337 series only. h8/3397 series ics have no sda pin function. p9 6 / bit p9 6 ddr and the operating mode select the pin function as follows operating mode modes 1 and 2 mode 3 p9 6 ddr always 1 0 1 pin function output p9 6 input output p9 5 / as bit p9 5 ddr and the operating mode select the pin function as follows operating mode modes 1 and 2 mode 3 p9 5 ddr 01 pin function as output p9 5 input p9 5 output p9 4 / wr bit p9 4 ddr and the operating mode select the pin function as follows operating mode modes 1 and 2 mode 3 p9 4 ddr 01 pin function wr output p9 4 input p9 4 output 155 pin pin functions and selection method p9 3 / rd bit p9 3 ddr and the operating mode select the pin function as follows operating mode modes 1 and 2 mode 3 p9 3 ddr 01 pin function rd output p9 3 input p9 3 output p9 2 / irq 0 p9 2 ddr 0 1 pin function p9 2 input p9 2 output irq 0 input irq 0 input can be used when bit irq0e is set to 1 in ier p9 1 / irq 1 / eiow bit stac in stcr, bit p9 1 ddr, and the operating mode select the pin function as follows operating mode slave mode not slave mode stac 0 1 p9 1 ddr 0 1 01 pin function p9 1 input p9 1 output eiow input * p9 1 input p9 1 output irq 1 input irq 1 input can be used when bit irq1e is set to 1 in ier note: * h8/3337 series only. h8/3397 series ics have no eiow pin function. p9 0 / irq 2 / adtrg / ecs 2 * bit stac in stcr, bit p9 0 ddr, and the operating mode select the pin function as follows operating mode slave mode not slave mode stac 0 1 p9 0 ddr 0 1 01 pin function p9 0 input p9 0 output ecs 2 input * p9 0 input p9 0 output irq 2 input and adtrg input irq 2 input irq 2 input and adtrg input irq 2 input can be used when bit irq2e is set to 1 in ier adtrg input can be used when bit trge is set to 1 in adcr note: * h8/3337 series only. h8/3397 series ics have no ecs 2 pin function. 156 157 section 8 16-bit free-running timer 8.1 overview the h8/3337 series and h8/3397 series have an on-chip 16-bit free-running timer (frt) module that uses a 16-bit free-running counter as a time base. applications of the frt module include rectangular-wave output (up to two independent waveforms), input pulse width measurement, and measurement of external clock periods. 8.1.1 features the features of the free-running timer module are listed below. ? selection of four clock sources the free-running counter can be driven by an internal clock source ( p /2, p /8, or p /32), or an external clock input (enabling use as an external event counter). ? two independent comparators each comparator can generate an independent waveform. ? four input capture channels the current count can be captured on the rising or falling edge (selectable) of an input signal. the four input capture registers can be used separately, or in a buffer mode. ? counter can be cleared under program control the free-running counters can be cleared on compare-match a. ? seven independent interrupts compare-match a and b, input capture a to d, and overflow interrupts are requested independently. 158 8.1.2 block diagram figure 8.1 shows a block diagram of the free-running timer. external clock source internal clock sources clock select comparator a ocra (h/l) comparator b ocrb (h/l) bus interface internal data bus p /2 p /8 p /32 ftci compare- match a clear clock ftoa ftob overflow icra (h/l) compare- match b capture frc (h/l) tcsr ftia ftib ftic ftid control logic module data bus tier tcr tocr interrupt signals icia icib icic icid ocia ocib fovi legend: ocra, b: frc: icra, b, c, d: tcsr: output compare register a, b (16 bits) free-running counter (16 bits) input capture register a, b, c, d (16 bits) timer control/status register (8 bits) tier: tcr: tocr: timer interrupt enable register (8 bits) timer control register (8 bits) timer output compare control register (8 bits) icrb (h/l) icrc (h/l) icrd (h/l) figure 8.1 block diagram of 16-bit free-running timer 159 8.1.3 input and output pins table 8.1 lists the input and output pins of the free-running timer module. table 8.1 input and output pins of free-running timer module name abbreviation i/o function counter clock input ftci input input of external free-running counter clock signal output compare a ftoa output output controlled by comparator a output compare b ftob output output controlled by comparator b input capture a ftia input trigger for capturing current count into input capture register a input capture b ftib input trigger for capturing current count into input capture register b input capture c ftic input trigger for capturing current count into input capture register c input capture d ftid input trigger for capturing current count into input capture register d 160 8.1.4 register configuration table 8.2 lists the registers of the free-running timer module. table 8.2 register configuration name abbreviation r/w initial value address timer interrupt enable register tier r/w h'01 h'ff90 timer control/status register tcsr r/(w) * 1 h'00 h'ff91 free-running counter (high) frc (h) r/w h'00 h'ff92 free-running counter (low) frc (l) r/w h'00 h'ff93 output compare register a/b (high) * 2 ocra/b (h) r/w h'ff h'ff94 * 2 output compare register a/b (low) * 2 ocra/b (l) r/w h'ff h'ff95 * 2 timer control register tcr r/w h'00 h'ff96 timer output compare control register tocr r/w h'e0 h'ff97 input capture register a (high) icra (h) r h'00 h'ff98 input capture register a (low) icra (l) r h'00 h'ff99 input capture register b (high) icrb (h) r h'00 h'ff9a input capture register b (low) icrb (l) r h'00 h'ff9b input capture register c (high) icrc (h) r h'00 h'ff9c input capture register c (low) icrc (l) r h'00 h'ff9d input capture register d (high) icrd (h) r h'00 h'ff9e input capture register d (low) icrd (l) r h'00 h'ff9f notes: * 1 software can write a 0 to clear bits 7 to 1, but cannot write a 1 in these bits. bit 0 can be read and written to. * 2 ocra and ocrb share the same addresses. access is controlled by the ocrs bit in tocr. 161 8.2 register descriptions 8.2.1 free-running counter (frc) bit 1514131211109876543210 initial value 0 0 0 0000000000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w frc is a 16-bit readable/writable up-counter that increments on an internal pulse generated from a clock source. the clock source is selected by the clock select 1 and 0 bits (cks1 and cks0) of the timer control register (tcr). when frc overflows from h'ffff to h'0000, the overflow flag (ovf) in the timer control/status register (tcsr) is set to 1. because frc is a 16-bit register, a temporary register (temp) is used when frc is written or read. see section 8.3, cpu interface, for details. frc is initialized to h'0000 by a reset and in the standby modes. 8.2.2 output compare registers a and b (ocra and ocrb) bit 1514131211109876543210 initial value 1 1 1 1111111111111 read/write r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w ocra and ocrb are 16-bit readable/writable registers, the contents of which are continually compared with the value in the frc. when a match is detected, the corresponding output compare flag (ocfa or ocfb) is set in the timer control/status register (tcsr). in addition, if the output enable bit (oea or oeb) in the timer output compare control register (tocr) is set to 1, when the output compare register and frc values match, the logic level selected by the output level bit (olvla or olvlb) in tocr is output at the output compare pin (ftoa or ftob). following a reset, the ftoa and ftob output levels are 0 until the first compare-match. ocra and ocrb share the same address. they are differentiated by the ocrs bit in tocr. a temporary register (temp) is used for write access, as explained in section 8.3, cpu interface. ocra and ocrb are initialized to h'ffff by a reset and in the standby modes. 162 8.2.3 input capture registers a to d (icra to icrd) bit 1514131211109876543210 initial value 0 0 0 0000000000000 read/write r r r rrrrrrrrrrrrr there are four input capture registers a to d, each of which is a 16-bit read-only register. when the rising or falling edge of the signal at an input capture pin (ftia to ftid) is detected, the current frc value is copied to the corresponding input capture register (icra to icrd).* at the same time, the corresponding input capture flag (icfa to icfd) in the timer control/status register (tcsr) is set to 1. the input capture edge is selected by the input edge select bits (iedga to iedgd) in the timer control register (tcr). note: * the frc contents are transferred to the input capture register regardless of the value of the input capture flag (icfa/b/c/d). input capture can be buffered by using the input capture registers in pairs. when the bufea bit in tcr is set to 1, icrc is used as a buffer register for icra as shown in figure 8.2. when an ftia input is received, the old icra contents are moved into icrc, and the new frc count is copied into icra. bufea: iedga: iedgc: icrc: icra: frc: buffer enable a input edge select a input edge select c input capture register c input capture register a free-running counter bufea iedga iedgc ftia edge detect and capture signal generating circuit frc icrc icra figure 8.2 input capture buffering (example) 163 similarly, when the bufeb bit in tcr is set to 1, icrd is used as a buffer register for icrb. when input capture is buffered, if the two input edge bits are set to different values (iedga iedgc or iedgb iedgd), then input capture is triggered on both the rising and falling edges of the ftia or ftib input signal. if the two input edge bits are set to the same value (iedga = iedgc or iedgb = iedgd), then input capture is triggered on only one edge. see table 8.3. table 8.3 buffered input capture edge selection (example) iedga iedgc input capture edge 0 0 captured on falling edge of input capture a (ftia) (initial value) 1 captured on both rising and falling edges of input capture a (ftia) 10 1 captured on rising edge of input capture a (ftia) because the input capture registers are 16-bit registers, a temporary register (temp) is used when they are read. see section 8.3, cpu interface, for details. to ensure input capture, the width of the input capture pulse should be at least 1.5 system clock (? periods. when triggering is enabled on both edges, the input capture pulse width should be at least 2.5 system clock periods. the input capture registers are initialized to h'0000 by a reset and in the standby modes. 164 8.2.4 timer interrupt enable register (tier) bit 76543210 iciae icibe icice icide ociae ocibe ovie initial value 0 0 0 0 0 0 0 1 read/write r/w r/w r/w r/w r/w r/w r/w tier is an 8-bit readable/writable register that enables and disables interrupts. tier is initialized to h'01 by a reset and in the standby modes. bit 7?nput capture interrupt a enable (iciae): this bit selects whether to request input capture interrupt a (icia) when input capture flag a (icfa) in the timer status/control register (tcsr) is set to 1. bit 7: iciae description 0 input capture interrupt request a (icia) is disabled. (initial value) 1 input capture interrupt request a (icia) is enabled. bit 6?nput capture interrupt b enable (icibe): this bit selects whether to request input capture interrupt b (icib) when input capture flag b (icfb) in tcsr is set to 1. bit 6: icibe description 0 input capture interrupt request b (icib) is disabled. (initial value) 1 input capture interrupt request b (icib) is enabled. bit 5?nput capture interrupt c enable (icice): this bit selects whether to request input capture interrupt c (icic) when input capture flag c (icfc) in tcsr is set to 1. bit 5: icice description 0 input capture interrupt request c (icic) is disabled. (initial value) 1 input capture interrupt request c (icic) is enabled. bit 4?nput capture interrupt d enable (icide): this bit selects whether to request input capture interrupt d (icid) when input capture flag d (icfd) in tcsr is set to 1. bit 4: icide description 0 input capture interrupt request d (icid) is disabled. (initial value) 1 input capture interrupt request d (icid) is enabled. 165 bit 3?utput compare interrupt a enable (ociae): this bit selects whether to request output compare interrupt a (ocia) when output compare flag a (ocfa) in tcsr is set to 1. bit 3: ociae description 0 output compare interrupt request a (ocia) is disabled. (initial value) 1 output compare interrupt request a (ocia) is enabled. bit 2?utput compare interrupt b enable (ocibe): this bit selects whether to request output compare interrupt b (ocib) when output compare flag b (ocfb) in tcsr is set to 1. bit 2: ocibe description 0 output compare interrupt request b (ocib) is disabled. (initial value) 1 output compare interrupt request b (ocib) is enabled. bit 1?imer overflow interrupt enable (ovie): this bit selects whether to request a free- running timer overflow interrupt (fovi) when the timer overflow flag (ovf) in tcsr is set to 1. bit 1: ovie description 0 timer overflow interrupt request (fovi) is disabled. (initial value) 1 timer overflow interrupt request (fovi) is enabled. bit 0?eserved: this bit cannot be modified and is always read as 1. 166 8.2.5 timer control/status register (tcsr) bit 76543210 icfa icfb icfc icfd ocfa ocfb ovf cclra initial value 0 0 0 0 0 0 0 0 read/write r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/w note: * software can write a 0 in bits 7 to 1 to clear the flags, but cannot write a 1 in these bits. tcsr is an 8-bit readable and partially writable register that contains the seven interrupt flags and specifies whether to clear the counter on compare-match a (when the frc and ocra values match). tcsr is initialized to h'00 by a reset and in the standby modes. timing is described in section 8.4, operation. bit 7?nput capture flag a (icfa): this status bit is set to 1 to flag an input capture a event. if bufea = 0, icfa indicates that the frc value has been copied to icra. if bufea = 1, icfa indicates that the old icra value has been moved into icrc and the new frc value has been copied to icra. icfa must be cleared by software. it is set by hardware, however, and cannot be set by software. bit 7: icfa description 0 to clear icfa, the cpu must read icfa after it has been set to 1, then write a 0 in this bit. (initial value) 1 this bit is set to 1 when an ftia input signal causes the frc value to be copied to icra. bit 6?nput capture flag b (icfb): this status bit is set to 1 to flag an input capture b event. if bufeb = 0, icfb indicates that the frc value has been copied to icrb. if bufeb = 1, icfb indicates that the old icrb value has been moved into icrd and the new frc value has been copied to icrb. icfb must be cleared by software. it is set by hardware, however, and cannot be set by software. bit 6: icfb description 0 to clear icfb, the cpu must read icfb after it has been set to 1, then write a 0 in this bit. (initial value) 1 this bit is set to 1 when an ftib input signal causes the frc value to be copied to icrb. 167 bit 5?nput capture flag c (icfc): this status bit is set to 1 to flag input of a rising or falling edge of ftic as selected by the iedgc bit. when bufea = 0, this indicates capture of the frc count in icrc. when bufea = 1, however, the frc count is not captured, so icfc becomes simply an external interrupt flag. in other words, the buffer mode frees ftic for use as a general- purpose interrupt signal (which can be enabled or disabled by the icice bit). icfc must be cleared by software. it is set by hardware, however, and cannot be set by software. bit 5: icfc description 0 to clear icfc, the cpu must read icfc after it has been set to 1, then write a 0 in this bit. (initial value) 1 this bit is set to 1 when an ftic input signal is received. bit 4?nput capture flag d (icfd): this status bit is set to 1 to flag input of a rising or falling edge of ftid as selected by the iedgd bit. when bufeb = 0, this indicates capture of the frc count in icrd. when bufeb = 1, however, the frc count is not captured, so icfd becomes simply an external interrupt flag. in other words, the buffer mode frees ftid for use as a general- purpose interrupt signal (which can be enabled or disabled by the icide bit). icfd must be cleared by software. it is set by hardware, however, and cannot be set by software. bit 4: icfd description 0 to clear icfd, the cpu must read icfd after it has been set to 1, then write a 0 in this bit. (initial value) 1 this bit is set to 1 when an ftid input signal is received. bit 3?utput compare flag a (ocfa): this status flag is set to 1 when the frc value matches the ocra value. this flag must be cleared by software. it is set by hardware, however, and cannot be set by software. bit 3: ocfa description 0 to clear ocfa, the cpu must read ocfa after it has been set to 1, then write a 0 in this bit. (initial value) 1 this bit is set to 1 when frc = ocra. 168 bit 2?utput compare flag b (ocfb): this status flag is set to 1 when the frc value matches the ocrb value. this flag must be cleared by software. it is set by hardware, however, and cannot be set by software. bit 2: ocfb description 0 to clear ocfb, the cpu must read ocfb after it has been set to 1, then write a 0 in this bit. (initial value) 1 this bit is set to 1 when frc = ocrb. bit 1?imer overflow flag (ovf): this status flag is set to 1 when frc overflows (changes from h'ffff to h'0000). this flag must be cleared by software. it is set by hardware, however, and cannot be set by software. bit 1: ovf description 0 to clear ovf, the cpu must read ovf after it has been set to 1, then write a 0 in this bit. (initial value) 1 this bit is set to 1 when frc changes from h'ffff to h'0000. bit 0?ounter clear a (cclra): this bit selects whether to clear frc at compare-match a (when the frc and ocra values match). bit 0: cclra description 0 the frc is not cleared. (initial value) 1 the frc is cleared at compare-match a. 8.2.6 timer control register (tcr) bit 76543210 iedga iedgb iedgc iedgd bufea bufeb cks1 cks0 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w tcr is an 8-bit readable/writable register that selects the rising or falling edge of the input capture signals, enables the input capture buffer mode, and selects the frc clock source. tcr is initialized to h'00 by a reset and in the standby modes. 169 bit 7?nput edge select a (iedga): this bit selects the rising or falling edge of the input capture a signal (ftia). bit 7: iedga description 0 input capture a events are recognized on the falling edge of ftia. (initial value) 1 input capture a events are recognized on the rising edge of ftia. bit 6?nput edge select b (iedgb): this bit selects the rising or falling edge of the input capture b signal (ftib). bit 6: iedgb description 0 input capture b events are recognized on the falling edge of ftib. (initial value) 1 input capture b events are recognized on the rising edge of ftib. bit 5?nput edge select c (iedgc): this bit selects the rising or falling edge of the input capture c signal (ftic). bit 5: iedgc description 0 input capture c events are recognized on the falling edge of ftic. (initial value) 1 input capture c events are recognized on the rising edge of ftic. bit 4?nput edge select d (iedgd): this bit selects the rising or falling edge of the input capture d signal (ftid). bit 4: iedgd description 0 input capture d events are recognized on the falling edge of ftid. (initial value) 1 input capture d events are recognized on the rising edge of ftid. bit 3?uffer enable a (bufea): this bit selects whether to use icrc as a buffer register for icra. bit 3: bufea description 0 icrc is used for input capture c. (initial value) 1 icrc is used as a buffer register for input capture a. 170 bit 2?uffer enable b (bufeb): this bit selects whether to use icrd as a buffer register for icrb. bit 2: bufeb description 0 icrd is used for input capture d. (initial value) 1 icrd is used as a buffer register for input capture b. bits 1 and 0?lock select (cks1 and cks0): these bits select external clock input or one of three internal clock sources for frc. external clock pulses are counted on the rising edge of signals input to pin ftci. bit 1: cks1 bit 0: cks0 description 00 p /2 internal clock source (initial value) 1 p /8 internal clock source 10 p /32 internal clock source 1 external clock source (rising edge) 8.2.7 timer output compare control register (tocr) bit 76543210 ocrs oea oeb olvla olvlb initial value 1 1 1 0 0 0 0 0 read/write r/w r/w r/w r/w r/w tocr is an 8-bit readable/writable register that enables output from the output compare pins, selects the output levels, and switches access between output compare registers a and b. tocr is initialized to h'e0 by a reset and in the standby modes. bits 7 to 5?eserved: these bits cannot be modified and are always read as 1. bit 4?utput compare register select (ocrs): ocra and ocrb share the same address. when this address is accessed, the ocrs bit selects which register is accessed. this bit does not affect the operation of ocra or ocrb. bit 4: ocrs description 0 ocra is selected. (initial value) 1 ocrb is selected. 171 bit 3?utput enable a (oea): this bit enables or disables output of the output compare a signal (ftoa). bit 3: oea description 0 output compare a output is disabled. (initial value) 1 output compare a output is enabled. bit 2?utput enable b (oeb): this bit enables or disables output of the output compare b signal (ftob). bit 2: oeb description 0 output compare b output is disabled. (initial value) 1 output compare b output is enabled. bit 1?utput level a (olvla): this bit selects the logic level to be output at the ftoa pin when the frc and ocra values match. bit 1: olvla description 0 a 0 logic level is output for compare-match a. (initial value) 1 a 1 logic level is output for compare-match a. bit 0?utput level b (olvlb): this bit selects the logic level to be output at the ftob pin when the frc and ocrb values match. bit 0: olvlb description 0 a 0 logic level is output for compare-match b. (initial value) 1 a 1 logic level is output for compare-match b. 172 8.3 cpu interface the free-running counter (frc), output compare registers (ocra and ocrb), and input capture registers (icra to icrd) are 16-bit registers, but they are connected to an 8-bit data bus. when the cpu accesses these registers, to ensure that both bytes are written or read simultaneously, the access is performed using an 8-bit temporary register (temp). these registers are written and read as follows: ? register write when the cpu writes to the upper byte, the byte of write data is placed in temp. next, when the cpu writes to the lower byte, this byte of data is combined with the byte in temp and all 16 bits are written in the register simultaneously. ? register read when the cpu reads the upper byte, the upper byte of data is sent to the cpu and the lower byte is placed in temp. when the cpu reads the lower byte, it receives the value in temp. programs that access these registers should normally use word access. equivalently, they may access first the upper byte, then the lower byte by two consecutive byte accesses. data will not be transferred correctly if the bytes are accessed in reverse order, or if only one byte is accessed. figure 8.3 shows the data flow when frc is accessed. the other registers are accessed in the same way. as an exception, when the cpu reads ocra or ocrb, it reads both the upper and lower bytes directly, without using temp. coding examples to write the contents of general register r0 to ocra: mov.w r0, @ocra to transfer the contents of icra to general register r0: mov.w @icra, r0 173 cpu writes data h'aa (1) upper byte write (2) lower byte write cpu writes data h'55 bus interface bus interface module data bus module data bus temp [h'aa] frch [ ] frcl [ ] temp [h'aa] frch [h'aa] frcl [h'55] figure 8.3 (a) write access to frc (when cpu writes h'aa55) 174 cpu reads data h'aa (1) upper byte read (2) lower byte read cpu reads data h'55 bus interface bus interface module data bus module data bus temp [h'55] frch [h'aa] frcl [h'55] temp [h'55] frch [ ] frcl [ ] figure 8.3 (b) read access to frc (when frc contains h'aa55) 175 8.4 operation 8.4.1 frc increment timing frc increments on a pulse generated once for each period of the selected (internal or external) clock source. the clock source is selected by bits cks0 and cks1 in tcr. internal clock: the internal clock sources ( p /2, p /8, p /32) are created from the system clock (? by a prescaler. frc increments on a pulse generated from the falling edge of the prescaler output. see figure 8.4. n 1 frc clock pulse frc internal clock n n + 1 figure 8.4 increment timing for internal clock source 176 external clock: if external clock input is selected, frc increments on the rising edge of the ftci clock signal. figure 8.5 shows the increment timing. the pulse width of the external clock signal must be at least 1.5 system clock (? periods. the counter will not increment correctly if the pulse width is shorter than 1.5 system clock periods. n + 1 n frc clock pulse frc ftci figure 8.5 increment timing for external clock source 177 8.4.2 output compare timing when a compare-match occurs, the logic level selected by the output level bit (olvla or olvlb) in tocr is output at the output compare pin (ftoa or ftob). figure 8.6 shows the timing of this operation for compare-match a. n + 1 n n + 1 n n ocra internal compare- match a signal frc olvla ftoa clear * note: * cleared b y software n figure 8.6 timing of output compare a 178 8.4.3 frc clear timing if the cclra bit in tcsr is set to 1, the frc is cleared when compare-match a occurs. figure 8.7 shows the timing of this operation. n h'0000 frc internal compare- match a signal figure 8.7 clearing of frc by compare-match a 8.4.4 input capture timing input capture timing: an internal input capture signal is generated from the rising or falling edge of the signal at the input capture pin ftix (x = a, b, c, d), as selected by the corresponding iedgx bit in tcr. figure 8.8 shows the usual input capture timing when the rising edge is selected (iedgx = 1). internal input capture signal input data fti pin figure 8.8 input capture timing (usual case) if the upper byte of icra/b/c/d is being read when the corresponding input capture signal arrives, the internal input capture signal is delayed by one state. figure 8.9 shows the timing for this case. 179 internal input capture signal input at fti pin t 1 t 2 t 3 icr upper byte read cycle figure 8.9 input capture timing (1-state delay due to icra/b/c/d read) buffered input capture timing: icrc and icrd can operate as buffers for icra and icrb. figure 8.10 shows how input capture operates when icra and icrc are used in buffer mode and iedga and iedgc are set to different values (iedga = 0 and iedgc = 1, or iedg a = 1 and iedgc = 0), so that input capture is performed on both the rising and falling edges of ftia. n n + 1 n n + 1 m n n n mm mn ftia internal input capture signal frc icra icrc figure 8.10 buffered input capture with both edges selected 180 when icrc or icrd is used as a buffer register, its input capture flag is set by the selected transition of its input capture signal. for example, if icrc is used to buffer icra, when the edge transition selected by the iedgc bit occurs on the ftic input capture line, icfc will be set, and if the iciec bit is set, an interrupt will be requested. the frc value will not be transferred to icrc, however. in buffered input capture, if the upper byte of either of the two registers to which data will be transferred (icra and icrc, or icrb and icrd) is being read when the input signal arrives, input capture is delayed by one system clock ( ). figure 8.11 shows the timing when bufea = 1. internal input capture si g nal input at ftia pin t 1 t 2 t 3 read cycle: cpu reads upper byte of icra or icrc figure 8.11 input capture timing (1-state delay, buffer mode) 181 8.4.5 timing of input capture flag (icf) setting the input capture flag icfx (x = a, b, c, d) is set to 1 by the internal input capture signal. figure 8.12 shows the timing of this operation. icf frc internal input capture signal n n icr figure 8.12 setting of input capture flag 8.4.6 setting of output compare flags a and b (ocfa and ocfb) the output compare flags are set to 1 by an internal compare-match signal generated when the frc value matches the ocra or ocrb value. this compare-match signal is generated at the last state in which the two values match, just before frc increments to a new value. accordingly, when the frc and ocr values match, the compare-match signal is not generated until the next period of the clock source. figure 8.13 shows the timing of the setting of the output compare flags. 182 ocra or ocrb internal compare- match signal frc n n + 1 n ocfa or ocfb figure 8.13 setting of output compare flags 8.4.7 setting of timer overflow flag (ovf) the timer overflow flag (ovf) is set to 1 when frc overflows (changes from h'ffff to h'0000). figure 8.14 shows the timing of this operation. h'ffff h'0000 internal overflow signal frc ovf figure 8.14 setting of timer overflow flag (ovf) 183 8.5 interrupts the free-running timer can request seven interrupts (three types): input capture a to d (icia, icib, icic, icid), output compare a and b (ocia and ocib), and overflow (fovi). each interrupt can be enabled or disabled by an enable bit in tier. independent signals are sent to the interrupt controller for each interrupt. table 8.4 lists information about these interrupts. table 8.4 free-running timer interrupts interrupt description priority icia requested by icfa high icib requested by icfb icic requested by icfc icid requested by icfd ocia requested by ocfa ocib requested by ocfb fovi requested by ovf low 184 8.6 sample application in the example below, the free-running timer is used to generate two square-wave outputs with a 50% duty cycle and arbitrary phase relationship. the programming is as follows: 1. the cclra bit in tcsr is set to 1. 2. each time a compare-match interrupt occurs, software inverts the corresponding output level bit in tocr (olvla or olvlb). t 1 t 2 t 3 write cycle: cpu write to lower byte of frc internal address bus frc address internal write signal frc clear signal frc n h'0000 figure 8.15 square-wave output (example) 185 8.7 application notes application programmers should note that the following types of contention can occur in the free- running timer. contention between frc write and clear: if an internal counter clear signal is generated during the t 3 state of a write cycle to the lower byte of the free-running counter, the clear signal takes priority and the write is not performed. figure 8.16 shows this type of contention. t 1 t 2 t 3 write cycle: cpu write to lower byte of frc internal address bus frc address internal write signal frc clear signal frc n h'0000 figure 8.16 frc write-clear contention 186 contention between frc write and increment: if an frc increment pulse is generated during the t 3 state of a write cycle to the lower byte of the free-running counter, the write takes priority and frc is not incremented. figure 8.17 shows this type of contention. t 1 t 2 t 3 write cycle: cpu write to lower byte of frc internal address bus internal write signal frc clock pulse frc n m write data frc address figure 8.17 frc write-increment contention 187 contention between ocr write and compare-match: if a compare-match occurs during the t 3 state of a write cycle to the lower byte of ocra or ocrb, the write takes priority and the compare-match signal is inhibited. figure 8.18 shows this type of contention. t 1 t 2 t 3 write cycle: cpu write to lower byte of ocra or ocrb internal address bus internal write signal frc ocra or ocrb n m write data ocr address n n + 1 compare-match a or b signal inhibited figure 8.18 contention between ocr write and compare-match 188 increment caused by changing of internal clock source: when an internal clock source is changed, the changeover may cause frc to increment. this depends on the time at which the clock select bits (cks1 and cks0) are rewritten, as shown in table 8.5. the pulse that increments frc is generated at the falling edge of the internal clock source. if clock sources are changed when the old source is high and the new source is low, as in case no. 3 in table 8.5, the changeover generates a falling edge that triggers the frc increment clock pulse. switching between an internal and external clock source can also cause frc to increment. table 8.5 effect of changing internal clock sources no. description timing 1 low low: cks1 and cks0 are rewritten while both clock sources are low. n + 1 old clock source new clock source frc clock pulse frc cks rewrite n 2 low high: cks1 and cks0 are rewritten while old clock source is low and new clock source is high. n + 1 n + 2 old clock source new clock source frc clock pulse frc cks rewrite n 189 no. description timing 3 high low: cks1 and cks0 are rewritten while old clock source is high and new clock source is low. n + 1 n n + 2 * old clock source new clock source frc clock pulse frc cks rewrite 4 high high: cks1 and cks0 are rewritten while both clock sources are high. n + 1 n + 2 n old clock source new clock source frc clock pulse cks rewrite frc note: * the switching of clock sources is regarded as a falling edge that increments frc. 190 191 section 9 8-bit timers 9.1 overview the h8/3337 series and h8/3397 series include an 8-bit timer module with two channels (numbered 0 and 1). each channel has an 8-bit counter (tcnt) and two time constant registers (tcora and tcorb) that are constantly compared with the tcnt value to detect compare- match events. one of the many applications of the 8-bit timer module is to generate a rectangular- wave output with an arbitrary duty cycle. 9.1.1 features the features of the 8-bit timer module are listed below. ? selection of seven clock sources the counters can be driven by one of six internal clock signals or an external clock input (enabling use as an external event counter). ? selection of three ways to clear the counters the counters can be cleared on compare-match a or b, or by an external reset signal. ? timer output controlled by two compare-match signals the timer output signal in each channel is controlled by two independent compare-match signals, enabling the timer to generate output waveforms with an arbitrary duty cycle, or pwm waveforms. ? three independent interrupts compare-match a and b and overflow interrupts can be requested independently. 192 9.1.2 block diagram figure 9.1 shows a block diagram of one channel in the 8-bit timer module. external clock source tmci tmo tmri internal clock sources channel 0 channel 1 p /2 p /8 p /32 p /64 p /256 p /1024 p /2 p /8 p /64 p /128 p /1024 p /2048 clock overflow clear compare-match b control logic clock select tcora comparator a tcnt comparator b tcorb tcsr tcr module data bus bus interface internal data bus cmia cmib ovi interrupt signals tcora: tcorb: tcnt: tcsr: tcr: time constant register a (8 bits) time constant register b (8 bits) timer counter timer control status register (8 bits) timer control register (8 bits) compare-match a figure 9.1 block diagram of 8-bit timer (1 channel) 193 9.1.3 input and output pins table 9.1 lists the input and output pins of the 8-bit timer. table 9.1 input and output pins of 8-bit timer abbreviation * name channel 0 channel 1 i/o function timer output tmo 0 tmo 1 output output controlled by compare-match timer clock input tmci 0 tmci 1 input external clock source for the counter timer reset input tmri 0 tmri 1 input external reset signal for the counter note: * in this manual, the channel subscript has been deleted, and only tmo, tmci, and tmri are used. 9.1.4 register configuration table 9.2 lists the registers of the 8-bit timer module. table 9.2 8-bit timer registers channel name abbreviation r/w initial value address 0 timer control register tcr r/w h'00 h'ffc8 timer control/status register tcsr r/(w) * h'10 h'ffc9 time constant register a tcora r/w h'ff h'ffca time constant register b tcorb r/w h'ff h'ffcb timer counter tcnt r/w h'00 h'ffcc 1 timer control register tcr r/w h'00 h'ffd0 timer control/status register tcsr r/(w) * h'10 h'ffd1 time constant register a tcora r/w h'ff h'ffd2 time constant register b tcorb r/w h'ff h'ffd3 timer counter tcnt r/w h'00 h'ffd4 0, 1 serial/timer control register stcr r/w h'00 h'ffc3 note: * software can write a 0 to clear bits 7 to 5, but cannot write a 1 in these bits. 194 9.2 register descriptions 9.2.1 timer counter (tcnt) bit 76543210 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w each timer counter (tcnt) is an 8-bit up-counter that increments on a pulse generated from an internal or external clock source selected by clock select bits 2 to 0 (cks2 to cks0) of the timer control register (tcr). the cpu can always read or write the timer counter. the timer counter can be cleared by an external reset input or by an internal compare-match signal generated at a compare-match event. clock clear bits 1 and 0 (cclr1 and cclr0) of the timer control register select the method of clearing. when a timer counter overflows from h'ff to h'00, the overflow flag (ovf) in the timer control/status register (tcsr) is set to 1. the timer counters are initialized to h'00 by a reset and in the standby modes. 9.2.2 time constant registers a and b (tcora and tcorb) bit 76543210 initial value 1 1 1 1 1 1 1 1 read/write r/w r/w r/w r/w r/w r/w r/w r/w tcora and tcorb are 8-bit readable/writable registers. the timer count is continually compared with the constants written in these registers (except during the t 3 state of a write cycle to tcora or tcorb). when a match is detected, the corresponding compare-match flag (cmfa or cmfb) is set in the timer control/status register (tcsr). the timer output signal is controlled by these compare-match signals as specified by output select bits 3 to 0 (os3 to os0) in the timer control/status register (tcsr). tcora and tcorb are initialized to h'ff by a reset and in the standby modes. 195 9.2.3 timer control register (tcr) bit 76543210 cmieb cmiea ovie cclr1 cclr0 cks2 cks1 cks0 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w tcr is an 8-bit readable/writable register that selects the clock source and the time at which the timer counter is cleared, and enables interrupts. tcr is initialized to h'00 by a reset and in the standby modes. for timing diagrams, see section 9.3, operation. bit 7?ompare-match interrupt enable b (cmieb): this bit selects whether to request compare-match interrupt b (cmib) when compare-match flag b (cmfb) in the timer control/status register (tcsr) is set to 1. bit 7: cmieb description 0 compare-match interrupt request b (cmib) is disabled. (initial value) 1 compare-match interrupt request b (cmib) is enabled. bit 6?ompare-match interrupt enable a (cmiea): this bit selects whether to request compare-match interrupt a (cmia) when compare-match flag a (cmfa) in tcsr is set to 1. bit 6: cmiea description 0 compare-match interrupt request a (cmia) is disabled. (initial value) 1 compare-match interrupt request a (cmia) is enabled. 196 bit 5?imer overflow interrupt enable (ovie): this bit selects whether to request a timer overflow interrupt (ovi) when the overflow flag (ovf) in tcsr is set to 1. bit 5: ovie description 0 the timer overflow interrupt request (ovi) is disabled. (initial value) 1 the timer overflow interrupt request (ovi) is enabled. bits 4 and 3?ounter clear 1 and 0 (cclr1 and cclr0): these bits select how the timer counter is cleared: by compare-match a or b or by an external reset input (tmri). bit 4: cclr1 bit 3: cclr0 description 0 0 not cleared. (initial value) 1 cleared on compare-match a. 1 0 cleared on compare-match b. 1 cleared on rising edge of external reset input signal. 197 bits 2, 1, and 0?lock select (cks2, cks1, and cks0): these bits and bits icks1 and icks0 in the serial/timer control register (stcr) select the internal or external clock source for the timer counter. six internal clock sources, derived by prescaling the system clock, are available for each timer channel. for internal clock sources the counter is incremented on the falling edge of the internal clock. for an external clock source, these bits can select whether to increment the counter on the rising or falling edge of the clock input (tmci), or on both edges. tcr stcr channel bit 2: cks2 bit 1: cks1 bit 0: cks0 bit 1: icks1 bit 0: icks0 description 0 0 0 0 no clock source (timer stopped) (initial value) 10 p /8 internal clock, counted on falling edge 1 p /2 internal clock, counted on falling edge 10 0 p /64 internal clock, counted on falling edge 1 p /32 internal clock, counted on falling edge 10 p /1024 internal clock, counted on falling edge 1 p /256 internal clock, counted on falling edge 1 0 0 no clock source (timer stopped) 1 external clock source, counted on rising edge 1 0 external clock source, counted on falling edge 1 external clock source, counted on both rising and falling edges 1 0 0 0 no clock source (timer stopped) (initial value) 10 p /8 internal clock, counted on falling edge 1 p /2 internal clock, counted on falling edge 10 0 p /64 internal clock, counted on falling edge 1 p /128 internal clock, counted on falling edge 10 p /1024 internal clock, counted on falling edge 1 p /2048 internal clock, counted on falling edge 1 0 0 no clock source (timer stopped) 1 external clock source, counted on rising edge 1 0 external clock source, counted on falling edge 1 external clock source, counted on both rising and falling edges 198 9.2.4 timer control/status register (tcsr) bit 76543210 cmfb cmfa ovf os3 os2 os1 os0 initial value 0 0 0 1 0 0 0 0 read/write r/(w) * r/(w) * r/(w) * r/w r/w r/w r/w note: * software can write a 0 in bits 7 to 5 to clear the flags, but cannot write a 1 in these bits. tcsr is an 8-bit readable and partially writable register that indicates compare-match and overflow status and selects the effect of compare-match events on the timer output signal. tcsr is initialized to h'10 by a reset and in the standby modes. bit 7?ompare-match flag b (cmfb): this status flag is set to 1 when the timer count matches the time constant set in tcorb. cmfb must be cleared by software. it is set by hardware, however, and cannot be set by software. bit 7: cmfb description 0 to clear cmfb, the cpu must read cmfb after it has been set to 1, then write a 0 in this bit. (initial value) 1 this bit is set to 1 when tcnt = tcorb. bit 6?ompare-match flag a (cmfa): this status flag is set to 1 when the timer count matches the time constant set in tcora. cmfa must be cleared by software. it is set by hardware, however, and cannot be set by software. bit 6: cmfa description 0 to clear cmfa, the cpu must read cmfa after it has been set to 1, then write a 0 in this bit. (initial value) 1 this bit is set to 1 when tcnt = tcora. bit 5?imer overflow flag (ovf): this status flag is set to 1 when the timer count overflows (changes from h'ff to h'00). ovf must be cleared by software. it is set by hardware, however, and cannot be set by software. bit 5: ovf description 0 to clear ovf, the cpu must read ovf after it has been set to 1, then write a 0 in this bit. (initial value) 1 this bit is set to 1 when tcnt changes from h'ff to h'00. 199 bit 4?eserved: this bit is always read as 1. it cannot be written. bits 3 to 0?utput select 3 to 0 (os3 to os0): these bits specify the effect of tcor?cnt compare-match events on the timer output signal (tmo). bits os3 and os2 control the effect of compare-match b on the output level. bits os1 and os0 control the effect of compare-match a on the output level. if compare-match a and b occur simultaneously, any conflict is resolved according to the following priority order: toggle > 1 output > 0 output. when all four output select bits are cleared to 0 the timer output signal is disabled. after a reset, the timer output is 0 until the first compare-match event. bit 3: os3 bit 2: os2 description 0 0 no change when compare-match b occurs. (initial value) 1 output changes to 0 when compare-match b occurs. 1 0 output changes to 1 when compare-match b occurs. 1 output inverts (toggles) when compare-match b occurs. bit 1: os3 bit 0: os2 description 0 0 no change when compare-match a occurs. (initial value) 1 output changes to 0 when compare-match a occurs. 1 0 output changes to 1 when compare-match a occurs. 1 output inverts (toggles) when compare-match a occurs. 200 9.2.5 serial/timer control register (stcr) bit 76543210 iics iicd iicx iice stac mpe icks1 icks0 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w stcr is an 8-bit readable/writable register that controls the i 2 c bus interface and host interface, controls the operating mode of the serial communication interface, and selects internal clock sources for the timer counters. stcr is initialized to h'00 by a reset. bits 7 to 4? 2 c control (iics, iicd, iicx, iice): these bits control operation of the i 2 c bus interface. for details, see section 13, i 2 c bus interface. bit 3?lave input switch (stac): controls the switching of the host interface input pins. for details, see section 14, host interface. bit 2?ultiprocessor enable (mpe): controls the operating mode of serial communication interfaces 0 and 1. for details, see section 12, serial communication interface. bits 1 and 0?nternal clock source select 1 and 0 (icks1 and icks0): these bits and bits cks2 to cks0 in tcr select clock sources for the timer counters. for details, see section 9.2.3, timer control register. 201 9.3 operation 9.3.1 tcnt increment timing the timer counter increments on a pulse generated once for each period of the selected (internal or external) clock source. internal clock: internal clock sources are created from the system clock by a prescaler. the counter increments on an internal tcnt clock pulse generated from the falling edge of the prescaler output, as shown in figure 9.2. bits cks2 to cks0 of tcr and bits icks1 and icks0 of stcr can select one of the six internal clocks. n 1 tcnt clock pulse tcnt internal clock n n + 1 figure 9.2 increment timing for internal clock input 202 external clock: if external clock input (tmci) is selected, the timer counter can increment on the rising edge, the falling edge, or both edges of the external clock signal. figure 9.3 shows incrementation on both edges of the external clock signal. the external clock pulse width must be at least 1.5 system clock (? periods for incrementation on a single edge, and at least 2.5 system clock periods for incrementation on both edges. the counter will not increment correctly if the pulse width is shorter than these values. n 1 n n + 1 tcnt clock pulse tcnt external clock source (tmci) figure 9.3 increment timing for external clock input 203 9.3.2 compare-match timing setting of compare-match flags a and b (cmfa and cmfb): the compare-match flags are set to 1 by an internal compare-match signal generated when the timer count matches the time constant in tcora or tcorb. the compare-match signal is generated at the last state in which the match is true, just before the timer counter increments to a new value. accordingly, when the timer count matches one of the time constants, the compare-match signal is not generated until the next period of the clock source. figure 9.4 shows the timing of the setting of the compare-match flags. tcor internal compare- match signal tcnt n n n + 1 cmf figure 9.4 setting of compare-match flags 204 output timing: when a compare-match event occurs, the timer output changes as specified by the output select bits (os3 to os0) in the tcsr. depending on these bits, the output can remain the same, change to 0, change to 1, or toggle. figure 9.5 shows the timing when the output is set to toggle on compare-match a. timer output ( tmo ) internal compare- match a signal figure 9.5 timing of timer output timing of compare-match clear: depending on the cclr1 and cclr0 bits in tcr, the timer counter can be cleared when compare-match a or b occurs. figure 9.6 shows the timing of this operation. tcnt internal compare- match signal n h'00 figure 9.6 timing of compare-match clear 205 9.3.3 external reset of tcnt when the cclr1 and cclr0 bits in tcr are both set to 1, the timer counter is cleared on the rising edge of an external reset input. figure 9.7 shows the timing of this operation. the timer reset pulse width must be at least 1.5 system clock (? periods. internal clear pulse tcnt external reset input (tmri) n 1 n h'00 figure 9.7 timing of external reset 9.3.4 setting of overflow flag (ovf) the overflow flag (ovf) in tcsr is set to 1 when the timer count overflows (changes from h'ff to h'00). figure 9.8 shows the timing of this operation. h'ff h'00 internal overflow signal tcnt ovf figure 9.8 setting of overflow flag (ovf) 206 9.4 interrupts each channel in the 8-bit timer can generate three types of interrupts: compare-match a and b (cmia and cmib), and overflow (ovi). each interrupt can be enabled or disabled by an enable bit in tcr. independent signals are sent to the interrupt controller for each interrupt. table 9.3 lists information about these interrupts. table 9.3 8-bit timer interrupts interrupt description priority cmia requested by cmfa high cmib requested by cmfb ovi requested by ovf low 9.5 sample application in the example below, the 8-bit timer is used to generate a pulse output with a selected duty cycle. the control bits are set as follows: 1. in tcr, cclr1 is cleared to 0 and cclr0 is set to 1 so that the timer counter is cleared when its value matches the constant in tcora. 2. in tcsr, bits os3 to os0 are set to 0110, causing the output to change to 1 on compare-match a and to 0 on compare-match b. with these settings, the 8-bit timer provides output of pulses at a rate determined by tcora with a pulse width determined by tcorb. no software intervention is required. tcnt clear counter h'ff tcora tcorb h'00 tmo figure 9.9 example of pulse output 207 9.6 application notes application programmers should note that the following types of contention can occur in the 8-bit timer. 9.6.1 contention between tcnt write and clear if an internal counter clear signal is generated during the t 3 state of a write cycle to the timer counter, the clear signal takes priority and the write is not performed. figure 9.10 shows this type of contention. t 1 t 2 t 3 write cycle: cpu writes to tcnt internal address bus tcnt address internal write signal counter clear signal tcnt n h'00 figure 9.10 tcnt write-clear contention 208 9.6.2 contention between tcnt write and increment if a timer counter increment pulse is generated during the t 3 state of a write cycle to the timer counter, the write takes priority and the timer counter is not incremented. figure 9.11 shows this type of contention. t 1 t 2 t 3 write cycle: cpu writes to tcnt internal address bus internal write signal tcnt clock pulse tnct n m write data tcnt address figure 9.11 tcnt write-increment contention 209 9.6.3 contention between tcor write and compare-match if a compare-match occurs during the t 3 state of a write cycle to tcor, the write takes priority and the compare-match signal is inhibited. figure 9.12 shows this type of contention. t 1 t 2 t 3 write cycle: cpu writes to tcor internal address bus internal write signal tcnt tcor n m tcor write data tcor address n n + 1 compare-match a or b signal inhibited figure 9.12 contention between tcor write and compare-match 210 9.6.4 contention between compare-match a and compare-match b if identical time constants are written in tcora and tcorb, causing compare-match a and b to occur simultaneously, any conflict between the output selections for compare-match a and b is resolved by following the priority order in table 9.4. table 9.4 priority of timer output output selection priority toggle high 1 output 0 output no change low 9.6.5 increment caused by changing of internal clock source when an internal clock source is changed, the changeover may cause the timer counter to increment. this depends on the time at which the clock select bits (cks1, cks0) are rewritten, as shown in table 9.5. the pulse that increments the timer counter is generated at the falling edge of the internal clock source signal. if clock sources are changed when the old source is high and the new source is low, as in case no. 3 in table 9.5, the changeover generates a falling edge that triggers the tcnt clock pulse and increments the timer counter. switching between an internal and external clock source can also cause the timer counter to increment. 211 table 9.5 effect of changing internal clock sources no. description timing 1 low low * 1 n + 1 old clock source new clock source tcnt clock pulse tcnt cks rewrite n 2 low high * 2 n + 1 n + 2 old clock source new clock source tcnt clock pulse tcnt cks rewrite n 212 no. description timing 3 high low * 3 n + 1 n n + 2 * 4 old clock source new clock source tcnt clock pulse tcnt cks rewrite 4 high high n + 1 n + 2 n old clock source new clock source tcnt clock pulse cks rewrite tcnt notes: * 1 including a transition from low to the stopped state (cks1 = 0, cks0 = 0), or a transition from the stopped state to low. * 2 including a transition from the stopped state to high. * 3 including a transition from high to the stopped state. * 4 the switching of clock sources is regarded as a falling edge that increments tcnt. 213 section 10 pwm timers 10.1 overview the h8/3337 series and h8/3397 series have an on-chip pulse-width modulation (pwm) timer module with two independent channels (pwm0 and pwm1). both channels are functionally identical. each pwm channel generates a rectangular output pulse with a duty cycle of 0 to 100%. the duty cycle is specified in an 8-bit duty register (dtr). 10.1.1 features the pwm timer module has the following features: ? selection of eight clock sources ? duty cycles from 0 to 100% with 1/250 resolution ? direct or inverted pwm output, and software enable/disable control 214 10.1.2 block diagram figure 10.1 shows a block diagram of one pwm timer channel. comparator dtr bus interface internal data bus pulse tcr tcnt compare-match p /2 p /8 p /32 p /128 p /256 p /1024 p /2048 p /4096 output control clock clock select internal clock sources dtr: tcnt: tcr: duty register (8 bits) timer counter (8 bits) timer control re g ister ( 8 bits ) module data bus figure 10.1 block diagram of pwm timer (one channel) 10.1.3 input and output pins table 10.1 lists the output pins of the pwm timer module. there are no input pins. table 10.1 output pins of pwm timer module name abbreviation i/o function pwm0 output pw 0 output pulse output from pwm timer channel 0. pwm1 output pw 1 output pulse output from pwm timer channel 1. 215 10.1.4 register configuration the pwm timer module has three registers for each channel as listed in table 10.2. table 10.2 pwm timer registers initial address name abbreviation r/w value pwm0 pwm1 timer control register tcr r/w h'38 h'ffa0 h'ffa4 duty register dtr r/w h'ff h'ffa1 h'ffa5 timer counter tcnt r/w h'00 h'ffa2 h'ffa6 10.2 register descriptions 10.2.1 timer counter (tcnt) bit 76543210 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w tcnt is an 8-bit readable/writable up-counter. when the output enable bit (oe) is set to 1 in tcr, tcnt starts counting pulses of an internal clock source selected by clock select bits 2 to 0 (cks2 to cks0). after counting from h'00 to h'f9, the count repeats from h'00. when tcnt changes from h'00 to to h'01, the pwm output is placed in the 1 state, unless the dtr value is h'00, in which case the duty cycle is 0% and the pwm output remains in the 0 state. tcnt is initialized to h'00 at a reset and in the standby modes, and when the oe bit is cleared to 0. 216 10.2.2 duty register (dtr) bit 76543210 initial value 1 1 1 1 1 1 1 1 read/write r/w r/w r/w r/w r/w r/w r/w r/w dtr is an 8-bit readable/writable register that specifies the duty cycle of the output pulse. any duty cycle from 0% to 100% can be output by setting the corresponding value in dtr. the resolution is 1/250. writing 0 (h'00) in dtr gives a 0% duty cycle. writing 125 (h'7d) gives a 50% duty cycle. writing 250 (h'fa) gives a 100% duty cycle. the dtr and tcnt values are always compared. when the values match, the pwm output is placed in the 0 state. dtr is double-buffered. a new value written in dtr does not become valid until after the timer count changes from h'f9 to h'00. while the oe bit is cleared to 0 in tcr, however, new values written in dtr become valid immediately. when dtr is read, the value read is the currently valid value. dtr is initialized to h'ff by a reset and in the standby modes. 217 10.2.3 timer control register (tcr) bit 76543210 oe os cks2 cks1 cks0 initial value 0 0 1 1 1 0 0 0 read/write r/w r/w r/w r/w r/w tcr is an 8-bit readable/writable register that selects the clock input to tcnt and controls pwm output. tcr is initialized to h'38 by a reset and in standby mode. bit 7?utput enable (oe): this bit enables the timer counter and the pwm output. bit 7: oe description 0 pwm output is disabled. tcnt is cleared to h'00 and stopped. (initial value) 1 pwm output is enabled. tcnt runs. bit 6?utput select (os): this bit selects positive or negative logic for the pwm output. bit 6: os description 0 positive logic; positive-going pwm pulse, 1 = high (initial value) 1 negative logic; negative-going pwm pulse, 1 = low bits 5 to 3?eserved: these bits cannot be modified and are always read as 1. 218 bits 2, 1, and 0?lock select (cks2, cks1, and cks0): these bits select one of eight internal clock sources obtained by dividing the supporting-module clock ( p ). bit 2: cks2 bit 1: cks1 bit 0: cks0 description 000 p /2 (initial value) 1 p /8 10 p /32 1 p /128 100 p /256 1 p /1024 10 p /2048 1 p /4096 from the clock source frequency, the resolution, period, and frequency of the pwm output can be calculated as follows. resolution = 1/clock source frequency pwm period = resolution 250 pwm frequency = 1/pwm period if the p clock frequency is 10 mhz, then the resolution, period, and frequency of the pwm output for each clock source are as shown in table 10.3. table 10.3 pwm timer parameters for 10 mhz system clock internal clock frequency resolution pwm period pwm frequency p /2 200 ns 50 s 20 khz p /8 800 ns 200 s 5 khz p /32 3.2 s 800 s 1.25 khz p /128 12.8 s 3.2 ms 312.5 hz p /256 25.6 s 6.4 ms 156.3 hz p /1024 102.4 s 25.6 ms 39.1 hz p /2048 204.8 s 51.2 ms 19.5 hz p /4096 409.6 s 102.4 ms 9.8 hz 219 10.3 operation 10.3.1 timer incrementation the pwm clock source is created by dividing the system clock (?. the timer counter increments on a tcnt clock pulse generated from the falling edge of the prescaler output as shown in figure 10.2. n 1 tcnt clock pulse tcnt prescaler output n n + 1 figure 10.2 tcnt increment timing 220 10.3.2 pwm operation figure 10.3 is a timing chart of the pwm operation. n 1 n + 1 (a) h'00 (b) h'01 h'02 n h'f9 (d) h'00 h'01 n (d) m h'ff (c) (a) * (e) * (b) (c) n written in dtr m written in dtr tcnt clock pulses oe tcnt dtr (os = 0) pwm output (os = 1) one pwm cycle note: * state depends on values in data register and data direction register. figure 10.3 pwm timing 221 direct output (os = 0) 1. when (oe = 0) (a) in figure 10.3 the timer count is held at h'00 and pwm output is inhibited. [pin 4 6 (for pw0) or pin 4 7 (for pw1) is used for port 4 input/output, and its state depends on the corresponding port 4 data register and data direction register.] any value (such as n in figure 10.3) written in the dtr becomes valid immediately. 2. when (oe = 1) a. the timer counter begins incrementing. the pwm output goes high when tcnt changes from h'00 to h'01, unless dtr = h'00. [(b) in figure 10.3] b. when the count passes the dtr value, the pwm output goes low. [(c) in figure 10.3] c. if the dtr value is changed (by writing the data m in figure 10.3), the new value becomes valid after the timer count changes from h'f9 to h'00. [(d) in figure 10.3] inverted output (os = 1)?e) in figure 10.3: the operation is the same except that high and low are reversed in the pwm output. [(e) in figure 10.3] 10.4 application notes some notes on the use of the pwm timer module are given below. 1. any necessary changes to the clock select bits (cks2 to cks0) and output select bit (os) should be made before the output enable bit (oe) is set to 1. 2. if the dtr value is h'00, the duty cycle is 0% and pwm output remains constant at 0. if the dtr value is h'fa to h'ff, the duty cycle is 100% and pwm output remains constant at 1. (for direct output, 0 is low and 1 is high. for inverted output, 0 is high and 1 is low.) 222 223 section 11 watchdog timer 11.1 overview the h8/3337 series and h8/3397 series have an on-chip watchdog timer (wdt) that can monitor system operation by resetting the cpu or generating a nonmaskable interrupt if a system crash allows the timer count to overflow. when this watchdog function is not needed, the watchdog timer module can be used as an interval timer. in interval timer mode, it requests an wovf interrupt at each counter overflow. 11.1.1 features wdt features are shown below. ? selection of eight counter input clocks ? switchable between watchdog timer mode and interval timer mode ? timer counter overflow generates an internal reset or internal interrupt: ? selection of internal reset or internal interrupt generation in watchdog timer mode ? wovf interrupt request in interval timer mode 224 11.1.2 block diagram figure 11.1 is a block diagram of the watchdog timer. interrupt control internal reset or internal nmi (watchdog timer mode) wovf interrupt request signal (interval timer mode) overflow tcnt tcsr read/write control internal data bus clock select p /2 p /32 p /64 p /128 p /256 p /512 p /2048 p /4096 internal clock source clock tcnt: tcsr: timer counter timer control/status register figure 11.1 block diagram of watchdog timer 11.1.3 register configuration table 11.1 lists information on the watchdog timer registers. table 11.1 register configuration initial addresses name abbreviation r/w value write read timer control/status register tcsr r/(w) * h'10 h'ffa8 h'ffa8 timer counter tcnt r/w h'00 h'ffa8 h'ffa9 note: * software can write a 0 to clear the status flag bits, but cannot write 1. 225 11.2 register descriptions 11.2.1 timer counter (tcnt) bit 76543210 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w tcnt is an 8-bit readable/writable up-counter. when the timer enable bit (tme) in the timer control/status register (tcsr) is set to 1, the timer counter starts counting pulses of an internal clock source selected by clock select bits 2 to 0 (cks2 to cks0) in tcsr. when the count overflows (changes from h'ff to h'00), an overflow flag (ovf) in tcsr is set to 1. tcnt is initialized to h'00 by a reset and when the tme bit is cleared to 0. note: tcnt is write-protected by a password. see section 11.2.3, register access, for details. 11.2.2 timer control/status register (tcsr) bit 76543210 ovf wt/ it tme rst/ nmi cks2 cks1 cks0 initial value 0 0 0 1 0 0 0 0 read/write r/(w) * r/w r/w r/w r/w r/w r/w note: * software can write a 0 in bit 7 to clear the flag, but cannot write a 1 in this bit. tcsr is an 8-bit readable/writable register that selects the timer mode and clock source and performs other functions. bits 7 to 5 and bit 3 are initialized to 0 by a reset and in the standby modes. bits 2 to 0 are initialized to 0 by a reset, but retain their values in the standby modes. note: tcsr is write-protected by a password. see section 11.2.3, register access, for details. 226 bit 7?verflow flag (ovf): indicates that the watchdog timer count has overflowed from h'ff to h'00. bit 7: ovf description 0 to clear ovf, the cpu must read ovf after it has been set to 1, then write a 0 in this bit (initial value) 1 set to 1 when tcnt changes from h'ff to h'00 bit 6?imer mode select (wt/ it ): selects whether to operate in watchdog timer mode or interval timer mode. when tcnt overflows, an wovf interrupt request is sent to the cpu in interval timer mode. for watchdog timer mode, a reset or nmi interrupt is requested. bit 6: wt/ it description 0 interval timer mode (wovf request) (initial value) 1 watchdog timer mode (reset or nmi request) bit 5?imer enable (tme): enables or disables the timer. bit 5: tme description 0 tcnt is initialized to h'00 and stopped (initial value) 1 tcnt runs and requests a reset or an interrupt when it overflows bit 4?eserved: this bit cannot be modified and is always read as 1. bit 3: reset or nmi select (rst/ nmi ): selects either an internal reset or internal nmi function at watchdog timer overflow. bit 3: rst/ nmi description 0 nmi function enabled (initial value) 1 reset function enabled 227 bits 2to 0?clock select (cks2?ks0): these bits select one of eight clock sources obtained by dividing the system clock (?. the overflow interval is the time from when the watchdog timer counter begins counting from h'00 until an overflow occurs. in interval timer mode, wovf interrupts are requested at this interval. bit 2: cks2 bit 1: cks1 bit 0: cks0 description overflow interval ( p = 10 mhz) 000 p /2 51.2 s (initial value) 1 p /32 819.2 s 10 p /64 1.6 ms 1 p /128 3.3 ms 100 p /256 6.6 ms 1 p /512 13.1 ms 10 p /2048 52.4 ms 1 p /4096 104.9 ms 11.2.3 system control register (syscr) bit 76543210 ssby sts2 sts1 sts0 xrst nmieg hie rame initial value 0 0 0 0 1 0 0 1 read/write r/w r/w r/w r/w r r/w r/w r/w only bit 3 is described here. for details of other bits, see section 3.2., system control register (syscr), and descriptions of the relevant modules. bit 3?xternal reset (xrst): indicates the reset source. when the watchdog timer is used, a reset can be generated by watchdog timer overflow as well as by external reset input. xrst is a read-only bit. it is set to 1 by an external reset and cleared to 0 by an internal reset due to watchdog timer overflow when the rst/ nmi bit is 1. bit 3: xrst description 0 a reset is generated by an internal reset due to watchdog timer overflow 1 a reset is generated by external reset input (initial value) 228 11.2.4 register access the watchdog timer? tcnt and tcsr registers are more difficult to write to than other registers. the procedures for writing and reading these registers are given below. writing to tcnt and tcsr: word access is required. byte data transfer instructions cannot be used for write access. the tcnt and tcsr registers have the same write address. the write data must be contained in the lower byte of a word written at this address. the upper byte must contain h'5a (password for tcnt) or h'a5 (password for tcsr). see figure 11.2. the result of the access depicted in figure 11.2 is to transfer the write data from the lower byte to tcnt or tcsr. write data h'5a 15 8 7 0 write data h'a5 15 8 7 0 h'ffa8 h'ffa8 writing to tcnt writing to tcsr address address figure 11.2 writing to tcnt and tcsr reading tcnt and tcsr: the read addresses are h'ffa8 for tcsr and h'ffa9 for tcnt, as indicated in table 11.2. these two registers are read like other registers. byte access instructions can be used. table 11.2 read addresses of tcnt and tcsr read address register h'ffa8 tcsr h'ffa9 tcnt 229 11.3 operation 11.3.1 watchdog timer mode the watchdog timer function begins operating when software sets the wt/ it and tme bits to 1 in tcsr. thereafter, software should periodically rewrite the contents of the timer counter (normally by writing h'00) to prevent the count from overflowing. if a program crash allows the timer count to overflow, the entire chip is reset for 518 system clocks (518 ?, or an nmi interrupt is requested. figure 11.3 shows the operation. nmi requests from the watchdog timer have the same vector as nmi requests from the nmi pin. avoid simultaneous handling of watchdog timer nmi requests and nmi requests from pin nmi . a reset from the watchdog timer has the same vector as an external reset from the res pin. the reset source can be determined by the xrst bit in syscr. h'ff h'00 tcnt count wdt overflow wt/ it h'00 written to tcnt wt/ it figure 11.3 operation in watchdog timer mode 230 11.3.2 interval timer mode interval timer operation begins when the wt/ it bit is cleared to 0 and the tme bit is set to 1. in interval timer mode, an wovf request is generated each time the timer count overflows. this function can be used to generate wovf requests at regular intervals. see figure 11.4. h'ff h'00 wt/ it figure 11.4 operation in interval timer mode 11.3.3 setting the overflow flag the ovf bit is set to 1 when the timer count overflows. simultaneously, the wdt module requests an internal reset, nmi, or wovf interrupt. the timing is shown in figure 11.5. h'ff h'00 tcnt internal overflow signal ovf figure 11.5 setting the ovf bit 231 11.4 application notes 11.4.1 contention between tcnt write and increment if a timer counter clock pulse is generated during the t 3 state of a write cycle to the timer counter, the write takes priority and the timer counter is not incremented. see figure 11.6. tcnt address nm counter write data internal address bus internal write signal tcnt clock pulse tcnt t 3 t 2 t 1 write cycle (cpu writes to tcnt) figure 11.6 tcnt write-increment contention 11.4.2 changing the clock select bits (cks2 to cks0) software should stop the watchdog timer (by clearing the tme bit to 0) before changing the value of the clock select bits. if the clock select bits are modified while the watchdog timer is running, the timer count may be incremented incorrectly. 11.4.3 recovery from software standby mode tcsr bits, except bits 0?, and the tcnt counter are reset when the chip recovers from software standby mode. re-initialize the watchdog timer as necessary to resume normal operation. 232 11.4.4 switching between watchdog timer mode and interval timer mode if a switch is made between watchdog timer mode and interval timer mode while the wdt is operating, correct operation may not be performed. the wdt must be stopped (by clearing the tme bit to 0) before changing the timer mode. 11.4.5 detection of program runaway the following points should be noted when using the microcomputer? on-chip watchdog timer to detect program runaway. during program runaway, instructions other than the usual instructions may be executed. if an instruction reserved for system use is executed as a result of runaway, the watchdog timer may sometimes stop, preventing detection of the runaway. this problem can be avoided by making the following settings in the program. 1. set code h'0004 in rom address h'0002. 2. set code h'56f0 in rom address h'0004. as system reserved addresses may be used by an emulator, the above settings should only be made for the real chip. 233 section 12 serial communication interface 12.1 overview the h8/3337 series and h8/3397 series include two serial communication interface channels (sci0 and sci1) for transferring serial data to and from other chips. either synchronous or asynchronous communication can be selected. 12.1.1 features the features of the on-chip serial communication interface are: ? asynchronous mode the h8/3337 series and h8/3397 series can communicate with a uart (universal asynchronous receiver/transmitter), acia (asynchronous communication interface adapter), or other chip that employs standard asynchronous serial communication. it also has a multiprocessor communication function for communication with other processors. twelve data formats are available. ? data length: 7 or 8 bits ? stop bit length: 1 or 2 bits ? parity: even, odd, or none ? multiprocessor bit: 1 or 0 ? error detection: parity, overrun, and framing errors ? break detection: when a framing error occurs, the break condition can be detected by reading the level of the rxd line directly. ? synchronous mode the sci can communicate with chips able to perform clocked synchronous data transfer. ? data length: 8 bits ? error detection: overrun errors ? full duplex communication the transmitting and receiving sections are independent, so each channel can transmit and receive simultaneously. both the transmit and receive sections use double buffering, so continuous data transfer is possible in either direction. ? built-in baud rate generator any specified bit rate can be generated. ? internal or external clock source the sci can operate on an internal clock signal from the baud rate generator, or an external clock signal input at the sck0 or sck1 pin. 234 ? four interrupts tdr-empty, tsr-empty, receive-end, and receive-error interrupts are requested independently. 12.1.2 block diagram figure 12.1 shows a block diagram of one serial communication interface channel. tdr bus interface internal data bus parity generate clock parity check tsr p /4 p /16 p /64 rxd txd txi rxi eri interrupt signals external clock source internal clock rdr rsr sck brr communi- cation control ssr scr smr baud rate generator rsr: rdr: tsr: tdr: smr: scr: ssr: brr: receive shift register (8 bits) receive data register (8 bits) transmit shift register (8 bits) transmit data register (8 bits) serial mode register (8 bits) serial control register (8 bits) serial status register (8 bits) bit rate re g ister ( 8 bits ) tei module data bus figure 12.1 block diagram of serial communication interface 235 12.1.3 input and output pins table 12.1 lists the input and output pins used by the sci module. table 12.1 sci input/output pins channel name abbreviation i/o function 0 serial clock input/output sck0 input/output sci0 clock input and output receive data input rxd0 input sci0 receive data input transmit data output txd0 output sci0 transmit data output 1 serial clock input/output sck1 input/output sci1 clock input and output receive data input rxd1 input sci1 receive data input transmit data output txd1 output sci1 transmit data output note: in this manual, the channel subscript has been deleted, and only sck, rxd, and txd are used. 236 12.1.4 register configuration table 12.2 lists the sci registers. these registers specify the operating mode (synchronous or asynchronous), data format and bit rate, and control the transmit and receive sections. table 12.2 sci registers channel name abbreviation r/w initial value address 0 receive shift register rsr receive data register rdr r h'00 h'ffdd transmit shift register tsr transmit data register tdr r/w h'ff h'ffdb serial mode register smr * 2 r/w h'00 h'ffd8 serial control register scr r/w h'00 h'ffda serial status register ssr r/(w) * 1 h'84 h'ffdc bit rate register brr * 2 r/w h'ff h'ffd9 1 receive shift register rsr receive data register rdr r h'00 h'ff8d transmit shift register tsr transmit data register tdr r/w h'ff h'ff8b serial mode register smr r/w h'00 h'ff88 serial control register scr r/w h'00 h'ff8a serial status register ssr r/(w) * 1 h'84 h'ff8c bit rate register brr r/w h'ff h'ff89 0 and 1 serial/timer control register stcr r/w h'00 h'ffc3 notes: * 1 software can write a 0 to clear the flags in bits 7 to 3, but cannot write 1 in these bits. * 2 smr and brr have the same addresses as i 2 c bus interface registers iccr and icsr. for the access switching method and other details, see section 13, i 2 c bus interface. 237 12.2 register descriptions 12.2.1 receive shift register (rsr) bit 76543210 read/write rsr is a shift register that converts incoming serial data to parallel data. when one data character has been received, it is transferred to the receive data register (rdr). the cpu cannot read or write rsr directly. 12.2.2 receive data register (rdr) bit 76543210 initial value 0 0 0 0 0 0 0 0 read/write r r r r r r r r rdr stores received data. as each character is received, it is transferred from rsr to rdr, enabling rsr to receive the next character. this double-buffering allows the sci to receive data continuously. rdr is a read-only register. rdr is initialized to h'00 by a reset and in the standby modes. 12.2.3 transmit shift register (tsr) bit 76543210 read/write tsr is a shift register that converts parallel data to serial transmit data. when transmission of one character is completed, the next character is moved from the transmit data register (tdr) to tsr and transmission of that character begins. if the tdre bit is still set to 1, however, nothing is transferred to tsr. the cpu cannot read or write tsr directly. 238 12.2.4 transmit data register (tdr) bit 76543210 initial value 1 1 1 1 1 1 1 1 read/write r/w r/w r/w r/w r/w r/w r/w r/w tdr is an 8-bit readable/writable register that holds the next data to be transmitted. when tsr becomes empty, the data written in tdr is transferred to tsr. continuous data transmission is possible by writing the next data in tdr while the current data is being transmitted from tsr. tdr is initialized to h'ff by a reset and in the standby modes. 12.2.5 serial mode register (smr) bit 76543210 c/ a chr pe o/ e stop mp cks1 cks0 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w smr is an 8-bit readable/writable register that controls the communication format and selects the clock source of the on-chip baud rate generator. it is initialized to h'00 by a reset and in the standby modes. for further information on the smr settings and communication formats, see tables 12.5 and 12.7 in section 12.3, operation. bit 7?ommunication mode (c/ a ): this bit selects asynchronous or synchronous communication mode. bit 7: c/ a description 0 asynchronous communication (initial value) 1 synchronous communication bit 6?haracter length (chr): this bit selects the character length in asynchronous mode. it is ignored in synchronous mode. bit 6: chr description 0 8 bits per character (initial value) 1 7 bits per character (bits 0 to 6 of tdr and rdr are used for transmitting and receiving, respectively.) 239 bit 5?arity enable (pe): this bit selects whether to add a parity bit in asynchronous mode. it is ignored in synchronous mode, and when a multiprocessor format is used. bit 5: pe description 0 transmit: no parity bit is added. (initial value) receive: parity is not checked. 1 transmit: a parity bit is added. receive: parity is checked. bit 4?arity mode (o/ e ): in asynchronous mode, when parity is enabled (pe = 1), this bit selects even or odd parity. even parity means that a parity bit is added to the data bits for each character to make the total number of 1? even. odd parity means that the total number of 1? is made odd. this bit is ignored when pe = 0, or when a multiprocessor format is used. it is also ignored in synchronous mode. bit 4: o/ e description 0 even parity (initial value) 1 odd parity bit 3?top bit length (stop): this bit selects the number of stop bits. it is ignored in synchronous mode. bit 3: stop description 0 one stop bit (initial value) transmit: one stop bit is added. receive: one stop bit is checked to detect framing errors. 1 two stop bits transmit: two stop bits are added. receive: the first stop bit is checked to detect framing errors. if the second stop bit is a space (0), it is regarded as the next start bit. 240 bit 2?ultiprocessor mode (mp): this bit selects the multiprocessor format in asynchronous communication. when multiprocessor format is selected, the parity settings of the parity enable bit (pe) and parity mode bit (o/ e ) are ignored. the mp bit is ignored in synchronous communication. the mp bit is valid only when the mpe bit in the serial/timer control register (stcr) is set to 1. when the mpe bit is cleared to 0, the multiprocessor communication function is disabled regardless of the setting of the mp bit. bit 2: mp description 0 multiprocessor communication function is disabled. (initial value) 1 multiprocessor communication function is enabled. bits 1 and 0?lock select 1 and 0 (cks1 and cks0): these bits select the clock source of the on-chip baud rate generator. bit 1: cks1 bit 0: cks0 description 0 0 clock (initial value) 1 p /4 clock 10 p /16 clock 1 p /64 clock 12.2.6 serial control register (scr) bit 76543210 tie rie te re mpie teie cke1 cke0 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w scr is an 8-bit readable/writable register that enables or disables various sci functions. it is initialized to h'00 by a reset and in the standby modes. bit 7?ransmit interrupt enable (tie): this bit enables or disables the tdr-empty interrupt (txi) requested when the transmit data register empty (tdre) bit in the serial status register (ssr) is set to 1. bit 7: tie description 0 the tdr-empty interrupt request (txi) is disabled. (initial value) 1 the tdr-empty interrupt request (txi) is enabled. 241 bit 6?eceive interrupt enable (rie): this bit enables or disables the receive-end interrupt (rxi) requested when the receive data register full (rdrf) bit in the serial status register (ssr) is set to 1, and the receive error interrupt (eri) requested when the overrun error (orer), framing error (fer), or parity error (per) bit in the serial status register (ssr) is set to 1. bit 6: rie description 0 the receive-end interrupt (rxi) and receive-error (eri) requests are disabled. (initial value) 1 the receive-end interrupt (rxi) and receive-error (eri) requests are enabled. bit 5?ransmit enable (te): this bit enables or disables the transmit function. when the transmit function is enabled, the txd pin is automatically used for output. when the transmit function is disabled, the txd pin can be used as a general-purpose i/o port. bit 5: te description 0 the transmit function is disabled. (initial value) the txd pin can be used for general-purpose i/o. 1 the transmit function is enabled. the txd pin is used for output. bit 4?eceive enable (re): this bit enables or disables the receive function. when the receive function is enabled, the rxd pin is automatically used for input. when the receive function is disabled, the rxd pin is available as a general-purpose i/o port. bit 4: re description 0 the receive function is disabled. the rxd pin can be used for general-purpose i/o. (initial value) 1 the receive function is enabled. the rxd pin is used for input. bit 3?ultiprocessor interrupt enable (mpie): when serial data is received in a multiprocessor format, this bit enables or disables the receive-end interrupt (rxi) and receive- error interrupt (eri) until data with the multiprocessor bit set to 1 is received. it also enables or disables the transfer of received data from rsr to rdr, and enables or disables setting of the rdrf, fer, per, and orer bits in the serial status register (ssr). the mpie bit is ignored when the mp bit is cleared to 0, and in synchronous mode. clearing the mpie bit to 0 disables the multiprocessor receive interrupt function. in this condition data is received regardless of the value of the multiprocessor bit in the receive data. 242 setting the mpie bit to 1 enables the multiprocessor receive interrupt function. in this condition, if the multiprocessor bit in the receive data is 0, the receive-end interrupt (rxi) and receive-error interrupt (eri) are disabled, the receive data is not transferred from rsr to rdr, and the rdrf, fer, per, and orer bits in the serial status register (ssr) are not set. if the multiprocessor bit is 1, however, the mpb bit in ssr is set to 1, the mpie bit is cleared to 0, the receive data is transferred from rsr to rdr, the fer, per, and orer bits can be set, and the receive-end and receive-error interrupts are enabled. bit 3: mpie description 0 the multiprocessor receive interrupt function is disabled. (initial value) (normal receive operation) 1 the multiprocessor receive interrupt function is enabled. during the interval before data with the multiprocessor bit set to 1 is received, the receive interrupt request (rxi) and receive-error interrupt request (eri) are disabled, the rdrf, fer, per, and orer bits are not set in the serial status register (ssr), and no data is transferred from the rsr to the rdr. the mpie bit is cleared at the following times: 1. when 0 is written in mpie. 2. when data with the multiprocessor bit set to 1 is received. bit 2?ransmit-end interrupt enable (teie): this bit enables or disables the tsr-empty interrupt (tei) requested when the transmit-end bit (tend) in the serial status register (ssr) is set to 1. bit 2: teie description 0 the tsr-empty interrupt request (tei) is disabled. (initial value) 1 the tsr-empty interrupt request (tei) is enabled. bit 1?lock enable 1 (cke1): this bit selects the internal or external clock source for the baud rate generator. when the external clock source is selected, the sck pin is automatically used for input of the external clock signal. bit 1: cke1 description 0 internal clock source (initial value) when c/ a = 1, the serial clock signal is output at the sck pin. when c/ a = 0, output depends on the cke0 bit. 1 external clock source. the sck pin is used for input. 243 bit 0?lock enable 0 (cke0): when an internal clock source is used in asynchronous mode, this bit enables or disables serial clock output at the sck pin. this bit is ignored when the external clock is selected, or when synchronous mode is selected. for further information on the communication format and clock source selection, see table 12.6 in section 12.3, operation. bit 0: cke0 description 0 the sck pin is not used by the sci (and is available as a general-purpose i/o port). (initial value) 1 the sck pin is used for serial clock output. 12.2.7 serial status register (ssr) bit 76543210 tdre rdrf orer fer per tend mpb mpbt initial value 1 0 0 0 0 1 0 0 read/write r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r r r/w note: * software can write a 0 to clear the flags, but cannot write a 1 in these bits. ssr is an 8-bit register that indicates transmit and receive status. it is initialized to h'84 by a reset and in the standby modes. bit 7?ransmit data register empty (tdre): this bit indicates when transmit data can safely be written in tdr. bit 7: tdre description 0 to clear tdre, the cpu must read tdre after it has been set to 1, then write a 0 in this bit. 1 this bit is set to 1 at the following times: (initial value) 1. when tdr contents are transferred to tsr. 2. when the te bit in scr is cleared to 0. 244 bit 6?eceive data register full (rdrf): this bit indicates when one character has been received and transferred to rdr. bit 6: rdrf description 0 to clear rdrf, the cpu must read rdrf after it has been set to 1, then write a 0 in this bit. (initial value) 1 this bit is set to 1 when one character is received without error and transferred from rsr to rdr. bit 5?verrun error (orer): this bit indicates an overrun error during reception. bit 5: orer description 0 to clear orer, the cpu must read orer after it has been set to 1, then write a 0 in this bit. (initial value) 1 this bit is set to 1 if reception of the next character ends while the receive data register is still full (rdrf = 1). bit 4?raming error (fer): this bit indicates a framing error during data reception in asynchronous mode. it has no meaning in synchronous mode. bit 4: fer description 0 to clear fer, the cpu must read fer after it has been set to 1, then write a 0 in this bit. (initial value) 1 this bit is set to 1 if a framing error occurs (stop bit = 0). bit 3?arity error (per): this bit indicates a parity error during data reception in the asynchronous mode, when a communication format with parity bits is used. this bit has no meaning in the synchronous mode, or when a communication format without parity bits is used. bit 3: per description 0 to clear per, the cpu must read per after it has been set to 1, then write a 0 in this bit. (initial value) 1 this bit is set to 1 when a parity error occurs (the parity of the received data does not match the parity selected by the o/ e bit in smr). 245 bit 2?ransmit end (tend): this bit indicates that the serial communication interface has stopped transmitting because there was no valid data in tdr when the last bit of the current character was transmitted. the tend bit is also set to 1 when the te bit in the serial control register (scr) is cleared to 0. the tend bit is a read-only bit and cannot be modified directly. to use the tei interrupt, first start transmitting data, which clears tend to 0, then set teie to 1. bit 2: tend description 0 to clear tend, the cpu must read tdre after tdre has been set to 1, then write a 0 in tdre 1 this bit is set to 1 when: (initial value) 1. te = 0 2. tdre = 1 at the end of transmission of a character bit 1?ultiprocessor bit (mpb): stores the value of the multiprocessor bit in data received in a multiprocessor format in asynchronous communication mode. this bit retains its previous value in synchronous mode, when a multiprocessor format is not used, or when the re bit is cleared to 0 even if a multiprocessor format is used. mpb can be read but not written. bit 1: mpb description 0 multiprocessor bit = 0 in receive data. (initial value) 1 multiprocessor bit = 1 in receive data. bit 0?ultiprocessor bit transfer (mpbt): stores the value of the multiprocessor bit inserted in transmit data when a multiprocessor format is used in asynchronous communication mode. the mpbt bit is double-buffered in the same way as tsr and tdr. the mpbt bit has no effect in synchronous mode, or when a multiprocessor format is not used. bit 0: mpbt description 0 multiprocessor bit = 0 in transmit data. (initial value) 1 multiprocessor bit = 1 in transmit data. 246 12.2.8 bit rate register (brr) bit 76543210 initial value 1 1 1 1 1 1 1 1 read/write r/w r/w r/w r/w r/w r/w r/w r/w brr is an 8-bit register that, together with the cks1 and cks0 bits in smr, determines the bit rate output by the baud rate generator. brr is initialized to h'ff by a reset and in the standby modes. tables 12.3 and 12.6 show examples of brr settings. table 12.3 examples of brr settings in asynchronous mode (when p = ? ?(mhz) 2 2.097152 bit rate (bits/s) n n error (%) n n error (%) 110 1 141 +0.03 1 148 ?.04 150 1 103 +0.16 1 108 +0.21 300 0 207 +0.16 0 217 +0.21 600 0 103 +0.16 0 108 +0.21 1200 0 51 +0.16 0 54 ?.70 2400 0 25 +0.16 0 26 +1.14 4800 0 12 +0.16 0 13 ?.48 9600 0 6 ?.48 19200 31250 0 1 0 38400 247 ?(mhz) 2.4576 3 3.6864 4 bit rate (bits/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 1 174 ?.26 2 52 +0.50 2 64 +0.70 2 70 +0.03 150 1 127 0 1 155 +0.16 1 191 0 1 207 +0.16 300 0 255 0 1 77 +0.16 1 95 0 1 103 +0.16 600 0 127 0 0 155 +0.16 0 191 0 0 207 +0.16 1200 0 63 0 0 77 +0.16 0 95 0 0 103 +0.16 2400 0 31 0 0 38 +0.16 0 47 0 0 51 +0.16 4800 0 15 0 0 19 ?.34 0 23 0 0 25 +0.16 9600 0 7 0 0 9 ?.34 0 11 0 0 12 +0.16 19200 0 3 0 0 4 ?.34 0 5 0 31250 0 2 0 0 3 0 38400 0 1 0 0 2 0 note: if possible, the error should be within 1%. ?(mhz) 4.9152 5 6 6.144 bit rate (bits/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 2 86 +0.31 2 88 ?.25 2 106 ?.44 2 108 +0.08 150 1 255 0 2 64 +0.16 2 77 0 2 79 0 300 1 127 0 1 129 +0.16 1 155 0 1 159 0 600 0 255 0 1 64 +0.16 1 77 0 1 79 0 1200 0 127 0 0 129 +0.16 0 155 +0.16 0 159 0 2400 0 63 0 0 64 +0.16 0 77 +0.16 0 79 0 4800 0 31 0 0 32 ?.36 0 38 +0.16 0 39 0 9600 0 15 0 0 15 +1.73 0 19 ?.34 0 19 0 19200 0 7 0 0 7 +1.73 0 9 ?.34 0 4 0 31250 0 4 ?.70 0 4 0 0 5 0 0 5 +2.40 38400 0 3 0 0 3 +1.73 0 4 ?.34 0 4 0 248 ?(mhz) 7.3728 8 9.8304 10 bit rate (bits/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 2 130 ?.07 2 141 +0.03 2 174 ?.26 3 43 +0.88 150 2 95 0 2 103 +0.16 2 127 0 2 129 +0.16 300 1 191 0 1 207 +0.16 1 255 0 2 64 +0.16 600 1 95 0 1 103 +0.16 1 127 0 1 129 +0.16 1200 0 191 0 0 207 +0.16 0 255 0 1 64 +0.16 2400 0 95 0 0 103 +0.16 0 127 0 0 129 +0.16 4800 0 47 0 0 51 +0.16 0 63 0 0 64 +0.16 9600 0 23 0 0 25 +0.16 0 31 0 0 32 ?.36 19200 0 11 0 0 12 +0.16 0 15 0 0 15 +1.73 31250 0 7 0 0 9 ?.70 0 9 0 38400 0 5 0 0 7 0 0 7 +1.73 note: if possible, the error should be within 1%. ?(mhz) 12 12.288 14.7456 16 bit rate (bits/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 2 212 +0.03 2 217 +0.08 3 64 +0.76 3 70 +0.03 150 2 155 +0.16 2 159 0 2 191 0 2 207 +0.16 300 2 77 +0.16 2 79 0 2 95 0 2 103 +0.16 600 1 155 +0.16 1 159 0 1 191 0 1 207 +0.16 1200 1 77 +0.16 1 79 0 1 95 0 1 103 +0.16 2400 0 155 +0.16 0 159 0 0 191 0 0 207 +0.16 4800 0 77 +0.16 0 79 0 0 95 0 0 103 +0.16 9600 0 38 +0.16 0 39 0 0 47 0 0 51 +0.16 19200 0 19 ?.34 0 19 0 0 23 0 0 25 +0.16 31250 0 11 0 0 11 +2.4 0 14 ?.7 0 15 0 38400 0 9 ?.34 0 9 0 0 11 0 0 12 +0.16 note: if possible, the error should be within 1%. 249 table 12.4 examples of brr settings in asynchronous mode (when p = ?2) ?(mhz) 2 2.097152 bit rate (bits/s) n n error (%) n n error (%) 110 1 70 0.03 1 73 0.64 150 1 51 0.16 1 54 ?.70 300 0 207 0.16 0 217 0.21 600 0 103 0.16 0 108 0.21 1200 0 51 0.16 0 54 ?.70 2400 0 25 0.16 0 26 1.14 4800 0 12 0.16 0 13 ?.48 9600 0 6 ?.48 19200 31250 0 1 0 38400 ?(mhz) 2.4576 3 3.6864 4 bit rate (bits/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 1 86 0.31 1 106 ?.44 1 130 ?.07 1 141 0.03 150 1 63 0 1 77 0.16 1 95 0 1 103 0.16 300 0 255 0 1 38 0.16 1 47 0 1 51 0.16 600 0 127 0 0 155 0.16 0 191 0 0 207 0.16 1200 0 63 0 0 77 0.16 0 95 0 0 103 0.16 2400 0 31 0 0 38 0.16 0 47 0 0 51 0.16 4800 0 15 0 0 19 ?.34 0 23 0 0 25 0.16 9600 0 7 0 0 9 ?.34 0 11 0 0 12 0.16 19200 0 3 0 0 4 ?.34 0 5 0 31250 0 2 0 0 3 0 38400 0 1 0 0 2 0 0 2 8.51 250 ?(mhz) 4.9152 5 6 6.144 bit rate (bits/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 1 174 ?.26 1 177 ?.25 1 212 0.03 1 217 0.08 150 1 127 0 1 129 0.16 1 155 0.16 1 159 0 300 1 63 0 1 64 0.16 1 77 0.16 1 79 0 600 0 255 0 1 32 1.36 1 38 0.16 1 39 0 1200 0 127 0 0 129 0.16 0 155 0.16 0 159 0 2400 0 63 0 0 64 0.16 0 77 0.16 0 79 0 4800 0 31 0 0 32 ?.36 0 38 0.16 0 39 0 9600 0 15 0 0 15 1.73 0 19 ?.34 0 19 0 19200 0 7 0 0 7 1.73 0 9 ?.34 0 9 0 31250 0 4 ?.70 0 4 0 0 5 0 0 5 2.40 38400 0 3 0 0 3 1.73 0 4 ?.34 0 4 0 ?(mhz) 7.3728 8 9.8304 10 bit rate (bits/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 2 64 0.70 2 70 0.03 2 86 0.31 2 88 ?.25 150 1 191 0 1 207 0.16 1 255 0 2 64 0.16 300 1 95 0 1 103 0.16 1 127 0 1 129 0.16 600 1 47 0 1 51 0.16 1 63 0 1 64 0.16 1200 0 191 0 0 207 0.16 0 255 0 1 32 1.36 2400 0 95 0 0 103 0.16 0 127 0 0 129 0.16 4800 0 47 0 0 51 0.16 0 63 0 0 64 0.16 9600 0 23 0 0 25 0.16 0 31 0 0 32 ?.36 19200 0 11 0 0 12 0.16 0 15 0 0 15 1.73 31250 0 7 0 0 9 ?.70 0 9 0 38400 0 5 0 0 7 0 0 7 1.73 251 ?(mhz) 12 12.288 14.7456 16 bit rate (bits/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 2 106 ?.44 2 108 0.08 2 130 ?.07 2 141 0.03 150 2 77 0.16 2 79 0 2 95 0 2 103 0.16 300 1 155 0.16 1 159 0 1 191 0 1 207 0.16 600 1 77 0.16 1 79 0 1 95 0 1 103 0.16 1200 1 38 0.16 1 39 0 1 47 0 1 51 0.16 2400 0 155 0.16 0 159 0 0 191 0 0 207 0.16 4800 0 77 0.16 0 79 0 0 95 0 0 103 0.16 9600 0 38 0.16 0 39 0 0 47 0 0 51 0.16 19200 0 19 ?.34 0 19 0 0 23 0 0 25 0.16 31250 0 11 0 0 11 2.40 0 14 ?.70 0 15 0 38400 0 9 ?.34 0 9 0 0 11 0 0 12 0.16 legend: blank: no setting is available ? a setting is available, but error occurs. 252 note: if possible, the error should be within 1%. n = 64 1 1 b = ff 64 1 p (mhz) when n (mhz) when n = 0 n: baud rate generator input clock (n = 0, 1, 2, 3) the meaning of n is given below. smr wscr n cks1 cks0 ckdbl clock 000 0 101 0 /4 210 0 /16 311 0 /64 000 1 101 1 /8 210 1 /32 311 1 /128 the bit rate error can be calculated with the formula below. error (%) = (n + 1) 1 1 253 table 12.5 examples of brr settings in synchronous mode (when p = ? ?(mhz) bit rate 24581016 (bits/s) n n n n n n n n n n n n 100 250 2 124 2 249 3 124 3 249 500 1 249 2 124 2 249 3 124 1 k 1 124 1 249 2 124 2 249 2.5 k 0 199 1 99 1 124 1 199 1 249 2 99 5 k 0 99 0 199 0 249 1 99 1 124 1 199 10 k 0 49 0 99 0 124 0 199 0 249 1 99 25 k 0 19 0 39 0 49 0 79 0 99 0 159 50 k 0 9 0 19 0 24 0 39 0 49 0 79 100 k 0 4 0 9 019 024 039 250 k 0 1 0 3 0 4 0 7 0 9 0 15 500 k 0 0 * 01 03 04 07 1 m 0 0 * 01 03 2.5 m 0 0 * 4 m 00 * legend: blank: no setting is available : a setting is available, but error occurs. * : continuous transfer is not possible 254 table 12.6 examples of brr settings in synchronous mode (when p = ?2) ?(mhz) bit rate 24581016 (bits/s) n n n n n n n n n n n n 100 250 1 249 2 124 2 249 3 124 500 1 124 1 249 2 124 2 249 1 k 1 124 1 249 2 124 2.5 k 0 199 1 49 1 99 1 124 1 199 5 k 0 99 0 199 0 249 1 49 199 10 k 0 49 0 99 0 124 0 199 0 249 1 49 25 k 0 19 0 39 0 49 0 79 0 99 0 159 50 k 0 9 0 19 0 24 0 39 0 49 0 79 100 k 0 4 0 9 019 024 039 250 k 0 1 0 3 0 4 0 7 0 9 0 15 500 k 0 0 * 01 03 04 07 1 m 0 0 * 01 03 2.5 m 00 * 4 m 00 * legend: blank: no setting is available : a setting is available, but error occurs. * : continuous transfer is not possible 255 n = 8 1 1 b = ff 8 1 p (mhz) when n (mhz) when n = 0 n: baud rate generator input clock (n = 0, 1, 2, 3) the meaning of n is given below. smr wscr n cks1 cks0 ckdbl clock 000 0 101 0 /4 210 0 /16 311 0 /64 000 1 101 1 /8 210 1 /32 311 1 /128 256 12.2.9 serial/timer control register (stcr) bit 76543210 iics iicd iicx iice stac mpe icks1 icks0 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w stcr is an 8-bit readable/writable register that controls the sci operating mode and selects the tcnt clock source in the 8-bit timers. stcr is initialized to h'00 by a reset. bits 7 to 4? 2 c control (iics, iicd, iicx, iice): these bits control operation of the i 2 c bus interface. for details, refer to section 13, i 2 c bus interface. bit 3?lave input switch (stac): controls the input pin of the host interface. for details, refer to section 14, host interface. bit 2?ultiprocessor enable (mpe): enables or disables the multiprocessor communication function on channels sci0 and sci1. bit 2: mpe description 0 the multiprocessor communication function is disabled, regardless of the setting of the mp bit in smr. (initial value) 1 the multiprocessor communication function is enabled. the multiprocessor format can be selected by setting the mp bit in smr to 1. bits 1 and 0?nternal clock source select 1 and 0 (icks1, icks0): these bits select the clock input to the timer counters (tcnt) in the 8-bit timers. for details, see section 9, 8-bit timers. 257 12.3 operation 12.3.1 overview the sci supports serial data transfer in two modes. in asynchronous mode each character is synchronized individually. in synchronous mode communication is synchronized with a clock signal. the selection of asynchronous or synchronous mode and the communication format depend on smr settings as indicated in table 12.7. the clock source depends on the settings of the c/ a bit in smr and the cke1 and cke0 bits in scr as indicated in table 12.8. asynchronous mode ? data length: 7 or 8 bits can be selected. ? a parity bit or multiprocessor bit can be added, and stop bit lengths of 1 or 2 bits can be selected. (these selections determine the communication format and character length.) ? framing errors (fer), parity errors (per), and overrun errors (orer) can be detected in receive data, and the line-break condition can be detected. ? sci clock source: an internal or external clock source can be selected. ? internal clock: the sci is clocked by the on-chip baud rate generator and can output a clock signal at the bit-rate frequency. ? external clock: the external clock frequency must be 16 times the bit rate. (the on-chip baud rate generator is not used.) synchronous mode ? communication format: the data length is 8 bits. ? overrun errors (orer) can be detected in receive data. ? sci clock source: an internal or external clock source can be selected. ? internal clock: the sci is clocked by the on-chip baud rate generator and outputs a serial clock signal to external devices. ? external clock: the on-chip baud rate generator is not used. the sci operates on the input serial clock. 258 table 12.7 communication formats used by sci smr settings communication format bit 7: c/ a bit 6: chr bit 2: mp bit 5: pe bit 3: stop mode data length multipro- cessor bit parity bit stop bit length 00000 asynchronous mode 8 bits none none 1 bit 1 2 bits 1 0 present 1 bit 1 2 bits 1 0 0 7 bits none 1 bit 1 2 bits 1 0 present 1 bit 1 2 bits 01 0 asynchronous mode 8 bits present none 1 bit 1 (multiprocessor 2 bits 10 format) 7 bits 1 bit 1 2 bits 1 synchronous mode 8 bits none none table 12.8 sci clock source selection smr scr serial transmit/receive clock bit 7: c/ a bit 1: cke1 bit 0: cke0 mode clock source sck pin function 0 0 0 async internal input/output port (not used by sci) 1 serial clock output at bit rate 1 0 external serial clock input at 16 259 12.3.2 asynchronous mode in asynchronous mode, each transmitted or received character is individually synchronized by framing it with a start bit and stop bit. full duplex data transfer is possible because the sci has independent transmit and receive sections. double buffering in both sections enables the sci to be programmed for continuous data transfer. figure 12.2 shows the general format of one character sent or received in asynchronous mode. the communication channel is normally held in the mark state (high). character transmission or reception starts with a transition to the space state (low). the first bit transmitted or received is the start bit (low). it is followed by the data bits, in which the least significant bit (lsb) comes first. the data bits are followed by the parity or multiprocessor bit, if present, then the stop bit or bits (high) confirming the end of the frame. in receiving, the sci synchronizes on the falling edge of the start bit, and samples each bit at the center of the bit (at the 8th cycle of the internal serial clock, which runs at 16 times the bit rate). d0 d1 dn start bit 1 bit 7 or 8 bits one unit of data (one character or frame) parity or multipro- cessor bit stop bit 0 or 1 bit 1 or 2 bits idle state (mark) figure 12.2 data format in asynchronous mode (example of 8-bit data with parity bit and two stop bits) 260 data format table 12.9 lists the data formats that can be sent and received in asynchronous mode. twelve formats can be selected by bits in the serial mode register (smr). table 12.9 data formats in asynchronous mode smr bits chr pe mp stop 123456789101112 0000 s 8-bit data stop 0001 s 8-bit data stop stop 0100 s 8-bit data p stop 0101 s 8-bit data p stop stop 1000 s 7-bit data stop 1001 s 7-bit data stop stop 1100 s 7-bit data p stop 1101 s 7-bit data p stop stop 0 1 0 s 8-bit data mpb stop 0 1 1 s 8-bit data mpb stop stop 1 1 0 s 7-bit data mpb stop 1 1 1 s 7-bit data mpb stop stop notes: smr: serial mode register s: start bit stop: stop bit p: parity bit mpb: multiprocessor bit 261 clock in asynchronous mode it is possible to select either an internal clock created by the on-chip baud rate generator, or an external clock input at the sck pin. the selection is made by the c/ a bit in the serial mode register (smr) and the cke1 and cke0 bits in the serial control register (scr). refer to table 12.8. if an external clock is input at the sck pin, its frequency should be 16 times the desired bit rate. if the internal clock provided by the on-chip baud rate generator is selected and the sck pin is used for clock output, the output clock frequency is equal to the bit rate, and the clock pulse rises at the center of the transmit data bits. figure 12.3 shows the phase relationship between the output clock and transmit data. 0 d0d1d2d3d4 one frame d5 d6 d7 0/1 1 1 figure 12.3 phase relationship between clock output and transmit data (asynchronous mode) transmitting and receiving data sci initialization: before transmitting or receiving, software must clear the te and re bits to 0 in the serial control register (scr), then initialize the sci following the procedure in figure 12.4. note: when changing the communication mode or format, always clear the te and re bits to 0 before following the procedure given below. clearing te to 0 sets tdre to 1 and initializes the transmit shift register (tsr). clearing re to 0, however, does not initialize the rdrf, per, fer, and orer flags and receive data register (rdr), which retain their previous contents. when an external clock is used, the clock should not be stopped during initialization or subsequent operation. sci operation becomes unreliable if the clock is stopped. 262 clear te and re bits to 0 in scr 1 bit interval elapsed? start transmitting or receiving no yes 1. 2. 3. 4. select interrupts and the clock source in the serial control register (scr). leave te and re cleared to 0. if clock output is selected, in asynchronous mode, clock output starts immediately after the setting is made in scr. select the communication format in the serial mode register (smr). write the value corresponding to the bit rate in the bit rate register (brr). this step is not necessary when an external clock is used. wait for at least the interval required to transmit or receive one bit, then set te or re in the serial control register (scr). setting te or re enables the sci to use the txd or rxd pin. also set the rie, tie, teie, and mpie bits as necessary to enable interrupts. the initial states are the mark transmit state, and the idle receive state (waiting for a start bit). 1 2 set cke1 and cke0 bits in scr (leaving te and re cleared to 0) 3 set te or re to 1 in scr, and set rie, tie, teie, and mpie as necessary 4 initialization set value in brr select communication format in smr figure 12.4 sample flowchart for sci initialization 263 transmitting serial data: follow the procedure in figure 12.5 for transmitting serial data. start transmitting read tdre bit in ssr tdre = 1? write transmit data in tdr end of transmission? end 1 2 3 no yes no yes sci initialization: the transmit data output function of the txd pin is selected automatically. after the te bit is set to 1, one frame of 1s is output, then transmission is possible. sci status check and transmit data write: read the serial status register (ssr), check that the tdre bit is 1, then write transmit data in the transmit data register (tdr) and clear tdre to 0. if a multiprocessor format is selected, after writing the transmit data write 0 or 1 in the multiprocessor bit transfer (mpbt) in ssr. transition of the tdre bit from 0 to 1 can be reported by an interrupt. to continue transmitting serial data: read the tdre bit to check whether it is safe to write; if tdre = 1, write data in tdr, then clear tdre to 0. to end serial transmission: end of transmission can be confirmed by checking transition of the tend bit from 0 to 1. this can be reported by a tei interrupt. to output a break signal at the end of serial transmission: set the ddr bit to 1 and clear the dr bit to 0 (ddr and dr are i/o port registers), then clear te to 0 in scr. (a) (b) if using multiprocessor format, select mpbt value in ssr clear tdre bit to 0 read tend bit in ssr tend = 1? no yes output break signal? no yes clear te bit in scr to 0 4 1. 2. 3. 4. initialize set dr = 0, ddr = 1 serial transmission figure 12.5 sample flowchart for transmitting serial data 264 in transmitting serial data, the sci operates as follows. 1. the sci monitors the tdre bit in ssr. when tdre is cleared to 0 the sci recognizes that the transmit data register (tdr) contains new data, and loads this data from tdr into the transmit shift register (tsr). 2. after loading the data from tdr into tsr, the sci sets the tdre bit to 1 and starts transmitting. if the tie bit (tdr-empty interrupt enable) is set to 1 in scr, the sci requests a txi interrupt (tdr-empty interrupt) at this time. serial transmit data are transmitted in the following order from the txd pin: a. start bit: one 0 bit is output. b. transmit data: seven or eight bits are output, lsb first. c. parity bit or multiprocessor bit: one parity bit (even or odd parity) or one multiprocessor bit is output. formats in which neither a parity bit nor a multiprocessor bit is output can also be selected. d. stop bit: one or two 1 bits (stop bits) are output. e. mark state: output of 1 bits continues until the start bit of the next transmit data. 3. the sci checks the tdre bit when it outputs the stop bit. if tdre is 0, after loading new data from tdr into tsr and transmitting the stop bit, the sci begins serial transmission of the next frame. if tdre is 1, after setting the tend bit to 1 in ssr and transmitting the stop bit, the sci continues 1-level output in the mark state, and if the teie bit (tsr-empty interrupt enable) in scr is set to 1, the sci generates a tei interrupt request (tsr-empty interrupt). figure 12.6 shows an example of sci transmit operation in asynchronous mode. 265 1 start bit 0 d0 d1 d7 0/1 stop bit 1 data parity bit start bit 0 d0 d1 d7 0/1 stop bit 1 data parity bit 1 idle state (mark) tdre tend txi request txi interrupt handler writes data in tdr and clears tdre to 0 txi request 1 frame tei request figure 12.6 example of sci transmit operation (8-bit data with parity and one stop bit) 266 receiving serial data: follow the procedure in figure 12.7 for receiving serial data. start receiving rdrf = 1? read receive data from rdr, and clear rdrf bit to 0 in ssr per figure 12.7 sample flowchart for receiving serial data 267 in receiving, the sci operates as follows. 1. the sci monitors the receive data line and synchronizes internally when it detects a start bit. 2. receive data is shifted into rsr in order from lsb to msb. 3. the parity bit and stop bit are received. after receiving these bits, the sci makes the following checks: a. parity check: the number of 1s in the receive data must match the even or odd parity setting of the o/ e bit in smr. b. stop bit check: the stop bit value must be 1. if there are two stop bits, only the first stop bit is checked. c. status check: rdrf must be 0 so that receive data can be loaded from rsr into rdr. if these checks all pass, the sci sets rdrf to 1 and stores the received data in rdr. if one of the checks fails (receive error), the sci operates as indicated in table 12.10. note: when a receive error flag is set, further receiving is disabled. the rdrf bit is not set to 1. be sure to clear the error flags. 4. after setting rdrf to 1, if the rie bit (receive-end interrupt enable) is set to 1 in scr, the sci requests an rxi (receive-end) interrupt. if one of the error flags (orer, per, or fer) is set to 1 and the rie bit in scr is also set to 1, the sci requests an eri (receive-error) interrupt. figure 12.8 shows an example of sci receive operation in asynchronous mode. table 12.10 receive error conditions and sci operation receive error abbreviation condition data transfer overrun error orer receiving of next data ends while rdrf is still set to 1 in ssr receive data not loaded from rsr into rdr framing error fer stop bit is 0 receive data loaded from rsr into rdr parity error per parity of receive data differs from even/odd parity setting in smr receive data loaded from rsr into rdr 268 1 start bit 0 d0 d1 d7 0/1 stop bit 1 data parity bit start bit 0 d0 d1 d7 0/1 stop bit 0 data parity bit 1 idle state (mark) rdrf fer 1 frame framing error, eri request rxi interrupt handler reads data in rdr and clears rdrf to 0 rxi request figure 12.8 example of sci receive operation (8-bit data with parity and one stop bit) multiprocessor communication the multiprocessor communication function enables several processors to share a single serial communication line. the processors communicate in asynchronous mode using a format with an additional multiprocessor bit (multiprocessor format). in multiprocessor communication, each receiving processor is addressed by an id. a serial communication cycle consists of two cycles: an id-sending cycle that identifies the receiving processor, and a data-sending cycle. the multiprocessor bit distinguishes id-sending cycles from data-sending cycles. the transmitting processor starts by sending the id of the receiving processor with which it wants to communicate as data with the multiprocessor bit set to 1. next the transmitting processor sends transmit data with the multiprocessor bit cleared to 0. receiving processors skip incoming data until they receive data with the multiprocessor bit set to 1. after receiving data with the multiprocessor bit set to 1, the receiving processor with an id matching the received data continues to receive further incoming data. multiple processors can send and receive data in this way. four formats are available. parity-bit settings are ignored when a multiprocessor format is selected. for details see table 12.9. 269 transmitting processor receiving processor a serial communication line receiving processor b receiving processor c receiving processor d (id = 01) (id = 02) (id = 03) (id = 04) serial data h'01 h'aa (mpb = 1) (mpb = 0) id-sending cycle: receiving processor address data-sending cycle: data sent to receiving processor specified by id mpb: multiprocessor bit figure 12.9 example of communication among processors using multiprocessor format (sending data h'aa to receiving processor a) 270 transmitting multiprocessor serial data: see figures 12.5 and 12.6. receiving multiprocessor serial data: follow the procedure in figure 12.10 for receiving multiprocessor serial data. start receiving set mpie bit to 1 in scr fer s own id. transition of the rdrf bit from 0 to 1 can be reported by an rxi interrupt. if the id does not match the receive data, set mpie to 1 again and clear rdrf to 0. if the id matches the receive data, clear rdrf to 0. 4. sci status check and data receiving: read ssr, check that rdrf is set to 1, then read data from the receive data register (rdr) and write 0 in the rdrf bit. transition of the rdrf bit from 0 to 1 can be reported by an rxi interrupt. 5. receive error handling and break detection: if a receive error occurs, read the orer and fer bits in ssr to identify the error. after executing the necessary error handling, clear both orer and fer to 0. receiving cannot resume while orer or fer remains set to 1. when a framing error occurs, the rxd pin can be read to detect the break state. yes no yes no initialize start error handling read rdrf bit in ssr rdrf = 1? read orer and fer bits in ssr own id? no yes read rdrf bit in ssr rdrf = 1? read orer and fer bits in ssr read receive data from rdr read receive data from rdr figure 12.10 sample flowchart for receiving multiprocessor serial data 271 figure 12.11 shows an example of an sci receive operation using a multiprocessor format (8-bit data with multiprocessor bit and one stop bit). 1 start bit 0d0d1 d71 stop bit 1 data (id1) mpb start bit 0d0d1 d70 stop bit 1 data (data1) mpb 1 idle state (mark) mpie rdrf rdr value id1 rxi request rxi handler reads rdr data and clears rdrf to 0 not own id, so mpie is set to 1 again no rxi request, rdr not updated (multiprocessor interrupt) (a) own id does not match data 1 start bit 0d0d1 d71 stop bit 1 data (id2) mpb start bit 0d0d1 d70 stop bit 1 data (data2) mpb 1 idle state (mark) mpie rdrf rdr value id2 rxi handler reads rdr data and clears rdrf to 0 own id, so receiving continues, with data received at each rxi mpie set to 1 again (multiprocessor interrupt) (b) own id matches data data 2 mpb detection mpie = 0 rxi request mpb detection mpie = 0 figure 12.11 example of sci receive operation (8-bit data with multiprocessor bit and one stop bit) 272 12.3.3 synchronous mode overview in synchronous mode, the sci transmits and receives data in synchronization with clock pulses. this mode is suitable for high-speed serial communication. the sci transmitter and receiver share the same clock but are otherwise independent, so full duplex communication is possible. the transmitter and receiver are also double buffered, so continuous transmitting or receiving is possible by reading or writing data while transmitting or receiving is in progress. figure 12.12 shows the general format in synchronous serial communication. serial clock serial data bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 lsb msb don t care don t care one unit (character or frame) of serial data ** note: high except in continuous transmitting or receiving * figure 12.12 data format in synchronous communication in synchronous serial communication, each data bit is sent on the communication line from one falling edge of the serial clock to the next. data is received in synchronization with the rising edge of the serial clock. in each character, the serial data bits are transmitted in order from lsb (first) to msb (last). after output of the msb, the communication line remains in the state of the msb. communication format: the data length is fixed at eight bits. no parity bit or multiprocessor bit can be added. clock: an internal clock generated by the on-chip baud rate generator or an external clock input from the sck pin can be selected by clearing or setting the c/ a bit in the serial mode register (smr) and the cke1 and cke0 bits in the serial control register (scr). see table 12.8. when the sci operates on an internal clock, it outputs the clock signal at the sck pin. eight clock pulses are output per transmitted or received character. when the sci is not transmitting or receiving, the clock signal remains at the high level. 273 transmitting and receiving data sci initialization: the sci must be initialized in the same way as in asynchronous mode. see figure 12.4. when switching from asynchronous mode to synchronous mode, check that the orer, fer, and per bits are cleared to 0. transmitting and receiving cannot begin if orer, fer, or per is set to 1. transmitting serial data: follow the procedure in figure 12.13 for transmitting serial data. start transmitting read tdre bit in ssr tdre = 1? write transmit data in tdr and clear tdre bit to 0 in ssr end of transmission? end 1 2 3 no yes no yes sci initialization: the transmit data output function of the txd pin is selected automatically. sci status check and transmit data write: read the serial status register (ssr), check that the tdre bit is 1, then write transmit data in the transmit data register (tdr) and clear tdre to 0. transition of the tdre bit from 0 to 1 can be reported by a txi interrupt. to continue transmitting serial data: read the tdre bit to check whether it is safe to write; if tdre = 1, write data in tdr, then clear tdre to 0. to end serial transmission: end of transmission can be confirmed by checking transition of the tend bit from 0 to 1. this can be reported by a tei interrupt. (a) (b) read tend bit in ssr tend = 1? no yes 1. 2. 3. initialize clear te bit to 0 in scr serial transmission figure 12.13 sample flowchart for serial transmitting 274 in transmitting serial data, the sci operates as follows. 1. the sci monitors the tdre bit in ssr. when tdre is cleared to 0 the sci recognizes that the transmit data register (tdr) contains new data, and loads this data from tdr into the transmit shift register (tsr). 2. after loading the data from tdr into tsr, the sci sets the tdre bit to 1 and starts transmitting. if the tie bit (tdr-empty interrupt enable) in scr is set to 1, the sci requests a txi interrupt (tdr-empty interrupt) at this time. if clock output is selected the sci outputs eight serial clock pulses, triggered by the clearing of the tdre bit to 0. if an external clock source is selected, the sci outputs data in synchronization with the input clock. data is output from the txd pin in order from lsb (bit 0) to msb (bit 7). 3. the sci checks the tdre bit when it outputs the msb (bit 7). if tdre is 0, the sci loads data from tdr into tsr, then begins serial transmission of the next frame. if tdre is 1, the sci sets the tend bit in ssr to 1, transmits the msb, then holds the output in the msb state. if the teie bit (transmit-end interrupt enable) in scr is set to 1, a tei interrupt (tsr-empty interrupt) is requested at this time. 4. after the end of serial transmission, the sck pin is held at the high level. figure 12.14 shows an example of sci transmit operation. serial clock serial data bit 0 bit 1 bit 7 bit 0 bit 1 bit 6 bit 7 txi request tdre tend txi interrupt handler writes data in tdr and clears tdre to 0 txi request tei request 1 frame figure 12.14 example of sci transmit operation 275 receiving serial data: follow the procedure in figure 12.15 for receiving serial data. when switching from asynchronous mode to synchronous mode, be sure to check that per and fer are cleared to 0. if per or fer is set to 1 the rdrf bit will not be set and both transmitting and receiving will be disabled. start receiving read orer bit in ssr orer = 1? rdrf = 1? read rdrf in ssr finished receiving? clear re to 0 in scr end error handling 1 2 3 yes no no yes no yes 4 1. 2. 3. 4. sci initialization: the receive data function of the rxd pin is selected automatically. receive error handling: if a receive error occurs, read the orer bit in ssr then, after executing the necessary error handling, clear orer to 0. neither transmitting nor receiving can resume while orer remains set to 1. when clock output mode is selected, receiving can be halted temporarily by receiving one dummy byte and causing an overrun error. when preparations to receive the next data are completed, clear the orer bit to 0. this causes receiving to resume, so return to the step marked 2 in the flowchart. sci status check and receive data read: read the serial status register (ssr), check that rdrf is set to 1, then read receive data from the receive data register (rdr) and clear rdrf to 0. transition of the rdrf bit from 0 to 1 can be reported by an rxi interrupt. to continue receiving serial data: read rdr and clear rdrf to 0 before the msb (bit 7) of the current frame is received. clear orer to 0 in ssr return overrun error handling start error handling initialize read receive data from rdr, and clear rdrf bit to 0 in ssr figure 12.15 sample flowchart for serial receiving 276 in receiving, the sci operates as follows. 1. if an external clock is selected, data is input in synchronization with the input clock. if clock output is selected, as soon as the re bit is set to 1 the sci begins outputting the serial clock and inputting data. if clock output is stopped because the orer bit is set to 1, output of the serial clock and input of data resume as soon as the orer bit is cleared to 0. 2. receive data is shifted into rsr in order from lsb to msb. after receiving the data, the sci checks that rdrf is 0 so that receive data can be loaded from rsr into rdr. if this check passes, the sci sets rdrf to 1 and stores the received data in rdr. if the check does not pass (receive error), the sci operates as indicated in table 12.10. note: both transmitting and receiving are disabled while a receive error flag is set. the rdrf bit is not set to 1. be sure to clear the error flag. 3. after setting rdrf to 1, if the rie bit (receive-end interrupt enable) is set to 1 in scr, the sci requests an rxi (receive-end) interrupt. if the orer bit is set to 1 and the rie bit in scr is set to 1, the sci requests an eri (receive-error) interrupt. when clock output mode is selected, clock output stops when the re bit is cleared to 0 or the orer bit is set to 1. to prevent clock count errors, it is safest to receive one dummy byte and generate an overrun error. figure 12.16 shows an example of sci receive operation. serial clock serial data bit 0 bit 1 bit 7 bit 0 bit 1 bit 6 bit 7 rxi request rdrf orer rxi interrupt handler reads data in rdr and clears rdrf to 0 rxi request overrun error, eri request 1 frame figure 12.16 example of sci receive operation 277 transmitting and receiving serial data simultaneously: follow the procedure in figure 12.17 for transmitting and receiving serial data simultaneously. if clock output mode is selected, output of the serial clock begins simultaneously with serial transmission. start read tdre bit in ssr tdre = 1? write transmit data in tdr and clear tdre bit to 0 in ssr rdrf = 1? read orer bit in ssr end of transmitting and receiving? clear te and re bits to 0 in scr end error handling 1 2 3 no yes yes yes no yes 4 1. 2. 3. 4. 5. sci initialization: the transmit data output function of the txd pin and receive data input function of the rxd pin are selected, enabling simultaneous transmitting and receiving. sci status check and transmit data write: read the serial status register (ssr), check that the tdre bit is 1, then write transmit data in the transmit data register (tdr) and clear tdre to 0. transition of the tdre bit from 0 to 1 can be reported by a txi interrupt. sci status check and receive data read: read the serial status register (ssr), check that the rdrf bit is 1, then read receive data from the receive data register (rdr) and clear rdrf to 0. transition of the rdrf bit from 0 to 1 can be reported by an rxi interrupt. receive error handling: if a receive error occurs, read the orer bit in ssr then, after executing the necessary error handling, clear orer to 0. neither transmitting nor receiving can resume while orer remains set to 1. to continue transmitting and receiving serial data: read rdr and clear rdrf to 0 before the msb (bit 7) of the current frame is received. also read the tdre bit and check that it is set to 1, indicating that it is safe to write; then write data in tdr and clear tdre to 0 before the msb (bit 7) of the current frame is transmitted. orer = 1? read rdrf bit in ssr 5 no no initialize read receive data from rdr and clear rdrf bit to 0 in ssr figure 12.17 sample flowchart for serial transmitting and receiving note: in switching from transmitting or receiving to simultaneous transmitting and receiving, clear both te and re to 0, then set te and re to 1 simultaneously using an mov instruction. do not use a best instruction for this purpose. 278 12.4 interrupts the sci can request four types of interrupts: eri, rxi, txi, and tei. table 12.11 indicates the source and priority of these interrupts. the interrupt sources can be enabled or disabled by the tie, rie, and teie bits in the scr. independent signals are sent to the interrupt controller for each interrupt source, except that the receive-error interrupt (eri) is the logical or of three sources: overrun error, framing error, and parity error. the txi interrupt indicates that the next transmit data can be written. the tei interrupt indicates that the sci has stopped transmitting data. table 12.11 sci interrupt sources interrupt description priority eri receive-error interrupt (orer, fer, or per) high rxi receive-end interrupt (rdrf) txi tdr-empty interrupt (tdre) tei tsr-empty interrupt (tend) low 12.5 application notes application programmers should note the following features of the sci. tdr write: the tdre bit in ssr is simply a flag that indicates that the tdr contents have been transferred to tsr. the tdr contents can be rewritten regardless of the tdre value. if a new byte is written in tdr while the tdre bit is 0, before the old tdr contents have been moved into tsr, the old byte will be lost. software should check that the tdre bit is set to 1 before writing to tdr. multiple receive errors: table 12.12 lists the values of flag bits in the ssr when multiple receive errors occur, and indicates whether the rsr contents are transferred to rdr. 279 table 12.12 ssr bit states and data transfer when multiple receive errors occur ssr bits rsr receive error rdrf orer fer per rdr * 2 overrun error 1 * 1 100no framing error 0010yes parity error 0001yes overrun and framing errors 1 * 1 110no overrun and parity errors 1 * 1 101no framing and parity errors 0011yes overrun, framing, and parity errors 1 * 1 111no notes: * 1 set to 1 before the overrun error occurs. * 2 yes: the rsr contents are transferred to rdr. no: the rsr contents are not transferred to rdr. line break detection: when the rxd pin receives a continuous stream of 0 s in asynchronous mode (line-break state), a framing error occurs because the sci detects a 0 stop bit. the value h'00 is transferred from rsr to rdr. software can detect the line-break state as a framing error accompanied by h'00 data in rdr. the sci continues to receive data, so if the fer bit is cleared to 0 another framing error will occur. sampling timing and receive margin in asynchronous mode: the serial clock used by the sci in asynchronous mode runs at 16 times the bit rate. the falling edge of the start bit is detected by sampling the rxd input on the falling edge of this clock. after the start bit is detected, each bit of receive data in the frame (including the start bit, parity bit, and stop bit or bits) is sampled on the rising edge of the serial clock pulse at the center of the bit. see figure 12.18. it follows that the receive margin can be calculated as in equation (1). when the absolute frequency deviation of the clock signal is 0 and the clock duty cycle is 0.5, data can theoretically be received with distortion up to the margin given by equation (2). this is a theoretical limit, however. in practice, system designers should allow a margin of 20% to 30%. 280 12 4 0 56 7 89 3 2 12 3456789 1 11 12 13 14 15 16 10 13 14 15 16 12 10 11 3 4 5 basic clock sync sampling data sampling d0 d1 receive data start bit 7.5 pulses +7.5 pulses figure 12.18 sampling timing (asynchronous mode) m = {(0.5 1/2n) (d 0.5)/n (l 0.5)f} ratio of high pulse width to low width (0.5 to 1.0) l: frame length (9 to 12) f: absolute clock frequency deviation when d = 0.5 and f = 0 m = (0.5 1/2 281 section 13 i 2 c bus interface (h8/3337 series only) [option] an i 2 c bus interface is available as an option. observe the following notes when using this option. ? for mask-rom versions, the y in the part number becomes a w in products in which this optional function is used. examples: hd6433337wf, hd6433334wf 13.1 overview the i 2 c bus interface conforms to and provides a subset of the philips i 2 c bus (inter-ic bus) interface functions. the register configuration that controls the i 2 c bus differs partly from the philips configuration, however. the i 2 c bus interface uses only one data line (sda) and one clock line (scl) to transfer data, so it can save board and connector space. figure 13.1 shows typical i 2 c bus interface connections. 13.1.1 features ? conforms to philips i 2 c bus interface ? start and stop conditions generated automatically ? selectable acknowledge output level when receiving ? auto-loading of acknowledge bit when transmitting ? selection of eight internal clocks (in master mode) ? selection of acknowledgement mode, or serial mode without acknowledge bit ? wait function: a wait can be inserted in acknowledgement mode by holding the scl pin low after a data transfer, before acknowledgement of the transfer. ? three interrupt sources ? data transfer end ? in slave receive mode: slave address matched, or general call address received ? in master transmit mode: bus arbitration lost ? direct bus drive (with pins scl and sda) ? the p8 6 /sck 1 /scl pin and the p9 7 / wait /sda pin are nmos outputs only when the bus drive function is selected 282 scl in scl out sda in sda out (slave 1) scl sda scl in scl out sda in sda out (slave 2) scl sda scl in scl out sda in sda out (master) scl sda v cc scl sda figure 13.1 i 2 c bus interface connections (example) (h8/3337 series chip as master) 283 13.1.2 block diagram figure 13.2 shows a block diagram of the i 2 c bus interface. p ps noise canceler noise canceler clock control bus state decision circuit arbitration decision circuit output data control circuit address comparator sar interrupt generator icdr icsr icmr iccr stcr internal data bus interrupt request scl sda legend: iccr: icmr: icsr: icdr: sar: ps: stcr: i 2 c bus control register i 2 c bus mode register i 2 c bus status register i 2 c bus data register slave address register prescaler serial timer control re g ister figure 13.2 block diagram of i 2 c bus interface 284 13.1.3 input/output pins table 13.1 summarizes the input/output pins used by the i 2 c bus interface. table 13.1 i 2 c bus interface name abbreviation i/o function serial clock scl input/output serial clock input/output serial data sda input/output serial data input/output 13.1.4 register configuration table 13.2 summarizes the registers of the i 2 c bus interface. table 13.2 i 2 c bus interface register configuration name abbreviation r/w initial value address * 2 i 2 c bus control register iccr r/w h'00 h'ffd8 i 2 c bus status register icsr r/w h'30 h'ffd9 i 2 c bus data register icdr r/w h'ffde i 2 c bus mode register icmr r/w h'38 h'ffdf * 1 slave address register sar r/w h'00 h'ffdf * 1 serial timer control register stcr r/w h'00 h'ffc3 notes: * 1 the register that can be written or read depends on the ice bit in the i 2 c bus control register. the slave address register can be accessed when ice = 0. the i 2 c bus mode register can be accessed when ice = 1. * 2 the addresses assigned to the i 2 c bus interface registers are also assigned to other registers. the accessible registers are selected with bit iice in the serial/timer control register (stcr). 285 13.2 register descriptions 13.2.1 i 2 c bus data register (icdr) bit 76543210 icdr7 icdr6 icdr5 icdr4 icdr3 icdr2 icdr1 icdr0 initial value read/write r/w r/w r/w r/w r/w r/w r/w r/w icdr is an 8-bit readable/writable register that is used as a transmit data register when transmitting and a receive data register when receiving. transmitting is started by writing data in icdr. receiving is started by reading data from icdr. icdr is also used as a shift register, so it must not be written or read until data has been completely transmitted or received. read or write access while data is being transmitted or received may result in incorrect data. the icdr value is undefined after a reset and in hardware standby mode. 13.2.2 slave address register (sar) bit 76543210 sva6 sva5 sva4 sva3 sva2 sva1 sva0 fs initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w sar is an 8-bit readable/writable register that stores the slave address and selects the communication format. when the chip is in slave mode (and the addressing format is selected), if the upper 7 bits of sar match the upper 7 bits of the first byte received after a start condition, the chip operates as the slave device specified by the master device. sar is assigned to the same address as icmr. sar can be written and read only when the ice bit is cleared to 0 in iccr. sar is initialized to h'00 by a reset and in hardware standby mode. bits 7 to 1?lave address (sva6 to sva0): set a unique address in bits sva6 to sva0, differing from the addresses of other slave devices connected to the i 2 c bus. 286 bit 0?ormat select (fs): selects whether to use the addressing format or non-addressing format in slave mode. the addressing format is used to recognize slave addresses. bit 0: fs description 0 addressing format, slave addresses recognized (initial value) 1 non-addressing format 13.2.3 i 2 c bus mode register (icmr) bit 76543210 mls wait bc2 bc1 bc0 initial value 0 0 1 1 1 0 0 0 read/write r/w r/w r/w r/w r/w icmr is an 8-bit readable/writable register that selects whether the msb or lsb is transferred first, performs wait control, and selects the transfer bit count. icmr is assigned to the same address as sar. icmr can be written and read only when the ice bit is set to 1 in iccr. icmr is initialized to h'38 by a reset and in hardware standby mode. bit 7?sb-first/lsb-first select (mls): selects whether data is transferred msb-first or lsb-first. bit 7: mls description 0 msb-first (initial value) 1 lsb-first bit 6?ait insertion bit (wait): selects whether to insert a wait between the transfer of data and the acknowledge bit, in acknowledgement mode. when wait is set to 1, after the fall of the clock for the final data bit, a wait state begins (with scl staying at the low level). when bit iric is cleared in icsr, the wait ends and the acknowledge bit is transferred. if wait is cleared to 0, data and acknowledge bits are transferred consecutively with no wait inserted. bit 6: wait description 0 data and acknowledge transferred consecutively (initial value) 1 wait inserted between data and acknowledge 287 bits 5 to 3?eserved: these bits cannot be modified and are always read as 1. bits 2 to 0?it counter (bc2 to bc0): bc2 to bc0 specify the number of bits to be transferred next. when the ack bit is cleared to 0 in iccr (acknowledgement mode), the data is transferred with one additional acknowledge bit. bc2 to bc0 settings should be made during an interval between transfer frames. if bc2 to bc0 are set to a value other than 000, the setting should be made while the scl line is low. the bit counter is initialized to 000 by a reset and when a start condition is detected. the value returns to 000 at the end of a data transfer, including the acknowledge. bit 2: bit 1: bit 0: bits/frame bc2 bc1 bc0 serial mode acknowledgement mode 0008 9 (initial value) 11 2 102 3 13 4 1004 5 15 6 106 7 17 8 13.2.4 i 2 c bus control register (iccr) bit 76543210 ice ieic mst trs ack cks2 cks1 cks0 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w iccr is an 8-bit readable/writable register that enables or disables the i 2 c bus interface, enables or disables interrupts, and selects master or slave mode, transmit or receive, acknowledgement or serial mode, and the clock frequency. iccr is initialized to h'00 by a reset and in hardware standby mode. bit 7? 2 c bus interface enable (ice): selects whether or not to use the i 2 c bus interface. when ice is set to 1, the scl and sda signals are assigned to input/output pins and transfer operations are enabled. when ice is cleared to 0, scl and sda are placed in the high-impedance state and the interface module is disabled. 288 the sar register can be accessed when ice is 0. the icmr register can be accessed when ice is 1. bit 7: ice description 0 interface module disabled, with scl and sda signals in high-impedance state (initial value) 1 interface module enabled for transfer operations (pins scl and sca are driving the bus * ) note: * pin sda is multiplexed with the wait input pin. in expanded mode, wait input has priority for this pin. bit 6? 2 c bus interface interrupt enable (ieic): enables or disables interrupts from the i 2 c bus interface to the cpu. bit 6: ieic description 0 interrupts disabled (initial value) 1 interrupts enabled bit 5?aster/slave select (mst) bit 4?ransmit/receive select (trs) mst selects whether the i 2 c bus interface operates in master mode or slave mode. trs selects whether the i 2 c bus interface operates in transmit mode or receive mode. in master mode, when arbitration is lost, mst and trs are both reset by hardware, causing a transition to slave receive mode. in slave receive mode with the addressing format (fs = 0), hardware automatically selects transmit or receive mode according to the r/w bit in the first byte after a start condition. mst and trs select the operating mode as follows. bit 5: mst bit 4: trs description 0 0 slave receive mode (initial value) 1 slave transmit mode 1 0 master receive mode 1 master transmit mode 289 bit 3?cknowledgement mode select (ack): selects acknowledgement mode or serial mode. in acknowledgement mode (ack = 0), data is transferred in frames consisting of the number of data bits selected by bc2 to bc0 in icmr, plus an extra acknowledge bit. in serial mode (ack = 1), the number of data bits selected by bc2 to bc0 in icmr is transferred as one frame. bit 3: ack description 0 acknowledgement mode (initial value) 1 serial mode bits 2 to 0?erial clock select (cks2 to cks0): these bits, together with the iicx bit in the stcr register, select the serial clock frequency in master mode. they should be set according to the required transfer rate. (stcr) bit 2: bit 1: bit 0: transfer rate * iicx cks2 cks1 cks0 clock p = 5 mhz p = 8 mhz p = 10 mhz p = 16 mhz 0 000 p /28 179 khz 286 khz 357 khz 571 khz 1 p /40 125 khz 200 khz 250 khz 400 khz 10 p /48 104 khz 167 khz 208 khz 333 khz 1 p /64 78.1 khz 125 khz 156 khz 250 khz 100 p /80 62.5 khz 100 khz 125 khz 200 khz 1 p /100 50.0 khz 80.0 khz 100 khz 160 khz 10 p /112 44.6 khz 71.4 khz 89.3 khz 143 khz 1 p /128 39.1 khz 62.5 khz 78.1 khz 125 khz 1 000 p /56 89.3 khz 143 khz 179 khz 286 khz 1 p /80 62.5 khz 100 khz 125 khz 200 khz 10 p /96 52.1 khz 83.3 khz 104 khz 167 khz 1 p /128 39.1 khz 62.5 khz 78.1 khz 125 khz 100 p /160 31.3 khz 50.0 khz 62.5 khz 100 khz 1 p /200 25.0 khz 40.0 khz 50.0 khz 80.0 khz 10 p /224 22.3 khz 35.7 khz 44.6 khz 71.4 khz 1 p /256 19.5 khz 31.3 khz 39.1 khz 62.5 khz note: * p = ? the shaded setting exceeds the maximum transfer rate in the standard i 2 c bus specifications. 290 13.2.5 i 2 c bus status register (icsr) bit 76543210 bbsy iric scp al aas adz ackb initial value 0 0 1 1 0 0 0 0 read/write r/w r/(w) * w r/(w) * r/(w) * r/(w) * r/w note: * only 0 can be written, to clear the flag. icsr is an 8-bit readable/writable register with flags that indicate the status of the i 2 c bus interface. it is also used for issuing start and stop conditions, and recognizing and controlling acknowledge data. icsr is initialized to h'30 by a reset and in hardware standby mode. bit 7?us busy (bbsy): this bit can be read to check whether the i 2 c bus (scl and sda) is busy or free. in master mode this bit is also used in issuing start and stop conditions. a high-to-low transition of sda while scl is high is recognized as a start condition, setting bbsy to 1. a low-to-high transition of sda while scl is high is recognized as a stop condition, clearing bbsy to 0. to issue a start condition, use a mov instruction to write 1 in bbsy and 0 in scp. a retransmit start condition is issued in the same way. to issue a stop condition, use a mov instruction to write 0 in bbsy and 0 in scp. it is not possible to write to bbsy in slave mode. bit 7: bbsy description 0 bus is free (initial value) this bit is cleared when a stop condition is detected. 1 bus is busy this bit is set when a start condition is detected. 291 bit 6? 2 c bus interface interrupt request flag (iric): indicates that the i 2 c bus interface has issued an interrupt request to the cpu. iric is set to 1 at the end of a data transfer, when a slave address or general call address is detected in slave receive mode, and when bus arbitration is lost in master transmit mode. iric is set at different timings depending on the ack bit in iccr and wait bit in icmr. see the item on iric set timing and scl control in section 13.3.6. iric is cleared by reading iric after it has been set to 1, then writing 0 in iric. bit 6: iric description 0 waiting for transfer, or transfer in progress (initial value) to clear this bit, the cpu must read iric when iric = 1, then write 0 in iric 1 interrupt requested this bit is set to 1 at the following times: master mode ? end of data transfer ? when bus arbitration is lost slave mode (when fs = 0) ? when the slave address is matched, and whenever a data transfer ends after that, until a retransmit start condition or a stop condition is detected ? when a general call address is detected, and whenever a data transfer ends after that, until a retransmit start condition or a stop condition is detected slave mode (when fs = 1) ? end of data transfer bit 5?tart condition/stop condition prohibit (scp): controls the issuing of start and stop conditions in master mode. to issue a start condition, write 1 in bbsy and 0 in scp. a start condition for retransmit is issued in the same way. to issue a stop condition, write 0 in bbsy and 0 in scp. this bit always reads 1. written data is not stored. bit 5: scp description 0 writing 0 issues a start or stop condition, in combination with bbsy 1 reading always results in 1 (initial value) writing is ignored bit 4?eserved: this bit cannot be modified and is always read as 1. 292 bit 3?rbitration lost flag (al): this flag indicates that arbitration was lost in master mode. the i 2 c bus interface monitors the bus. when two or more master devices attempt to seize the bus at nearly the same time, if the i 2 c bus interface detects data differing from the data it sent, it sets al to 1 to indicate that the bus has been taken by another master. at the same time, it sets the iric bit in icsr to generate an interrupt request. al is cleared by reading al after it has been set to 1, then writing 0 in al. in addition, al is reset automatically by write access to icdr in transmit mode, or read access to icdr in receive mode. bit 3: al description 0 bus arbitration won (initial value) this bit is cleared to 0 at the following times: ? when icdr data is written (transmit mode) or read (receive mode) ? when al is read while al = 1, then 0 is written in al 1 arbitration lost this bit is set to 1 at the following times: ? if the internal sda signal and bus line disagree at the rise of scl in master transmit mode ? if the internal scl is high at the fall of scl in master transmit mode bit 2?lave address recognition flag (aas): when the addressing format is selected (fs = 0) in slave receive mode, this flag is set to 1 if the first byte following a start condition matches bits sva6 to sva0 in sar, or if the general call address (h'00) is detected. aas is cleared by reading aas after it has been set to 1, then writing 0 in aas. in addition, aas is reset automatically by write access to icdr in transmit mode, or read access to icdr in receive mode. bit 2: aas description 0 slave address or general call address not recognized (initial value) this bit is cleared to 0 at the following times: ? when icdr data is written (transmit mode) or read (receive mode) ? when aas is read while aas = 1, then 0 is written in aas 1 slave address or general call address recognized this bit is set to 1 at the following times: ? when the slave address or general call address is detected in slave receive mode 293 bit 1?eneral call address recognition flag (adz): when the addressing format is selected (fs = 0) in slave receive mode, this flag is set to 1 if the first byte following a start condition is the general call address (h'00). adz is cleared by reading adz after it has been set to 1, then writing 0 in adz. in addition, adz is reset automatically by write access to icdr in transmit mode, or read access to icdr in receive mode. bit 1: adz description 0 general call address not recognized (initial value) this bit is cleared to 0 at the following times: ? when icdr data is written (transmit mode) or read (receive mode) ? when adz is read while adz = 1, then 0 is written in adz 1 general call address recognized this bit is set to 1 when the general call address is detected in slave receive mode bit 0?cknowledge bit (ackb): stores acknowledge data in acknowledgement mode. in transmit mode, after the receiving device receives data, it returns acknowledge data, and this data is loaded into ackb. in receive mode, after data has been received, the acknowledge data set in this bit is sent to the transmitting device. when this bit is read, if trs = 1, the value loaded from the bus line is read. if trs = 0, the value set by internal software is read. bit 0: ackb description 0 receive mode: 0 is output at acknowledge output timing (initial value) transmit mode: indicates that the receiving device has acknowledged the data 1 receive mode: 1 is output at acknowledge output timing transmit mode: indicates that the receiving device has not acknowledged the data 294 13.2.6 serial/timer control register (stcr) bit 76543210 iics iicd iicx iice stac mpe icks1 icks0 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w stcr is an 8-bit readable/writable register that controls the sci operating mode and selects the tcnt clock source in the 8-bit timers. stcr is initialized to h'00 by a reset and in hardware standby mode. bit 7? 2 c extra buffer select (iics): this bit is reserved, but it can be written and read. its initial value is 0. bit 6? 2 c extra buffer reserve (iicd): this bit is reserved, but it can be written and read. its initial value is 0. bit 5? 2 c transfer rate select (iicx): this bit, in combination with bits cks2 to cks0 in iccr, selects the transfer rate in master mode. for details regarding transfer rate, refer to section 13.2.4, i 2 c bus control register (iccr). bit 4? 2 c master enable (iice): controls cpu access to the data and control registers (iccr, icsr, icdr, icmr/sar) of the i 2 c bus interface. bit 4: iice description 0 cpu access to i 2 c bus interface data and control registers is disabled (initial value) 1 cpu access to i 2 c bus interface data and control registers is enabled bit 3?lave input switch (stac): switches host interface input pins. for details, see section 14, host interface. bit 2?ultiprocessor enable (mpe): enables or disables the multiprocessor communication function on channels sci0 and sci1. for details, see section 12, serial communication interface. bits 1 and 0?nternal clock source select 1 and 0 (icks1, icsk0): these bits select the clock input to the timer counters (tcnt) in the 8-bit timers. for details, see section 9, 8-bit timers. 295 13.3 operation 13.3.1 i 2 c bus data format the i 2 c bus interface has three data formats: two addressing formats, shown as (a) and (b) in figure 13.3, and a non-addressing format, shown as (c) in figure 13.4. the first byte following a start condition always consists of 8 bits. figure 13.5 shows the i 2 c bus timing. s sla r/ w a w w a a figure 13.3 i 2 c bus data formats (acknowledge formats) s data a data a a/ a figure 13.4 i 2 c bus data format (non-acknowledge format) legend: s: start condition. the master device drives sda from high to low while scl is high. sla: slave address, by which the master device selects a slave device. r/ w : indicates the direction of data transfer: from the slave device to the master device when r/ w is 1, or from the master device to the slave device when r/ w is 0. a: acknowledge. the receiving device (the slave in master transmit mode, or the master in master receive mode) drives sda low to acknowledge a transfer. if transfers need not be 296 acknowledged, set the ack bit to 1 in iccr to keep the interface from generating the acknowledge signal and its clock pulse. data: transferred data. the bit length is set by bits bc2 to bc0 in icmr. the msb-first or lsb-first format is selected by bit mls in icmr. p: stop condition. the master device drives sda from low to high while scl is high. sda scl s 1-7 sla 8 r/w 9 a 1-7 data 89 1-7 89 a data p a/ a figure 13.5 i 2 c bus timing 13.3.2 master transmit operation in master transmit mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. the transmit procedure and operations in master transmit mode are described below. 1. set bits mls and wait in icmr and bits ack and cks2 to cks0 in iccr according to the operating mode. set bit ice in iccr to 1. 2. read bbsy in icsr, check that the bus is free, then set mst and trs to 1 in iccr to select master transmit mode. after that, write 1 in bbsy and 0 in scp. this generates a start condition by causing a high-to-low transition of sda while scl is high. 3. write data in icdr. the master device outputs the written data together with a sequence of transmit clock pulses at the timing shown in figure 13.6. if fs is 0 in sar, the first byte following the start condition contains a 7-bit slave address and indicates the transmit/receive direction. the selected slave device (the device with the matching slave address) drives sda low at the ninth transmit clock pulse to acknowledge the data. 4. when 1 byte of data has been transmitted, iric is set to 1 in icsr at the rise of the ninth transmit clock pulse. if ieic is set to 1 in iccr, a cpu interrupt is requested. after one frame has been transferred, scl is automatically brought to the low level in synchronization with the internal clock and held low. 5. software clears iric to 0 in icsr. 297 6. to continue transmitting, write the next transmit data in icdr. transmission of the next byte will begin in synchronization with the internal clock. steps 4 to 6 can be repeated to transmit data continuously. to end the transmission, write 0 in bbsy and 0 in scp in icsr. this generates a stop condition by causing a low-to-high transition of sda while scl is high. 1 9 8 7 6 5 4 3 2 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 a scl sda (master output) sda (slave output) iric user processing 2. write bbsy = 1 and scp = 0 interrupt request 3. write to icdr 5. clear iric 6. write to icdr figure 13.6 operation timing in master transmit mode (mls = wait = ack = 0) 298 13.3.3 master receive operation in master receive mode, the master device outputs the receive clock, receives data, and returns an acknowledge signal. the slave device transmits the data. the receive procedure and operations in master receive mode are described below. see also figure 13.7. 1. clear trs to 0 in iccr to switch from transmit mode to receive mode. 2. read icdr to start receiving. when icdr is read, a receive clock is output in synchronization with the internal clock, and data is received. at the ninth clock pulse the master device drives sda low to acknowledge the data. 3. when 1 byte of data has been received, iric is set to 1 in icsr at the rise of the ninth receive clock pulse. if ieic is set to 1 in iccr, a cpu interrupt is requested. after one frame has been transferred, scl is automatically brought to the low level in synchronization with the internal clock and held low. 4. software clears iric to 0 in icsr. 5. when icdr is read, receiving of the next data starts in synchronization with the internal clock. steps 3 to 5 can be repeated to receive data continuously. to stop receiving, set trs to 1, read icdr, then write write 0 in bbsy and 0 in scp in icsr. this generates a stop condition by causing a low-to-high transition of sda while scl is high. if it is not necessary to acknowledge each bye of data, set ackb to 1 in icsr before receiving starts. 299 9 8 7 6 5 4 3 2 11 9 a a bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 interrupt request interrupt request master transmit mode master receive mode scl sda (slave output) sda (master output) iric user processing 2. read icdr 4. clear iric 5. read icdr figure 13.7 operation timing in master receive mode (mls = wait = ack = ackb = 0) 300 13.3.4 slave transmit operation in slave transmit mode, the slave device outputs the transmit data, and the master device outputs the transmit clock and returns an acknowledge signal. the transmit procedure and operations in slave transmit mode are described below. 1. set bits mls and wait in icmr and bits mst, trs, ack, and cks2 to cks0 in iccr according to the operating mode. set bit ice in iccr to 1. 2. after the slave device detects a start condition, if the first byte matches its slave address, at the ninth clock pulse the slave device drives sda low to acknowledge the transfer. at the same time, iric is set to 1 in icsr, generating an interrupt. if the eighth data bit (r/ w ) is 1, the trs bit is set to 1 in iccr, automatically causing a transition to slave transmit mode. the slave device holds scl low from the fall of the transmit clock until data is written in icdr. 3. software clears iric to 0 in icsr. 4. write data in icdr. the slave device outputs the written data serially in step with the clock output by the master device, with the timing shown in figure 13.8. 5. when 1 byte of data has been transmitted, at the rise of the ninth transmit clock pulse iric is set to 1 in icsr. if ieic is set to 1 in iccr, a cpu interrupt is requested. the slave device holds scl low from the fall of the transmit clock until data is written in icdr. the master device drives sda low at the ninth clock pulse to acknowledge the data. the acknowledge signal is stored in ackb in icsr, and can be used to check whether the transfer was carried out normally. 6. software clears iric to 0 in icsr. 7. to continue transmitting, write the next transmit data in icdr. steps 5 to 7 can be repeated to transmit continuously. to end the transmission, write h'ff in icdr. when a stop condition is detected (a low-to-high transition of sda while scl is high), bbsy will be cleared to 0 in icsr. 301 slave receive mode slave transmit mode scl (master output) scl (slave output) sda (slave output) sda (master output) 89 123456789 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 a r/w a interrupt request interrupt request user processing 3. clear iric 4. write to icdr 6. clear iric 7. write to icdr iric figure 13.8 operation timing in slave transmit mode (mls = wait = ack = 0) 302 13.3.5 slave receive operation in slave receive mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. the receive procedure and operations in slave receive mode are described below. see also figure 13.9. 1. set bits mls and wait in icmr and bits mst, trs, and ack in iccr according to the operating mode. set bit ice in iccr to 1, establishing slave receive mode. 2. a start condition output by the master device sets bbsy to 1 in icsr. 3. after the slave device detects the start condition, if the first byte matches its slave address, at the ninth clock pulse the slave device drives sda low to acknowledge the transfer. at the same time, iric is set to 1 in icsr. if ieic is 1 in iccr, a cpu interrupt is requested. the slave device holds scl low from the fall of the receive clock until it has read the data in icdr. 4. software clears iric to 0 in icsr. 5. when icdr is read, receiving of the next data starts. steps 4 and 5 can be repeated to receive data continuously. when a stop condition is detected (a low-to-high transition of sda while scl is high), bbsy is cleared to 0 in icsr. start condition scl (master output) scl (slave output) sda (master output sda (slave output) iric a bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 interrupt request 4. clear iric 5. read icdr user processing 1 9 8 7 6 5 4 3 2 1 figure 13.9 operation timing in slave receive mode (mls = wait = ack = ackb = 0) 303 13.3.6 iric set timing and scl control the interrupt request flag (iric) is set at different times depending on the wait bit in icmr and ack bit in iccr. scl is automatically held low after one frame has been transferred; this timing is synchronized with the internal clock. figure 13.10 shows the iric set timing and scl control. (a) when wait = 0 and ack = 0 scl sda iric user processing clear iric write to icdr (transmit) or read icdr (receive) 1 a 8 7 (b) when wait = 1 and ack = 0 scl sda iric user processing clear iric write to icdr (transmit) or read icdr (receive) note: the icdr write (transmit) or read (receive) following the clearing of iric should be executed after the rise of scl (ninth clock pulse). scl sda iric user processing (c) when ack = 1 clear iric write to icdr (transmit) or read icdr (receive) a 8 71 8 7 1 figure 13.10 iric set timing and scl control 304 13.3.7 noise canceler the logic levels at the scl and sda pins are routed through noise cancelers before being latched internally. figure 13.11 shows a block diagram of the noise canceler. the noise canceler consists of two cascaded latches and a match detector. the scl (or sda) input signal is sampled on the system clock, but is not passed forward to the next circuit unless the outputs of both latches agree. if they do not agree, the previous value is held. t sampling clock c dq latch c dq latch scl or sda input signal match detector internal scl or sda signal sampling clock t: s y stem clock figure 13.11 block diagram of noise canceler 305 13.3.8 sample flowcharts figures 13.12 to 13.15 show typical flowcharts for using the i 2 c bus interface in each mode. 1 2 3 4 5 6 7 8 9 10 start initialize read bbsy in icsr no bbsy = 0? yes set mst = 1 and trs = 1 in iccr write bbsy = 1 and scp = 0 in icsr write transmit data in icdr read iric in icsr no yes iric = 1? clear iric in icsr read ackb in icsr ackb = 0? no yes no yes transmit mode? write transmit data in icdr read iric in icsr iric = 1? no yes clear iric in icsr read ackb in icsr end of transmission (ackb = 1)? no yes write bbsy = 0 and scp = 0 in icsr end master receive mode 1. test the status of the scl and sda lines. 2. select master transmit mode. 3. generate a start condition. 4. set transmit data for the first byte (slave address + r/w). 5. wait for 1 byte to be transmitted. 6. test for acknowledgement by the designated slave device. 7. set transmit data for the second and subsequent bytes. 8. wait for 1 byte to be transmitted. 9. test for end of transfer. 10. generate a stop condition. figure 13.12 flowchart for master transmit mode (example) 306 master receive mode set trs = 0 in iccr set ackb = 0 in icsr last receive? read icdr read iric in icsr clear iric in icsr iric = 1? yes no no yes set ackb = 1 in icsr read icdr read iric in icsr iric = 1? clear iric in icsr set trs = 1 in iccr read icdr write bbsy = 0 and scp = 0 in icsr end 1 2 3 4 5 6 7 8 9 10 yes no 1. select receive mode. 2. set acknowledgement data. 3. start receiving. the first read is a dummy read. 4. wait for 1 byte to be received. 5. set acknowledgement data for the last receive. 6. start the last receive. 7. wait for 1 byte to be received. 8. select transmit mode. 9. read the last receive data (if icdr is read without selecting transmit mode, receive operations will resume). 10. generate a stop condition. figure 13.13 flowchart for master receive mode (example) 307 slave transmit mode write transmit data in icdr read iric in icsr iric = 1? clear iric in icsr read ackb in icsr write trs = 0 in iccr end of transmission (ackb = 1)? yes no no yes end 1 2 3 read icdr 5 4 1. set transmit data for the second and subsequent bytes. 2. wait for 1 byte to be transmitted. 3. test for end of transfer. 4. select slave receive mode. 5. dummy read (to release the scl line). figure 13.14 flowchart for slave transmit mode (example) 308 start initialize set mst = 0 and trs = 0 in iccr write ackb = 0 in icsr read iric in icsr iric = 1? yes no clear iric in icsr read aas and adz in icsr aas = 1 and adz = 0? read trs in iccr trs = 0? no yes no yes yes no yes yes no no 1 2 3 4 5 6 7 8 last receive? read icdr read iric in icsr iric = 1? clear iric in icsr set ackb = 1 in icsr read icdr read iric in icsr clear iric in icsr iric = 1? read icdr end general call address processing * description omitted slave transmit mode 1. select slave receive mode. 2. wait for the first byte to be received. 3. start receiving. the first read is a dummy read. 4. wait for the transfer to end. 5. set acknowledgement data for the last receive. 6. start the last receive. 7. wait for the transfer to end. 8. read the last receive data. figure 13.15 flowchart for slave receive mode (example) 309 13.4 application notes 1. in master mode, if an instruction to generate a start condition is immediately followed by an instruction to generate a stop condition, neither condition will be output correctly. to output consecutive start and stop conditions, after issuing the instruction that generates the start condition, read the relevant ports, check that scl and sda are both low, then issue the instruction that generates the stop condition. 2. either of the following two conditions will start the next transfer. pay attention to these conditions when reading or writing to icdr. ? write access to icdr when ice = 1 and trs = 1 ? read access to icdr when ice = 1 and trs = 0 3. the i 2 c bus interface specification for the scl rise time tsr is under 1000 ns (300 ns for high- speed mode). in master mode, the i 2 c bus interface monitors the scl line and synchronizes one bit at a time during communication. if tsr (the time for scl to go from low to v ih ) exceeds the time determined by the input clock of the i 2 c bus interface, the high period of scl is extended. scl rise time is determined by the pull-up resistance and load capacitance of the scl line. to insure proper operation at the set transfer rate, adjust the pull-up resistance and load capacitance so that the scl rise time falls below the values given in the table below. t cyc time display ckdbl iicx display ?= 5 mhz ?= 8 mhz ?= 10 mhz ?= 16 mhz 0 0 7.5t cyc normal mode 1000 ns 937 ns 750 ns 486 ns high-speed mode 300 ns 300 ns 300 ns 300 ns 0 1 17.5t cyc normal mode 1000 ns 1000 ns 1000 ns 1000 ns 1 0 high-speed mode 300 ns 300 ns 300 ns 300 ns 1 1 37.5t cyc normal mode 1000 ns 1000 ns 1000 ns 1000 ns high-speed mode 300 ns 300 ns 300 ns 300 ns 4. note on issuance of retransmission start condition when issuing a retransmission start condition, the condition must be issued after the scl clock falls during the acknowledge bit reception period. after the end of the acknowledge bit, the next data should be written to icdr after scl goes high. figure 13.16 shows the recommended program flow for issuing a retransmission start condition. a timing chart for the flowchart in figure 13.16 is shown in figure 13.17. 310 iric = 1? read iric in icsr clear iric in icsr retransmission? read scl scl = 0? write 1 to bbsy and 0 to scp in icsr read scl write data to icdr other operation no no yes yes scl = 1? no yes (1) confirm completion of 1- byte transmission (2) confirm that scl is low (3) issue retransmission start condition (4) confirm that scl is high (5) write transmit data note: read scl means reading dr for the scl pin. figure 13.16 recommended program flow for retransmission start condition issuance scl sda iric (1) iric check (2) scl low level determination (4) scl high level determination (5) transmit data setting (3) retransmission start condition issuance 9 ack bit 7 figure 13.17 timing chart for retransmission start condition issuance 311 5. note on issuance of stop condition if the rise of scl is weakened by external pull-up resistance r and bus load capacitance c in master mode, or if scl is pulled to the low level by a slave device, the timing at which scl is lowered by the internal bit synchronization circuit may be delayed by 1t scl. if, in this case, scl is identified as being low at the bit synchronization circuit sampling timing, and a stop condition issuing instruction is executed before the reference scl clock next falls, as in figure 13.18, sda will change from high to low to high while scl remains high. as a result, a stop condition will be issued before the end of the 9th clock. 9 9 bit synchronization circuit sampling timing v ih v ih normal operation erroneous operation scl output sda output scl output sda output normal operation erroneous operation reference clock scl sda iric bus line stop condition issuing instruction execution timing 9th clock not ended stop condition stop condition high interval secured scl identified as low figure 13.18 stop condition erroneous operation timing 312 6. countermeasure figure 13.19 shows the recommended program flow. iric = 1? read iric in icsr read ackb in icsr ackb = 1? read scl scl = 0? write 0 to bbsy and 0 to scp in icsr transmit data present? write data to icdr yes yes no no yes no yes no figure 13.19 recommended program flow 7. additional note when switching from master receive mode to master transmit mode, ensure that trs is set to 1 before the last receive data is latched by reading icdr. 8. precautions when clearing the iric flag when using the wait function if the scl rise time exceeds the specified duration when using the wait function in the i 2 c bus interface? master mode, or if there is a slave device that keeps scl low and applies a wait state, read scl and clear the iric flag only after determining that scl has gone low, as shown below. if the iric flag is cleared to 0 when wait is set to 1 and while the scl high level duration is being extended, the sda value may change before scl falls, erroneously resulting in a start or stop condition. 313 scl vih sda iric iric cleared scl determined to be low level scl low level detected scl high level duration maintained figure 13.20 iric flag clear timing when wait = 1 note that the clock may not be output properly during the next master send if receive data (icdr data) is read during the time between when the instruction to issue a stop condition is executed (writing 0 to bbsy and scp in issr) and when the stop condition is actually generated. in addition, overwriting of iic control bits in order to change the send or receive operation mode or to change settings, such as for example clearing the mst bit after completion of master send or receive, should always be performed during the period indicated as (a) in figure 13.21 below (after confirming that the bbsy bit in the iccr register has been cleared to 0). master receive mode icdr read f prohibited duration bbsy bit internal clock scl sda a 89 (a) bit 0 stop condition start condition execution of issue stop condition instruction (bbsy = 0 and scp = 0 written) stop condition generated (bbsy = 0 read) start condition issued figure 13.21 precautions when reading master receive data 314 315 section 14 host interface (h8/3337 series only) 14.1 overview the h8/3337 series has an on-chip host interface (hif) that provides a dual-channel parallel interface between the on-chip cpu and a host processor. the host interface is available only when the hie bit is set to 1 in syscr. this mode is called slave mode, because it is designed for a master-slave communication system in which the h8/3337-series chip is slaved to a host processor. the host interface consists of four 1-byte data registers, two 1-byte status registers, a 1-byte control register, fast a 20 gate logic, and a host interrupt request circuit. communication is carried out via five control signals from the host processor ( cs 1 , cs 2 or ecs 2 , ha 0 , ior , and iow or eiow ), four output signals to the host processor (ga 20 , hirq 1 , hirq 11 , and hirq 12 ), and an 8- bit bidirectional command/data bus (hdb 7 to hdb 0 ). the cs 1 and cs 2 (or ecs 2 ) signals select one of the two interface channels. note: if one of the two interface channels will not be used, tie the unused cs pin to v cc . for example, if interface channel 1 (idr1, odr1, str1) is not used, tie cs 1 to v cc . 316 14.1.1 block diagram figure 14.1 is a block diagram of the host interface. (internal interrupt signals) ibf2 ibf1 control logic hdb 7 ?db 0 idr1 odr1 str1 idr2 odr2 str2 hicr module data bus host data bus host interrupt request fast a 20 gate control port 4 port 8 internal data bus bus interface cs 1 ecs 2 /cs 2 ior eiow / iow ha 0 hirq 1 hirq 11 hirq 12 ga 20 legend: idr1: idr2: odr1: odr2: str1: str2: hicr: input data register 1 input data register 2 output data register 1 output data register 2 status register 1 status register 2 host interface control re g ister figure 14.1 host interface block diagram 317 14.1.2 input and output pins table 14.1 lists the input and output pins of the host interface module. table 14.1 hif input/output pins name abbreviation port i/o function i/o read ior p8 3 input host interface read signal i/o write * iow p8 4 input host interface write signal eiow p9 1 chip select 1 cs 1 p8 2 input host interface chip select signal for idr1, odr1, str1 chip select 2 * cs 2 p8 5 input host interface chip select signal for ecs 2 p9 0 idr2, odr2, str2 command/data ha 0 p8 0 input host interface address select signal in host read access, this signal selects the status registers (str1, str2) or data registers (odr1, odr2). in host write access to the data registers (idr1, idr2), this signal indicates whether the host is writing a command or data. data bus hdb 7 ?db 0 p3 7 ?3 0 i/o host interface data bus (single-chip mode) host interrupt 1 hirq 1 p4 4 output host interrupt output 1 to host host interrupt 11 hirq 11 p4 3 output host interrupt output 11 to host host interrupt 12 hirq 12 p4 5 output host interrupt output 12 to host gate a 20 ga 20 p8 1 output a 20 gate control signal output note: * selection between iow and eiow , and between cs 2 and ecs 2 , is by the stac bit in stcr. iow and cs 2 are used when stac is 0. eiow and ecs 2 are used when stac is 1. in this manual, both are referred to as iow and cs 2 . 318 14.1.3 register configuration table 14.2 lists the host interface registers. table 14.2 hif registers r/w initial slave master address * 4 name abbreviation slave host value address * 3 cs 1 cs 2 ha 0 system control register syscr r/w * 1 h'09 h'ffc4 host interface control register hicr r/w h'f8 h'fff0 input data register 1 idr1 r w h'fff4 0 1 0/1 * 5 output data register 1 odr1 r/w r h'fff5 0 1 0 status register 1 str1 r/(w) * 2 r h'00 h'fff6 0 1 1 input data register 2 idr2 r w h'fffc 1 0 0/1 * 5 output data register 2 odr2 r/w r h'fffd 1 0 0 status register 2 str2 r/(w) * 2 r h'00 h'fffe 1 0 1 serial/timer control register stcr r/w h'00 h'ffc3 notes: * 1 bit 3 is a read-only bit. * 2 the user-defined bits (bits 7 to 4 and 2) are read/write accessible from the slave processor. * 3 address when accessed from the slave processor. * 4 pin inputs used in access from the host processor. * 5 the ha 0 input discriminates between writing of commands and data. 319 14.2 register descriptions 14.2.1 system control register (syscr) bit 76543210 ssby sts2 sts1 sts0 xrst nmieg hie rame initial value 0 0 0 0 1 0 0 1 read/write r/w r/w r/w r/w r r/w r/w r/w syscr is an 8-bit read/write register which controls chip operations. host interface functions are enabled or disabled by the hie bit of syscr. see section 3.2, system control register (syscr), for information on other syscr bits. syscr is initialized to h'09 by an external reset and in hardware standby mode. bit 1?ost interface enable bit (hie): enables or disables the host interface in single-chip mode. when enabled, the host interface handles host-slave data transfers, operating in slave mode. bit 1: hie description 0 the host interface is disabled (initial value) 1 the host interface is enabled (slave mode) 14.2.2 host interface control register (hicr) bit 76543210 ibfie2 ibfie1 fga20e initial value 1 1 1 1 1 0 0 0 slave read/write r/w r/w r/w host read/write hicr is an 8-bit read/write register which controls host interface interrupts and the fast a 20 gate function. hicr is initialized to h'f8 by a reset and in hardware standby mode. bits 7 to 3?eserved: these bits cannot be modified and are always read as 1. 320 bit 2?nput buffer full interrupt enable 2 (ibfie2): enables or disables the ibf2 interrupt to the slave cpu. bit 2: ibfie2 description 0 idr2 input buffer full interrupt is disabled (initial value) 1 idr2 input buffer full interrupt is enabled bit 1?input buffer full interrupt enable 1 (ibfie1): enables or disables the ibf1 interrupt to the slave cpu. bit 1: ibfie1 description 0 idr1 input buffer full interrupt is disabled (initial value) 1 idr1 input buffer full interrupt is enabled bit 0?ast gate a 20 enable (fga20e): enables or disables the fast a 20 gate function. when the fast a 20 gate is disabled, a regular-speed a 20 gate signal can be implemented by using software to manipulate the p8 1 output. bit 0: fga20e description 0 disables fast a 20 gate function (initial value) 1 enables fast a 20 gate function 14.2.3 input data register 1 (idr1) bit 76543210 idr7 idr6 idr5 idr4 idr3 idr2 idr1 idr0 initial value slave read/write r r r r r r r r host read/write w w w w w w w w idr1 is an 8-bit read-only register to the slave processor, and an 8-bit write-only register to the host processor. when cs 1 is low, information on the host data bus is written into idr1 at the rising edge of iow . the ha 0 state is also latched into the c/ d bit in str1 to indicate whether the written information is a command or data. the initial values of idr1 after a reset or standby are undetermined. 321 14.2.4 output data register 1 (odr1) bit 76543210 odr7 odr6 odr5 odr4 odr3 odr2 odr1 odr0 initial value slave read/write r/w r/w r/w r/w r/w r/w r/w r/w host read/write r r r r r r r r odr1 is an 8-bit read/write register to the slave processor, and an 8-bit read-only register to the host processor. the odr1 contents are output on the host data bus when ha 0 is low, cs 1 is low, and ior is low. the initial values of odr1 after a reset or standby are undetermined. 14.2.5 status register 1 (str1) bit 76543210 dbu dbu dbu dbu c/ d dbu ibf obf initial value 0 0 0 0 0 0 0 0 slave read/write r/w r/w r/w r/w r r/w r r host read/write r r r r r r r r str1 is an 8-bit register that indicates status information during host interface processing. bits 3, 1, and 0 are read-only bits to both the host and slave processors. str1 is initialized to h'00 by a reset and in hardware standby mode. bits 7 to 4 and bit 2?efined by user (dbu): the user can use these bits as necessary. bit 3?ommand/data (c/ d ): receives the ha 0 input when the host processor writes to idr1, and indicates whether idr1 contains data or a command. bit 3: c/ d description 0 contents of idr1 are data (initial value) 1 contents of idr1 are a command 322 bit 1?nput buffer full (ibf): set to 1 when the host processor writes to idr1. this bit is an internal interrupt source to the slave processor. ibf is cleared to 0 when the slave processor reads idr1. bit 1: ibf description 0 this bit is cleared when the slave processor reads idr1 (initial value) 1 this bit is set when the host processor writes to idr1 bit 0?utput buffer full (obf): set to 1 when the slave processor writes to odr1. cleared to 0 when the host processor reads odr1. bit 0: obf description 0 this bit is cleared when the host processor reads odr1 (initial value) 1 this bit is set when the slave processor writes to odr1 table 14.3 shows the conditions for setting and clearing the str1 flags. table 14.3 set/clear timing for str1 flags flag setting condition clearing condition c/ d rising edge of host? write signal ( iow ) when ha 0 is high rising edge of host? write signal ( iow ) when ha 0 is low ibf rising edge of host? write signal ( iow ) when writing to idr1 falling edge of slave? internal read signal ( rd ) when reading idr1 obf falling edge of slave? internal write signal ( wr ) when writing to odr1 rising edge of host? read signal ( ior ) when reading odr1 14.2.6 input data register 2 (idr2) bit 76543210 idr7 idr6 idr5 idr4 idr3 idr2 idr1 idr0 initial value slave read/write r r r r r r r r host read/write w w w w w w w w idr2 is an 8-bit read-only register to the slave processor, and an 8-bit write-only register to the host processor. when cs 2 is low, information on the host data bus is written into idr2 at the rising edge of iow . the ha 0 state is also latched into the c/ d bit in str2 to indicate whether the written information is a command or data. the initial values of idr2 after a reset or standby are undetermined. 323 14.2.7 output data register 2 (odr2) bit 76543210 odr7 odr6 odr5 odr4 odr3 odr2 odr1 odr0 initial value slave read/write r/w r/w r/w r/w r/w r/w r/w r/w host read/write r r r r r r r r odr2 is an 8-bit read/write register to the slave processor, and an 8-bit read-only register to the host processor. the odr2 contents are output on the host data bus when ha 0 is low, cs 2 is low, and ior is low. the initial values of odr2 after a reset or standby are undetermined. 14.2.8 status register 2 (str2) bit 76543210 dbu dbu dbu dbu c/ d dbu ibf obf initial value 0 0 0 0 0 0 0 0 slave read/write r/w r/w r/w r/w r r/w r r host read/write r r r r r r r r str2 is an 8-bit register that indicates status information during host interface processing. bits 3, 1, and 0 are read-only bits to both the host and slave processors. str2 is initialized to h'00 by a reset and in hardware standby mode. bits 7 to 4 and bit 2?efined by user (dbu): the user can use these bits as necessary. bit 3?ommand/data (c/ d ): receives the ha 0 input when the host processor writes to idr2, and indicates whether idr2 contains data or a command. bit 3: c/ d description 0 contents of idr2 are data (initial value) 1 contents of idr2 are a command 324 bit 1?nput buffer full (ibf): set to 1 when the host processor writes to idr2. this bit is an internal interrupt source to the slave processor. ibf is cleared to 0 when the slave processor reads idr2. bit 1: ibf description 0 this bit is cleared when the slave processor reads idr2 (initial value) 1 this bit is set when the host processor writes to idr2 bit 0?utput buffer full (obf): set to 1 when the slave processor writes to odr2. cleared to 0 when the host processor reads odr2. bit 0: obf description 0 this bit is cleared when the host processor reads odr2 (initial value) 1 this bit is set when the slave processor writes to odr2 table 14.4 shows the conditions for setting and clearing the str2 flags. table 14.4 set/clear timing for str2 flags flag setting condition clearing condition c/ d rising edge of host? write signal ( iow ) when ha 0 is high rising edge of host? write signal ( iow ) when ha 0 is low ibf rising edge of host? write signal ( iow ) when writing to idr2 falling edge of slave? internal read signal ( rd ) when reading idr2 obf falling edge of slave? internal write signal ( wr ) when writing to odr2 rising edge of host? read signal ( ior ) when reading odr2 325 14.2.9 serial/timer control register (stcr) bit 76543210 iics iicd iicx iice stac mpe icks1 icks0 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w stcr is an 8-bit readable/writable register that controls the i 2 c bus interface and host interface and the sci operating mode, and selects the tcnt clock source. stcr is initialized to h'00 by a reset and in hardware standby mode. bits 7 to 4? 2 c control (iics, iicd, iicx, iice): these bits are used to control the i 2 c bus interface. for details, see section 13, i 2 c bus interface. bit 3?lave input switch (stac): controls switching of host interface input pins. settings of this bit are valid only when the host interface is enabled (slave mode). bit 3: stac description 0 in port 8, p8 5 switches over to cs 2 , and p8 4 to iow (initial value) 1 in port 9, p9 1 switches over to eiow , and p9 0 to ecs 2 bit 2?ultiprocessor enable (mpe): controls the operating mode of sci0 and sci1. for details, see section 12, serial communication interface. bits 1 and 0?nternal clock source select 1 and 0 (icks1, icsk0): together with bits cks2 to cks0 in tcr, these bits select timer counter clock inputs. for details, see section 9, 8-bit timers. 326 14.3 operation 14.3.1 host interface operation the host interface is activated by setting the hie bit (bit 1) to 1 in syscr, establishing slave mode. activation of the host interface (entry to slave mode) appropriates the related i/o lines in port 3 or b (data), port 8 or 9 (control) and port 4 (host interrupt requests) for interface use. for host interface read/write timing diagrams, see section 23.3.8, host interface timing. 14.3.2 control states table 14.5 indicates the slave operations carried out in response to host interface signals from the host processor. table 14.5 host interface operation cs 2 cs 1 ior iow ha 0 slave operation 10000 prohibited 1 prohibited 1 0 data read from output data register 1 (odr1) 1 status read from status register 1 (str1) 1 0 0 data write to input data register 1 (idr1) 1 command write to input data register 1 (idr1) 1 0 idle state 1 idle state 01000 prohibited 1 prohibited 1 0 data read from output data register 2 (odr2) 1 status read from status register 2 (str2) 1 0 0 data write to input data register 2 (idr2) 1 command write to input data register 2 (idr2) 1 0 idle state 1 idle state 327 14.3.3 a 20 gate the a 20 gate signal can mask address a 20 to emulate an addressing mode used by personal computers with an 8086*-family cpu. in slave mode, a regular-speed a 20 gate signal can be output under software control, or a fast a 20 gate signal can be output under hardware control. fast a 20 gate output is enabled by setting the fga20e bit (bit 0) to 1 in hicr (h'fff0). note: * intel microprocessor. regular a 20 gate operation: output of the a 20 gate signal can be controlled by an h'd1 command followed by data. when the slave processor receives data, it normally uses an interrupt routine activated by the ibf1 interrupt to read idr1. if the data follows an h'd1 command, software copies bit 1 of the data and outputs it at the gate a 20 pin (p8 1 /ga 20 ). fast a 20 gate operation: when the fga20e bit is set to 1, p8 1 /ga 20 is used for output of a fast a 20 gate signal. bit p8 1 ddr must be set to 1 to assign this pin for output. the initial output from this pin will be a logic 1, which is the initial dr value. afterward, the host processor can manipulate the output from this pin by sending commands and data. this function is available only when register idr1 is accessed using cs 1 . slave logic decodes the commands input from the host processor. when an h'd1 host command is detected, bit 1 of the data following the host command is output from the ga 20 output pin. this operation does not depend on software or interrupts, and is faster than the regular processing using interrupts. table 14.6 lists the conditions that set and clear ga 20 (p8 1 ). figure 14.2 describes the ga 20 output in flowchart form. table 14.7 indicates the ga 20 output signal values. table 14.6 ga 20 (p8 1 ) set/clear timing pin name setting condition clearing condition ga20 (p8 1 ) rising edge of the host? write signal ( iow ) when bit 1 of the written data is 1 and the data follows an h'd1 host command rising edge of the host? write signal ( iow ) when bit 1 of the written data is 0 and the data follows an h'd1 host command 328 start host write h'd1 command received? wait for next byte host write yes data byte? write bit 1 of data byte to dr bit of p8 1 /ga 20 yes no no figure 14.2 ga 20 output 329 table 14.7 fast a 20 gate output signal ha 0 data/command internal cpu interrupt flag ga 20 (pb 1 ) remarks 1 d1 command 0 q turn-on sequence 0 1 data * 1 01 1 ff command 0 q (1) 1 d1 command 0 q turn-off sequence 0 0 data * 2 00 1 ff command 0 q (0) 1 d1 command 0 q short turn-on sequence 0 1 data * 1 01 1/0 command other than ff and d1 1 q (1) 1 d1 command 0 q short turn-off sequence 0 0 data * 2 00 1/0 command other than ff and d1 1 q (0) 1 d1 command 0 q cancelled sequence 1 command other than d1 1 q 1 d1 command 0 q retriggered sequence 1 d1 command 0 q 1 d1 command 0 q consecutively executed 0 any data 0 1/0 sequences 1 d1 command 0 q (1/0) notes: * 1 arbitrary data with bit 1 set to 1. * 2 arbitrary data with bit 1 cleared to 0. 330 14.4 interrupts 14.4.1 ibf1, ibf2 the host interface can request two types of interrupts to the slave cpu: ibf1 and ibf2. they are input buffer full interrupts for input data registers idr1 and idr2 respectively. each interrupt is enabled when the corresponding enable bit is set (table 14.8). table 14.8 input buffer full interrupts interrupt description ibf1 requested when ibfie1 is set to 1 and idr1 is full ibf2 requested when ibfie2 is set to 1 and idr2 is full 14.4.2 hirq 11 , hirq 1 , and hirq 12 in slave mode (when hie = 1 in syscr in single-chip mode), three bits in the port 4 data register (p4dr) can be used as host interrupt request latches. these three p4dr bits are cleared to 0 by the host processor? read signal ( ior ). if cs 1 and ha 0 are low, when ior goes low and the host reads odr1, hirq 1 and hirq 12 are cleared to 0. if cs 2 and ha 0 are low, when ior goes low and the host reads odr2, hirq 11 is cleared to 0. to generate a host interrupt request, normally on-chip software writes 1 to the corresponding bit. in processing the interrupt, the host? interrupt-handling routine reads the output data register (odr1 or odr2), and this clears the host interrupt latch to 0. table 14.9 indicates how these bits are set and cleared. figure 14.3 shows the processing in flowchart form. table 14.9 host interrupt signal set/clear conditions host interrupt signal setting condition clearing condition hirq 11 (p4 3 ) slave cpu reads 0 from p4dr bit 3, then writes 1 slave cpu writes 0 in p4dr bit 3, or host reads output data register 2 hirq 1 (p4 4 ) slave cpu reads 0 from p4dr bit 4, then writes 1 slave cpu writes 0 in p4dr bit 4, or host reads output data register 1 hirq 12 (p4 5 ) slave cpu reads 0 from p4dr bit 5, then writes 1 slave cpu writes 0 in p4dr bit 5, or host reads output data register 1 331 slave cpu master cpu write to odr write 1 to p4dr p4dr = 0? yes no no yes all bytes transferred? hirq output high hirq output low interrupt initiation odr read hardware operations software operations figure 14.3 hirq output flowchart 14.5 application note the host interface provides buffering of asynchronous data from the host and slave processors, but an interface protocol must be followed to implement necessary functions and avoid data contention. for example, if the host and slave processors try to access the same input or output data register simultaneously, the data will be corrupted. interrupts can be used to design a simple and effective protocol. 332 333 section 15 a/d converter 15.1 overview the h8/3337series and h8/3397 series include a 10-bit successive-approximations a/d converter with a selection of up to eight analog input channels. 15.1.1 features a/d converter features are listed below. ? 10-bit resolution ? eight input channels ? high-speed conversion conversion time: minimum 8.4 s per channel (with 16-mhz system clock) ? two conversion modes single mode: a/d conversion of one channel scan mode: continuous conversion on one to four channels ? four 16-bit data registers a/d conversion results are transferred for storage into data registers corresponding to the channels. ? sample-and-hold function ? a/d conversion can be externally triggered ? a/d interrupt requested at end of conversion at the end of a/d conversion, an a/d end interrupt (adi) can be requested. 334 15.1.2 block diagram figure 15.1 shows a block diagram of the a/d converter. module data bus bus interface internal data bus addra addrb addrc addrd adcsr adcr successive- approximations register 10-bit d/a av cc analog multi- plexer an an an an an an an an 0 1 2 3 4 5 6 7 sample-and- hold circuit comparator + control circuit adtrg ?/8 ?/16 adi interrupt signal legend: adcr: adcsr: addra: addrb: addrc: addrd: a/d control register a/d control/status register a/d data register a a/d data register b a/d data register c a/d data register d av ss figure 15.1 a/d converter block diagram 335 15.1.3 input pins table 15.1 lists the a/d converter? input pins. the eight analog input pins are divided into two groups: group 0 (an 0 to an 3 ), and group 1 (an 4 to an 7 ). av cc and av ss are the power supply for the analog circuits in the a/d converter. table 15.1 a/d converter pins pin name abbreviation i/o function analog power supply pin av cc input analog power supply analog ground pin av ss input analog ground and reference voltage analog input pin 0 an 0 input group 0 analog inputs analog input pin 1 an 1 input analog input pin 2 an 2 input analog input pin 3 an 3 input analog input pin 4 an 4 input group 1 analog inputs analog input pin 5 an 5 input analog input pin 6 an 6 input analog input pin 7 an 7 input a/d external trigger input pin adtrg input external trigger input for starting a/d conversion 336 15.1.4 register configuration table 15.2 summarizes the a/d converter? registers. table 15.2 a/d converter registers name abbreviation r/w initial value address a/d data register a (high) addrah r h'00 h'ffe0 a/d data register a (low) addral r h'00 h'ffe1 a/d data register b (high) addrbh r h'00 h'ffe2 a/d data register b (low) addrbl r h'00 h'ffe3 a/d data register c (high) addrch r h'00 h'ffe4 a/d data register c (low) addrcl r h'00 h'ffe5 a/d data register d (high) addrdh r h'00 h'ffe6 a/d data register d (low) addrdl r h'00 h'ffe7 a/d control/status register adcsr r/w * h'00 h'ffe8 a/d control register adcr r/w h'7f h'ffe9 note: * only 0 can be written in bit 7, to clear the flag. 337 15.2 register descriptions 15.2.1 a/d data registers a to d (addra to addrd) bit 1514131211109876543210 addrn ad9 ad8 ad6 ad5 ad4 ad3 ad2 ad1 ad0 initial value 0 0 0 0000000000000 read/write r r r rrrrrrrrrrrrr (n = a to d) the four a/d data registers (addra to addrd) are 16-bit read-only registers that store the results of a/d conversion. an a/d conversion produces 10-bit data, which is transferred for storage into the a/d data register corresponding to the selected channel. the upper 8 bits of the result are stored in the upper byte of the a/d data register. the lower 2 bits are stored in the lower byte. bits 5 to 0 of an a/d data register are reserved bits that always read 0. table 15.3 indicates the pairings of analog input channels and a/d data registers. the cpu can always read and write the a/d data registers. the upper byte can be read directly, but the lower byte is read through a temporary register (temp). for details see section 15.3, cpu interface. the a/d data registers are initialized to h'0000 by a reset and in standby mode. table 15.3 analog input channels and a/d data registers analog input channel group 0 group 1 a/d data register an 0 an 4 addra an 1 an 5 addrb an 2 an 6 addrc an 3 an 7 addrd 338 15.2.2 a/d control/status register (adcsr) bit 76543210 adf adie adst scan cks ch2 ch1 ch0 initial value 0 0 0 0 0 0 0 0 read/write r/(w) * r/w r/w r/w r/w r/w r/w r/w note: * only 0 can be written, to clear the flag. adcsr is an 8-bit readable/writable register that selects the mode and controls the a/d converter. adcsr is initialized to h'00 by a reset and in standby mode. bit 7?/d end flag (adf): indicates the end of a/d conversion. bit 7: adf description 0 clearing condition: (initial value) cleared by reading adf while adf = 1, then writing 0 in adf 1 setting conditions: ? single mode: a/d conversion ends ? scan mode: a/d conversion ends in all selected channels bit 6?/d interrupt enable (adie): enables or disables the interrupt (adi) requested at the end of a/d conversion. bit 6: adie description 0 a/d end interrupt request (adi) is disabled (initial value) 1 a/d end interrupt request (adi) is enabled bit 5?/d start (adst): starts or stops a/d conversion. the adst bit remains set to 1 during a/d conversion. it can also be set to 1 by external trigger input at the adtrg pin. bit 5: adst description 0 a/d conversion is stopped (initial value) 1 ? single mode: a/d conversion starts; adst is automatically cleared to 0 when conversion ends ? scan mode: a/d conversion starts and continues, cycling among the selected channels, until adst is cleared to 0 by software, by a reset, or by a transition to standby mode 339 bit 4?can mode (scan): selects single mode or scan mode. for further information on operation in these modes, see section 15.4, operation. clear the adst bit to 0 before switching the conversion mode. bit 4: scan description 0 single mode (initial value) 1 scan mode bit 3?lock select (cks): selects the a/d conversion time. when p = ?2, the conversion time doubles. clear the adst bit to 0 before switching the conversion time. bit 3: cks description 0 conversion time = 266 states (maximum) (when p = ? (initial value) 1 conversion time = 134 states (maximum) (when p = ? bits 2 to 0?hannel select 2 to 0 (ch2 to ch0): these bits and the scan bit select the analog input channels. clear the adst bit to 0 before changing the channel selection. group selection channel selection description ch2 ch1 ch0 single mode scan mode 000an 0 (initial value) an 0 1an 1 an 0 , an 1 10 an 2 an 0 to an 2 1an 3 an 0 to an 3 100an 4 an 4 1an 5 an 4 , an 5 10 an 6 an 4 to an 6 1an 7 an 4 to an 7 340 15.2.3 a/d control register (adcr) bit 76543210 trge initial value 0 1 1 1 1 1 1 1 read/write r/w adcr is an 8-bit readable/writable register that enables or disables external triggering of a/d conversion. adcr is initialized to h'7f by a reset and in standby mode. bit 7?rigger enable (trge): enables or disables external triggering of a/d conversion. bit 7: trge description 0 a/d conversion cannot be externally triggered (initial value) 1 a/d conversion is enabled by the external trigger signal ( adtrg ) (a/d conversion can also be enabled by software) bits 6 to 0?eserved: these bits cannot be modified, and are always read as 1. 15.3 cpu interface addra to addrd are 16-bit registers, but they are connected to the cpu by an 8-bit data bus. therefore, although the upper byte can be be accessed directly by the cpu, the lower byte is read through an 8-bit temporary register (temp). an a/d data register is read as follows. when the upper byte is read, the upper-byte value is transferred directly to the cpu and the lower-byte value is transferred into temp. next, when the lower byte is read, the temp contents are transferred to the cpu. when reading an a/d data register, always read the upper byte before the lower byte. it is possible to read only the upper byte, but if only the lower byte is read, incorrect data may be obtained. figure 15.2 shows the data flow for access to an a/d data register. 341 upper-byte read bus interface module data bus cpu (h'aa) addrnh (h'aa) addrnl (h'40) lower-byte read bus interface module data bus cpu (h'40) addrnh (h'aa) addrnl (h'40) temp (h'40) temp (h'40) (n = a to d) (n = a to d) figure 15.2 a/d data register access operation (reading h'aa40) 342 15.4 operation the a/d converter operates by successive approximations with 10-bit resolution. it has two operating modes: single mode and scan mode. 15.4.1 single mode (scan = 0) single mode should be selected when only one a/d conversion on one channel is required. a/d conversion starts when the adst bit is set to 1 by software, or by external trigger input. the adst bit remains set to 1 during a/d conversion and is automatically cleared to 0 when conversion ends. when conversion ends the adf bit is set to 1. if the adie bit is also set to 1, an adi interrupt is requested at this time. to clear the adf flag to 0, first read adcsr, then write 0 in adf. when the mode or analog input channel must be switched during analog conversion, to prevent incorrect operation, first clear the adst bit to 0 in adcsr to halt a/d conversion. after making the necessary changes, set the adst bit to 1 to start a/d conversion again. the adst bit can be set at the same time as the mode or channel is changed. typical operations when channel 1 (an 1 ) is selected in single mode are described next. figure 15.3 shows a timing diagram for this example. 1. single mode is selected (scan = 0), input channel an 1 is selected (ch2 = ch1 = 0, ch0 = 1), the a/d interrupt is enabled (adie = 1), and a/d conversion is started (adst = 1). 2. when a/d conversion is completed, the result is transferred into addrb. at the same time the adf flag is set to 1, the adst bit is cleared to 0, and the a/d converter becomes idle. 3. since adf = 1 and adie = 1, an adi interrupt is requested. 4. the a/d interrupt handling routine starts. 5. the routine reads adcsr, then writes 0 in the adf flag. 6. the routine reads and processes the conversion result (addrb). 7. execution of the a/d interrupt handling routine ends. after that, if the adst bit is set to 1, a/d conversion starts again and steps 2 to 7 are repeated. 343 adie adst adf state of channel 0 (an ) set set set clear clear idle idle idle idle a/d conversion a/d conversion idle read conversion result a/d conversion result read conversion result a/d conversion result (2) note: vertical arrows ( ) indicate instructions executed by software. 0 1 2 3 a/d conversion starts * * * * * (2) (1) (1) * addra addrb addrc addrd state of channel 1 (an ) state of channel 2 (an ) state of channel 3 (an ) idle figure 15.3 example of a/d converter operation (single mode, channel 1 selected) 344 15.4.2 scan mode (scan = 1) scan mode is useful for monitoring analog inputs in a group of one or more channels. when the adst bit is set to 1 by software or external trigger input, a/d conversion starts on the first channel in the group (an 0 when ch2 = 0, an 4 when ch2 = 1). when two or more channels are selected, after conversion of the first channel ends, conversion of the second channel (an 1 or an 5 ) starts immediately. a/d conversion continues cyclically on the selected channels until the adst bit is cleared to 0. the conversion results are transferred for storage into the a/d data registers corresponding to the channels. when the mode or analog input channel selection must be changed during analog conversion, to prevent incorrect operation, first clear the adst bit to 0 in adcsr to halt a/d conversion. after making the necessary changes, set the adst bit to 1. a/d conversion will start again from the first channel in the group. the adst bit can be set at the same time as the mode or channel selection is changed. typical operations when three channels in group 0 (an 0 to an 2 ) are selected in scan mode are described next. figure 15.4 shows a timing diagram for this example. 1. scan mode is selected (scan = 1), scan group 0 is selected (ch2 = 0), analog input channels an 0 to an 2 are selected (ch1 = 1, ch0 = 0), and a/d conversion is started (adst = 1). 2. when a/d conversion of the first channel (an 0 ) is completed, the result is transferred into addra. next, conversion of the second channel (an 1 ) starts automatically. 3. conversion proceeds in the same way through the third channel (an 2 ). 4. when conversion of all selected channels (an 0 to an 2 ) is completed, the adf flag is set to 1 and conversion of the first channel (an 0 ) starts again. if the adie bit is set to 1, an adi interrupt is requested at this time. 5. steps 2 to 4 are repeated as long as the adst bit remains set to 1. when the adst bit is cleared to 0, a/d conversion stops. after that, if the adst bit is set to 1, a/d conversion starts again from the first channel (an 0 ). 345 adst adf state of channel 0 (an ) 0 1 2 3 continuous a/d conversion set clear * 1 clear * 1 idle a/d conversion idle idle idle a/d conversion idle a/d conversion idle a/d conversion idle a/d conversion idle idle transfer a/d conversion result a/d conversion result a/d conversion result a/d conversion result * 1 * 2 a/d conversion time notes: * 2 (1) (2) (4) (5) * 1 (3) (1) (4) (2) (3) addra addrb addrc addrd state of channel 1 (an ) state of channel 2 (an ) state of channel 3 (an ) vertical arrows ( ) indicate instructions executed by software. data currently being converted is ignored. figure 15.4 example of a/d converter operation (scan mode, channels an 0 to an 2 selected) 346 15.4.3 input sampling and a/d conversion time the a/d converter has a built-in sample-and-hold circuit. the a/d converter samples the analog input at a time t d after the adst bit is set to 1, then starts conversion. figure 15.5 shows the a/d conversion timing. table 15.4 indicates the a/d conversion time. as indicated in figure 15.5, the a/d conversion time includes t d and the input sampling time. the length of t d varies depending on the timing of the write access to adcsr. the total conversion time therefore varies within the ranges indicated in table 15.4. in scan mode, the values given in table 15.4 apply to the first conversion. in the second and subsequent conversions the conversion time is fixed at 256 states when cks = 0 or 128 states when cks = 1. (when p = ) address bus write signal input sampling timing adf (1) (2) t d t spl t conv legend: (1): (2): t : t : t : d spl conv adcsr write cycle adcsr address synchronization delay input sampling time a/d conversion time figure 15.5 a/d conversion timing 347 table 15.4 a/d conversion time (single mode) cks = 0 cks = 1 symbol min typ max min typ max synchronization delay t d 10 17 6 9 input sampling time * t spl 80 40 a/d conversion time * t conv 259 266 131 134 note: * values in the table are numbers of states. values are for p = . when p = /2, the values are doubled. 15.4.4 external trigger input timing a/d conversion can be externally triggered. when the trge bit is set to 1 in adcr, external trigger input is enabled at the adtrg adtrg adtrg figure 15.6 external trigger input timing 348 15.5 interrupts the a/d converter generates an interrupt (adi) at the end of a/d conversion. the adi interrupt request can be enabled or disabled by the adie bit in adcsr. 15.6 useage notes when using the a/d converter, note the following points: 15.6.1 setting ranges of analog power supply pins, etc. analog input voltage range: the voltage applied to analog input pins an n during a/d conversion should be in the range av ss av cc and av ss input voltages: for the av cc input voltage, set av ss = v ss . when the a/d converter is not used, set av cc = v cc and av ss = v ss . 15.6.2 notes on board design in board design, digital circuitry and analog circuitry should be as mutually isolated as possible, and layout in which digital circuit signal lines and analog circuit signal lines cross or are in close proximity should be avoided as far as possible. failure to do so may result in incorrect operation of the analog circuitry due to inductance, adversely affecting a/d conversion values. also, digital circuitry must be isolated from the analog input signals (an 0 to an 7 ), analog reference voltage (av ref ), and analog power supply (av cc ) by the analog ground (av ss ). the analog ground (av ss ) should be connected to a stable digital ground (v ss ) at one point on the board. 15.6.3 notes on noise a protection circuit should be connected between av cc and av ss as shown in figure 15.7 to prevent damage due to an abnormal voltage such as an excessive surge at the analog input pins (an 0 to an 7 ). also, the bypass capacitors connected to av cc and av ref and the filter capacitors connected to an 0 to an 7 must be connected to av ss . if filter capacitors are connected as shown in figure 15.7, the input currents at the analog input pins (an 0 to an 7 ) will be smoothed, which may give rise to error. error can also occur if a/d conversion is frequently performed in scan mode so that the current that charges and discharges the capacitor in the sample-and-hold circuit of the a/d converter becomes greater than that input 349 to the analog input pins via the input impedance (r in ). the circuit constants should therefore be selected carefully. av cc * 1 an 0 to an 7 av ss * 2 r in : input impedance r in * 2 100 ? figure 15.7 example of analog input pin protection circuit 15.6.4 a/d conversion accuracy definitions a/d conversion accuracy definitions for the h8/3397 series are given below. ? ? ? ? 350 ? ? figure 15.8 a/d conversion accuracy definitions (1) 351 fs offset error nonlinearity error actual a/d conversion characteristic analog input voltage digital output ideal a/d conversion characteristic full-scale error figure 15.9 a/d conversion accuracy definitions (2) 15.6.5 allowable signal-source impedance the analog inputs of the h8/3337 series and h8/3397 series are designed to assure accurate conversion of input signals with a signal-source impedance not exceeding 10 k ? ? ? 352 15.6.6 effect on absolute accuracy attaching an external capacitor creates a coupling with ground, so if there is noise on the ground line, it may degrade absolute accuracy. the capacitor must be connected to an electrically stable ground, such as av ss . if a filter circuit is used, be careful of interference with digital signals on the same board, and make sure the circuit does not act as an antenna. equivalent circuit of a/d converter h8/3337 series or h8/3397 series chip 20 pf c in = 15 pf 10 k ? ? figure 15.10 example of analog input circuit 353 section 16 d/a converter (h8/3337 series only) 16.1 overview the h8/3337 series has an on-chip d/a converter module with two channels. 16.1.1 features features of the d/a converter module are listed below. ? eight-bit resolution ? two-channel output ? maximum conversion time: 10 s (with 20-pf load capacitance) ? output voltage: 0 v to av cc 354 16.1.2 block diagram figure 16.1 shows a block diagram of the d/a converter. bus interface module data bus internal data bus 8-bit d/a dadr0 dadr1 dacr control circuit av da da av cc 0 1 ss dacr: dadr0: dadr1: d/a control register d/a data register 0 d/a data register 1 figure 16.1 d/a converter block diagram 355 16.1.3 input and output pins table 16.1 lists the input and output pins used by the d/a converter module. table 16.1 input and output pins of d/a converter module name abbreviation i/o function analog supply voltage av cc input power supply and reference voltage for analog circuits analog ground av ss input ground and reference voltage for analog circuits analog output 0 da 0 output analog output channel 0 analog output 1 da 1 output analog output channel 1 16.1.4 register configuration table 16.2 lists the three registers of the d/a converter module. table 16.2 d/a converter registers name abbreviation r/w initial value address d/a data register 0 dadr0 r/w h'00 h'fff8 d/a data register 1 dadr1 r/w h'00 h'fff9 d/a control register dacr r/w h'1f h'fffa 356 16.2 register descriptions 16.2.1 d/a data registers 0 and 1 (dadr0, dadr1) bit 76543210 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w d/a data registers 0 and 1 (dadr0 and dadr1) are 8-bit readable and writable registers that store data to be converted. when analog output is enabled, the value in the d/a data register is converted and output continuously at the analog output pin. the d/a data registers are initialized to h'00 at a reset and in the standby modes. 16.2.2 d/a control register (dacr) bit 76543210 daoe1 daoe0 dae initial value 0 0 0 1 1 1 1 1 read/write r/w r/w r/w dacr is an 8-bit readable and writable register that controls the operation of the d/a converter module. dacr is initialized to h'1f at a reset and in the standby modes. bit 7?/a output enable 1 (daoe1): controls analog output from the d/a converter. bit 7: daoe1 description 0 analog output at da 1 is disabled. 1 d/a conversion is enabled on channel 1. analog output is enabled at da 1 . 357 bit 6?/a output enable 0 (daoe0): controls analog output from the d/a converter. bit 6: daoe0 description 0 analog output at da 0 is disabled. 1 d/a conversion is enabled on channel 0. analog output is enabled at da 0 . bit 5?/a enable (dae): controls d/a conversion, in combination with bits daoe0 and daoe1. d/a conversion is controlled independently on channels 0 and 1 when dae = 0. channels 0 and 1 are controlled together when dae = 1. the decision to output the converted results is always controlled independently by daoe0 and daoe1. bit 7: daoe1 bit 6: daoe0 bit 5: dae description 0 0 disabled on channels 0 and 1. 1 0 enabled on channel 0. disabled on channel 1. 1 enabled on channels 0 and 1. 1 0 0 disabled on channel 0. enabled on channel 1. 1 enabled on channels 0 and 1. 1 enabled on channels 0 and 1. when the dae bit is set to 1, analog power supply current drain is the same as during a/d and d/a conversion, even if the daoe0 and daoe1 bits in dacr and the adst bit in adscr are cleared to 0. bits 4 to 0?eserved: these bits cannot be modified and are always read as 1. 358 16.3 operation the d/a converter module has two built-in d/a converter circuits that can operate independently. d/a conversion is performed continuously whenever enabled by the d/a control register. when a new value is written in dadr0 or dadr1, conversion of the new value begins immediately. the converted result is output by setting the daoe0 or daoe1 bit to 1. an example of conversion on channel 0 is given next. figure 16.2 shows the timing. 1. software writes the data to be converted in dadr0. 2. d/a conversion begins when the daoe0 bit in dacr is set to 1. after a conversion delay, analog output appears at the da0 pin. the output value is av cc (dadr0 value)/256. this output continues until a new value is written in dadr0 or the daoe0 bit is cleared to 0. 3. if a new value is written in dadr0, conversion begins immediately. output of the converted result begins after the conversion delay time. 4. when the daoe0 bit is cleared to 0, da0 becomes an input pin. dadr0 write cycle dacr write cycle dadr0 write cycle dacr write cycle address dadr0 daoe0 da0 conversion data (1) conversion data (2) high-impedance state conversion result (1) conversion result (2) t dconv t dconv t : d/a conversion time dconv figure 16.2 d/a conversion (example) 359 section 17 ram 17.1 overview the h8/3337y, h8/3336y, h8/3397, and h8/3396 have 2 kbytes of on-chip static ram. the h8/3334y and h8/3394 have 1 kbyte. the ram is connected to the cpu by a 16-bit data bus. both byte and word access to the on-chip ram are performed in two states, enabling rapid data transfer and instruction execution. the on-chip ram is assigned to addresses h'f780 to h'ff7f in the address space of the h8/3337y, h8/3336y, h8/3397, and h8/3396 and addresses h'fb80 to h'ff7f in the address space of the h8/3334y and h8/3394. the rame bit in the system control register (syscr) can enable or disable the on-chip ram. 17.1.1 block diagram figure 17.1 is a block diagram of the on-chip ram. h'ff7e internal data bus (upper 8 bits) h'ff7f h'f782 h'f780 h'f783 h'f781 even address odd address on-chip ram internal data bus (lower 8 bits) figure 17.1 block diagram of on-chip ram (h8/3337y) 360 17.1.2 ram enable bit (rame) in system control register (syscr) bit 76543210 ssby sts2 sts1 sts0 xrst nmieg hie rame initial value 0 0 0 0 1 0 0 1 read/write r/w r/w r/w r/w r r/w r/w r/w the on-chip ram is enabled or disabled by the rame bit in syscr. see section 3.2, system control register, for the other syscr bits. bit 0?am enable (rame): this bit enables or disables the on-chip ram. the rame bit is initialized to 1 on the rising edge of the res signal. the rame bit is not initialized in software standby mode. bit 0: rame description 0 on-chip ram is disabled. 1 on-chip ram is enabled. (initial value) 17.2 operation 17.2.1 expanded modes (modes 1 and 2) if the rame bit is set to 1, accesses to addresses h'f780 to h'ff7f in the h8/3337y, h8/3336y, h8/3397, and h8/3396 and addresses h'fb80 to h'ff7f in the h8/3334y and h8/3394 are directed to the on-chip ram. if the rame bit is cleared to 0, accesses to these addresses are directed to the external data bus. 17.2.2 single-chip mode (mode 3) if the rame bit is set to 1, accesses to addresses h'f780 to h'ff7f in the h8/3337y, h8/3336y, h8/3397, and h8/3396 and addresses h'fb80 to h'ff7f in the h8/3334y and h8/3394 are directed to the on-chip ram. if the rame bit is cleared to 0, the on-chip ram data cannot be accessed. attempted write access has no effect. attempted read access always results in h'ff data being read. notes: 1. when v cc v ram , on-chip ram values can be retained by using the specified method. see section 21.4.1 and appendix e for details. 2. on-chip ram values are not guaranteed if power is turned off, then on again, in any state. 3. when specific bits in ram are used as control bits, initial values must be set after powering on. 361 section 18 rom (mask rom version/ztat version) 18.1 overview the size of the on-chip rom is 60 kbytes in the h8/3337y and h8/3397, 48 kbytes in the h8/3336y and h8/3396, and 32 kbytes in the h8/3334y and h8/3394. the on-chip rom is connected to the cpu via a 16-bit data bus. both byte data and word data are accessed in two states, enabling rapid data transfer. the on-chip rom is enabled or disabled depending on the inputs at the mode pins (md 1 and md 0 ). see table 18.1. table 18.1 on-chip rom usage in each mcu operating mode mode pins mode md 1 md 0 on-chip rom mode 1 (expanded mode) 0 1 disabled (external addresses) mode 2 (expanded mode) 1 0 enabled mode 3 (single-chip mode) 1 1 enabled the prom versions (h8/3337y ztat and h8/3334y ztat) can be set to writer mode and programmed with a general-purpose prom programmer. in the h8/3337y and h8/3397, the accessible rom addresses are h'0000 to h'ef7f (61,312 bytes) in mode 2, and h'0000 to h'f77f (63,360 bytes) in mode 3. for details, see section 3, mcu operating modes and address space. 362 18.1.1 block diagram figure 18.1 is a block diagram of the on-chip rom. h'f77e internal data bus (upper 8 bits) h'f77f h'0002 h'0000 h'0003 h'0001 even address odd address on-chip rom internal data bus (lower 8 bits) figure 18.1 block diagram of on-chip rom (h8/3337y single-chip mode) 18.2 writer mode (h8/3337y, h8/3334y) 18.2.1 writer mode setup in writer mode the prom versions of the h8/3337y and h8/3334y suspend the usual microcomputer functions to allow the on-chip prom to be programmed. the programming method is the same as for the hn27c101, except that page programming is not supported. to select writer mode, apply the signal inputs listed in table 18.2. table 18.2 selection of writer mode pin input mode pin md 1 low mode pin md 0 low stby pin low pins p6 3 and p6 4 high 363 18.2.2 socket adapter pin assignments and memory map the h8/3337y and h8/3334y can be programmed with a general-purpose prom programmer by using a socket adapter to change the pin-out to 32 pins. see table 18.3. the same socket adapter can be used for both the h8/3337y and h8/3334y. figure 18.2 shows the socket adapter pin assignments. table 18.3 socket adapter package socket adapter 80-pin qfp hs3337eshs1h 80-pin tqfp hs3337esns1h 84-pin plcc hs3337escs1h 84-pin windowed lcc hs3337esgs1h the prom size is 60 kbytes for the h8/3337y and 32 kbytes for the h8/3334y. figures 18.3 and 18.4 show memory maps of the h8/3337y and h8/3334y in writer mode. h'ff data should be specified for unused address areas in the on-chip prom. when programming with a prom programmer, limit the program address range to h'0000 to h'f77f for the h8/3337y and h'0000 to h'7fff for the h8/3334y. specify h'ff data for addresses h'f780 and above (h8/3337y) or h'8000 and above (h8/3334y). if these addresses are programmed by mistake, it may become impossible to program or verify the prom data. the same problem may occur if an attempt is made to program the chip in page programming mode. note that the prom versions are one-time programmable (otp) microcomputers, packaged in plastic packages, and cannot be reprogrammed. 364 1 6 65 66 67 68 69 70 71 72 64 63 62 61 60 59 58 57 55 54 53 52 51 50 49 48 20 19 18 24 25 29 8, 47 5 4 7 38 12, 56, 73 res nmi p3 p3 p3 p3 p3 p3 p3 p3 p1 p1 p1 p1 p1 p1 p1 p1 p2 p2 p2 p2 p2 p2 p2 p2 p9 p9 p9 p6 p6 av v cc md md stby av v v ea eo eo eo eo eo eo eo eo ea ea ea ea ea ea ea ea ea oe ea ea ea ea ea ce ea ea pgm v v hn27c101 (32 pins) 1 26 13 14 15 17 18 19 20 21 12 11 10 9 8 7 6 5 27 24 23 25 4 28 29 22 2 3 31 32 16 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 cc 0 1 ss ss 9 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8 10 11 12 13 14 16 15 pp cc h8/3337y, h8/3334y eprom socket note: all pins not listed in this fi g ure should be left open. v pp : eo 7 to eo 0 : ea 16 to ea 0 : oe : ce : pgm : program voltage (12.5 v) data input/output address input output enable chip enable program enable ss fp-80a tfp-80c 12 17 79 80 81 82 83 84 1 3 78 77 76 75 74 73 72 71 69 68 67 66 65 63 62 61 32 31 30 36 37 42 19, 60 16 15 18 51 2, 4, 23, 24, 41, 64, 70 cp-84 cg-84 pin pin figure 18.2 socket adapter pin assignments 365 h'f77f h'f77f undefined value output * if this address area is read in writer mode, the output data is not guaranteed. h'1ffff address in writer mode address in mcu mode h'0000 h'0000 on-chip prom note: * figure 18.3 h8/3337y memory map in writer mode h'7fff h'7fff undefined value output * if this address area is read in writer mode, the output data is not guaranteed. h'1ffff address in writer mode address in mcu mode h'0000 h'0000 on-chip prom note: * figure 18.4 h8/3334y memory map in writer mode 366 18.3 prom programming the write, verify, and other sub-modes of the writer mode are selected as shown in table 18.4. table 18.4 selection of sub-modes in writer mode sub-mode ce oe pgm v pp v cc eo 7 to eo 0 ea 16 to ea 0 write low high low v pp v cc data input address input verify low low high v pp v cc data output address input programming inhibited low low high high low high low high low high low high v pp v cc high impedance address input legend: v pp :v pp level v cc :v cc level the h8/3337y and h8/3334y prom have the same standard read/write specifications as the hn27c101 eprom. page programming is not supported, however, so do not select page programming mode. prom programmers that provide only page programming cannot be used. when selecting a prom programmer, check that it supports a byte-at-a-time high-speed programming mode. be sure to set the address range to h'0000 to h'f77f for the h8/3337y, and to h'0000 to h'7fff for the h8/3334y. 18.3.1 programming and verification an efficient, high-speed programming procedure can be used to program and verify prom data. this procedure programs data quickly without subjecting the chip to voltage stress and without sacrificing data reliability. it leaves the data h'ff in unused addresses. figure 18.5 shows the basic high-speed programming flowchart. tables 18.5 and 18.6 list the electrical characteristics of the chip in writer mode. figure 18.6 shows a program/verify timing chart. 367 start set program/verify mode v cc = 6.0 v 0.25 v, v pp = 12.5 v 0.3 v address = 0 verify ok? program t opw = 0.2n ms last address? set read mode v cc = 5.0 v 0.25 v, v pp = v cc read all addresses end error n < 25? address + 1 address no yes no yes no no go program t pw = 0.2 ms 5% n = 0 n + 1 n yes go figure 18.5 high-speed programming flowchart 368 table 18.5 dc characteristics (when v cc = 6.0 v 0.25 v, v pp = 12.5 v 0.3 v, v ss = 0 v, ta = 25?c 5?c) item symbol min typ max unit test conditions input high voltage eo 7 ?o 0 , ea 16 ?a 0 , oe , ce , pgm v ih 2.4 v cc + 0.3 v input low voltage eo 7 ?eo 0 , ea 16 ?ea 0 , oe , ce , pgm v il ?.3 0.8 v output high voltage eo 7 ?o 0 v oh 2.4 v i oh = ?00 a output low voltage eo 7 ?o 0 v ol 0.45 v i ol = 1.6 ma input leakage current eo 7 ?eo 0 , ea 16 ?ea 0 , oe , ce , pgm |i li | 2 av in = 5.25 v/0.5 v v cc current i cc 40 ma v pp current i pp 40 ma 369 table 18.6 ac characteristics (when v cc = 6.0 v 0.25 v, v pp = 12.5 v 0.3 v, ta = 25?c 5?c) item symbol min typ max unit test conditions address setup time t as 2 s see figure 18.6 * oe setup time t oes 2 s data setup time t ds 2 s address hold time t ah 0 s data hold time t dh 2 s data output disable time t df 130 ns v pp setup time t vps 2 s program pulse width t pw 0.19 0.20 0.21 ms oe pulse width for overwrite-programming t opw 0.19 5.25 ms v cc setup time t vcs 2 s ce setup time t ces 2 s data output delay time t oe 0 150 ns note: * input pulse level: 0.8 v to 2.2 v input rise/fall time 20 ns timing reference levels: input?.0 v, 2.0 v; output?.8 v, 2.0 v 370 address data v pp v cc ce pgm oe figure 18.6 prom program/verify timing 371 18.3.2 notes on programming (1) a prom programmer that does not allow start address setting cannot be used. if such a prom programmer is used, it will not be possible to perform verification at addresses h'10002, h'10003, h'10004, and so on. therefore a prom programmer that allows address setting must be used. (2) program with the specified voltages and timing. the programming voltage (v pp ) is 12.5 v. caution: applied voltages in excess of the specified values can permanently destroy the chip. be particularly careful about the prom programmer? overshoot characteristics. if the prom programmer is set to hn27c101 specifications, v pp will be 12.5 v. (3) before writing data, check that the socket adapter and chip are correctly mounted in the prom writer. overcurrent damage to the chip can result if the index marks on the prom programmer, socket adapter, and chip are not correctly aligned. (4) don? touch the socket adapter or chip while writing. touching either of these can cause contact faults and write errors. (5) page programming is not supported. do not select page programming mode. (6) the h8/3337y prom size is 60 kbytes. the h8/3334y prom size is 32 kbytes. set the address range to h'0000 to h'f77f for the h8/3337y, and to h'0000 to h'7fff for the h8/3334y. when programming, specify h'ff data for unused address areas (h'f780 to h'1ffff in the h8/3337y, h'8000 to h'1ffff in the h8/3334y). 18.3.3 reliability of programmed data an effective way to assure the data holding characteristics of the programmed chips is to bake them at 150?c, then screen them for data errors. this procedure quickly eliminates chips with prom memory cells prone to early failure. figure 18.7 shows the recommended screening procedure. 372 read and check program install bake with power off 125 figure 18.7 recommended screening procedure if a series of write errors occurs while the same prom programmer is in use, stop programming and check the prom programmer and socket adapter for defects, using a microcontroller with on- chip eprom in a windowed package, for instance. please inform hitachi of any abnormal conditions noted during programming or in screening of program data after high-temperature baking. 18.3.4 erasing data data is erased by exposing the transparent window in the package to ultraviolet light. the erase conditions are shown in table 18.7. table 18.7 erase conditions item value ultraviolet wavelength 253.7nm minimum irradiation 15w s/cm 2 the erase conditions in table 18.7 can be met by exposure to a 12000 w/cm 2 ultraviolet lamp positioned 2 to 3 cm directly above the chip for approximately 20 minutes. 373 section 19 rom (32-kbyte dual-power-supply flash memory version) 19.1 flash memory overview 19.1.1 flash memory operating principle table 19.1 illustrates the principle of operation of the h8/3334yf? on-chip flash memory. like eprom, flash memory is programmed by applying a high gate-to-drain voltage that draws hot electrons generated in the vicinity of the drain into a floating gate. the threshold voltage of a programmed memory cell is therefore higher than that of an erased cell. cells are erased by grounding the gate and applying a high voltage to the source, causing the electrons stored in the floating gate to tunnel out. after erasure, the threshold voltage drops. a memory cell is read like an eprom cell, by driving the gate to the high level and detecting the drain current, which depends on the threshold voltage. erasing must be done carefully, because if a memory cell is overerased, its threshold voltage may become negative, causing the cell to operate incorrectly. section 19.4.6 shows an optimal erase control flowchart and sample program. table 19.1 principle of memory cell operation program erase read memory cell vd vg = v pp open vs = v pp vd vg memory array vd 0 v v pp 0 v 0 v open open 0 v v pp 0 v vd 0 v v cc 0 v 0 v 374 19.1.2 mode programming and flash memory address space as its on-chip rom, the h8/3334yf has 32 kbytes of flash memory. the flash memory is connected to the cpu by a 16-bit data bus. the cpu accesses both byte data and word data in two states. the h8/3334yf? flash memory is assigned to addresses h'0000 to h'7fff. the mode pins enable either on-chip flash memory or external memory to be selected for this area. table 19.2 summarizes the mode pin settings and usage of the memory area. table 19.2 mode pin settings and flash memory area mode pin setting mode md 1 md 0 memory area usage mode 0 0 0 illegal setting mode 1 0 1 external memory area mode 2 1 0 on-chip flash memory area mode 3 1 1 on-chip flash memory area 19.1.3 features features of the flash memory are listed below. ? five flash memory operating modes the flash memory has five operating modes: program mode, program-verify mode, erase mode, erase-verify mode, and prewrite-verify mode. ? block erase designation blocks to be erased in the flash memory address space can be selected by bit settings. the address space includes a large-block area (four blocks with sizes from 4 kbytes to 8 kbytes) and a small-block area (eight blocks with sizes from 128 bytes to 1 kbyte). ? program and erase time programming one byte of flash memory typically takes 50 s, while erasing typically takes 1 s. ? erase-program cycles flash memory contents can be erased and reprogrammed up to 100 times. ? on-board programming modes these modes can be used to program, erase, and verify flash memory contents. there are two modes: boot mode and user programming mode. 375 ? automatic bit-rate alignment in boot-mode data transfer, the h8/3334yf aligns its bit rate automatically to the host bit rate (maximum 9600 bps). ? flash memory emulation by ram part of the ram area can be overlapped onto flash memory, to emulate flash memory updates in real time. ? writer mode as an alternative to on-board programming, the flash memory can be programmed and erased in writer mode, using a general-purpose prom programmer. program, erase, verify, and other specifications are the same as for hn28f101 standard flash memory. 19.1.4 block diagram figure 19.1 shows a block diagram of the flash memory. flmcr ebr1 ebr2 h'0000 h'0002 h'0004 h'7ffc h'7ffe h'0001 h'0003 h'0005 h'7ffd h'7fff md 1 md 0 internal data bus (upper) internal data bus (lower) bus interface and control section operating mode on-chip flash memory (32 kbytes) upper byte (even address) lower byte (odd address) legend: flmcr: ebr1: ebr2: flash memory control register erase block register 1 erase block register 2 8 8 figure 19.1 flash memory block diagram 376 19.1.5 input/output pins flash memory is controlled by the pins listed in table 19.3. table 19.3 flash memory pins pin name abbreviation input/output function programming power fv pp power supply apply 12.0 v mode 1 md 1 input h8/3334yf operating mode setting mode 0 md 0 input h8/3334yf operating mode setting transmit data txd 1 output sci1 transmit data output receive data rxd 1 input sci1 receive data input the transmit data and receive data pins are used in boot mode. 19.1.6 register configuration the flash memory is controlled by the registers listed in table 19.4. table 19.4 flash memory registers name abbreviation r/w initial value address flash memory control register flmcr r/w * 2 h'00 * 2 h'ff80 erase block register 1 ebr1 r/w * 2 h'f0 * 2 h'ff82 erase block register 2 ebr2 r/w * 2 h'00 * 2 h'ff83 wait-state control register * 1 wscr r/w h'08 h'ffc2 notes: * 1 the wait-state control register controls the insertion of wait states by the wait-state controller, frequency division of clock signals for the on-chip supporting modules by the clock pulse generator, and emulation of flash-memory updates by ram in on-board programming mode. * 2 in modes 2 and 3 (on-chip flash memory enabled), the initial value is h'00 for flmcr and ebr2, and h'f0 for ebr1. in mode 1 (on-chip flash memory disabled), these registers cannot be modified and always read h'ff. registers flmcr, ebr1, and ebr2 are only valid when writing to or erasing flash memory, and can only be accessed while 12 v is being applied to the fv pp pin. when 12 v is not applied to the fv pp pin, in mode 2 addresses h'ff80 to h'ff83 are external address space, and in mode 3 these addresses connot be modified and always read h'ff. 377 19.2 flash memory register descriptions 19.2.1 flash memory control register (flmcr) flmcr is an 8-bit register that controls the flash memory operating modes. transitions to program mode, erase mode, program-verify mode, and erase-verify mode are made by setting bits in this register. flmcr is initialized to h'00 by a reset, in the standby modes, and when 12 v is not applied to fv pp . when 12 v is applied to the fv pp pin, a reset or entry to a standby mode initializes flmcr to h'80. bit 76543210 v pp evpve p initial value 0 0 0 0 0 0 0 0 read/write r r/w * r/w * r/w * r/w * note: * the initial value is h'00 in modes 2 and 3 (on-chip flash memory enabled). in mode 1 (on- chip flash memory disabled), this register cannot be modified and always reads h'ff. for information on accessing this register, refer to in section 19.7, flash memory programming and erasing precautions (11). bit 7?rogramming power (v pp ): this status flag indicates that 12 v is applied to the fv pp pin. refer to section 19.7, flash memory programming and erasing precautions (5), for details on use. bit 7: v pp description 0 cleared when 12 v is not applied to fv pp (initial value) 1 set when 12 v is applied to fv pp bits 6 to 4?eserved: these bits cannot be modified, and are always read as 0. bit 3?rase-verify mode (ev): *1 selects transition to or exit from erase-verify mode. bit 3: ev description 0 exit from erase-verify mode (initial value) 1 transition to erase-verify mode bit 2?rogram-verify mode (pv): *1 selects transition to or exit from program-verify mode. bit 2: pv description 0 exit from program-verify mode (initial value) 1 transition to program-verify mode 378 bit 1?rase mode (e): *1, *2 selects transition to or exit from erase mode. bit 1: e description 0 exit from erase mode (initial value) 1 transition to erase mode bit 0?rogram mode (p): *1, *2 selects transition to or exit from program mode. bit 0: p description 0 exit from program mode (initial value) 1 transition to program mode notes: *1 do not set two or more of these bits simultaneously. do not release or shut off the v cc or v pp power supply when these bits are set. *2 set the p or e bit according to the instructions given in section 19.4, programming and erasing flash memory. set the watchdog timer beforehand to make sure that these bits do not remain set for longer than the specified times. for notes on use, see section 19.7, flash memory programming and erasing precautions. 19.2.2 erase block register 1 (ebr1) ebr1 is an 8-bit register that designates large flash-memory blocks for programming and erasure. ebr1 is initialized to h'f0 by a reset, in the standby modes, and when 12 v is not applied to the fv pp pin. when a bit in ebr1 is set to 1, the corresponding block is selected and can be programmed and erased. figure 19.2 and table 19.6 show details of a block map. bit 76543210 lb3 lb2 lb1 lb0 initial value 1 1 1 1 0 0 0 0 read/write r/w * r/w * r/w * r/w * note: * the initial value is h'f0 in modes 2 and 3 (on-chip rom enabled). in mode 1 (on-chip rom disabled), this register cannot be modified and always reads h'ff. for information on accessing this register, refer to in section 19.7 flash memory programming and erasing precautions (11). 379 bits 7 to 4?eserved: these bits cannot be modified, and are always read as 1. bits 3 to 0?arge block 3 to 0 (lb3 to lb0): these bits select large blocks (lb3 to lb0) to be programmed and erased. bits 3 to 0: lb3 to lb0 description 0 block (lb3 to lb0) is not selected (initial value) 1 block (lb3 to lb0) is selected 19.2.3 erase block register 2 (ebr2) ebr2 is an 8-bit register that designates small flash-memory blocks for programming and erasure. ebr2 is initialized to h'00 by a reset, in the standby modes, and when 12 v is not applied to the fv pp pin. when a bit in ebr2 is set to 1, the corresponding block is selected and can be programmed and erased. figure 19.2 and table 19.6 show a block map. bit 76543210 sb7 sb6 sb5 sb4 sb3 sb2 sb1 sb0 initial value 0 0 0 0 0 0 0 0 read/write r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * note: * the initial value is h'00 in modes 2 and 3 (on-chip rom enabled). in mode 1 (on-chip rom disabled), this register cannot be modified and always reads h'ff. for information on accessing this register, refer to in section 19.7 flash memory programming and erasing precautions (11). bits 7 to 0?mall block 7 to 0 (sb7 to sb0): these bits select small blocks (sb7 to sb0) to be programmed and erased. bits 7 to 0: sb7 to sb0 description 0 block (sb7 to sb0) is not selected (initial value) 1 block (sb7 to sb0) is selected 380 19.2.4 wait-state control register (wscr) wscr is an 8-bit readable/writable register that enables flash-memory updates to be emulated in ram. it also controls frequency division of clock signals supplied to the on-chip supporting modules and insertion of wait states by the wait-state controller. wscr is initialized to h'08 by a reset and in hardware standby mode. it is not initialized in software standby mode. bit 76543210 rams ram0 ckdbl wms1 wms0 wc1 wc0 initial value 0 0 0 0 1 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w bits 7 and 6?am select and ram0 (rams and ram0): these bits are used to reassign an area to ram (see table 19.5). these bits are write-enabled and their initial value is 0. they are initialized by a reset and in hardware standby mode. they are not initialized in software standby mode. if only one of bits 7 and 6 is set, part of the ram area can be overlapped onto the small-block flash memory area. in that case, access is to ram, not flash memory, and all flash memory blocks are write/erase-protected (emulation protect *1 ). in this state, the mode cannot be changed to program or erase mode, even if the p bit or e bit in the flash memory control register (flmcr) is set (although verify mode can be selected). therefore, clear both of bits 7 and 6 before programming or erasing the flash memory area. if both of bits 7 and 6 are set, part of the ram area can be overlapped onto the small-block flash memory area, but this overlapping begins only when an interrupt signal is input while 12 v is being applied to the fv pp pin. up until that point, flash memory is accessed. use this setting for interrupt handling while flash memory is being programmed or erased. *2 table 19.5 ram area reassignment *3 bit 7: rams bit 6: ram0 ram area rom area 0 0 none 1 h'fc80 to h'fcff h'0080 to h'00ff 1 0 h'fc80 to h'fd7f h'0080 to h'017f 1 h'fc00 to h'fc7f h'0000 to h'007f 381 bit 5?lock double (ckdbl): controls frequency division of clock signals supplied to the on- chip supporting modules. for details, see section 6, clock pulse generator. bit 4?eserved: this bit is reserved, but it can be written and read. its initial value is 0. bits 3 and 2?ait mode select 1 and 0 (wms1, wms0) bits 1 and 0?ait count 1 and 0 (wc1, wc0) these bits control insertion of wait states by the wait-state controller. for details, see section 5, wait-state controller. notes: *1 for details on emulation protect, see section 19.4.8, protect modes. *2 for details on interrupt handling during programming and erasing of flash memory, see section 19.4.9, interrupt handling during flash memory programming and erasing. *3 ram area that overlaps flash memory. 382 h'0000 h'01ff h'0200 h'03ff h'0400 h'07ff h'0800 h'0bff h'0c00 h'0fff h'0000 h'0fff h'1000 h'1fff h'2000 h'3fff h'4000 h'5fff h'6000 h'7fff small block area (4 kbytes) large block area (28 kbytes) sb7 to sb0 4 kbytes lb0 4 kbytes lb1 8 kbytes lb2 8 kbytes lb3 8 kbytes sb0 128 bytes sb1 128 bytes sb2 128 bytes sb3 128 bytes sb4 512 bytes sb5 1 kbyte sb6 1 kbyte sb7 1 kbyte figure 19.2 erase block map 383 table 19.6 erase blocks and corresponding bits register bit block address size ebr1 0 lb0 h'1000 to h'1fff 4 kbytes 1 lb1 h'2000 to h'3fff 8 kbytes 2 lb2 h'4000 to h'5fff 8 kbytes 3 lb3 h'6000 to h'7fff 8 kbytes ebr2 0 sb0 h'0000 to h'007f 128 bytes 1 sb1 h'0080 to h'00ff 128 bytes 2 sb2 h'0100 to h'017f 128 bytes 3 sb3 h'0180 to h'01ff 128 bytes 4 sb4 h'0200 to h'03ff 512 bytes 5 sb5 h'0400 to h'07ff 1 kbyte 6 sb6 h'0800 to h'0bff 1 kbyte 7 sb7 h'0c00 to h'0fff 1 kbyte 19.3 on-board programming modes when an on-board programming mode is selected, the on-chip flash memory can be programmed, erased, and verified. there are two on-board programming modes: boot mode, and user programming mode. these modes are selected by inputs at the mode pins (md 1 and md 0 ) and fv pp pin. table 19.7 indicates how to select the on-board programming modes. for details on applying voltage v pp , refer to section 19.7, flash memory programming and erasing precautions (5). table 19.7 on-board programming mode selection mode selections fv pp md 1 md 0 notes boot mode mode 2 12 v * 12 v * 0 0: v il mode 3 12 v * 1 1: v ih user programming mode 2 1 0 mode mode 3 1 1 note: * for details on the timing of 12 v application, see notes 6 to 8 in the notes on use of boot mode at the end of this section. in boot mode, the mode control register (mdcr) can be used to monitor the mode (mode 2 or 3) in the same way as in normal mode. example: set the mode pins for mode 2 boot mode (md 1 = 12 v, md 0 = 0 v). if the mode select bits of mdcr are now read, they will indicate mode 2 (mds1 = 1, mds0 = 0). 384 19.3.1 boot mode to use boot mode, a user program for programming and erasing the flash memory must be provided in advance on the host machine (which may be a personal computer). serial communication interface channel 1 is used in asynchronous mode. if the h8/3334yf is placed in boot mode, after it comes out of reset, a built-in boot program is activated. this program starts by measuring the low period of data transmitted from the host and setting the bit rate register (brr) accordingly. the h8/3334yf? built-in serial communication interface (sci) can then be used to download the user program from the host machine. the user program is stored in on-chip ram. after the program has been stored, execution branches to address h'fbe0 in the on-chip ram, and the program stored on ram is executed to program and erase the flash memory. figure 19.4 shows the boot-mode execution procedure. host receive data to be programmed transmit verification data h8/3334yf rxd 1 txd 1 sci figure 19.3 boot-mode system configuration 385 boot-mode execution procedure: figure 19.4 shows the boot-mode execution procedure. start program h8/3334yf pins for boot mode, and reset host transmits h'00 data continuously at desired bit rate h8/3334yf measures low period of h'00 data transmitted from host h8/3334yf computes bit rate and sets bit rate register after completing bit-rate alignment, h8/3334yf sends one h'00 data byte to host to indicate that alignment is completed host checks that this byte, indicating completion of bit-rate alignment, is received normally, then transmits one h'55 byte after receiving h'55, h8/3334yf sends part of the boot program to ram h8/3334yf transfers one user program byte to ram * 2 h8/3334yf calculates number of bytes left to be transferred (n = n 1) all bytes transferred? (n = 0?) all data = h'ff? erase all flash memory blocks * 3 after transferring the user program to ram, h8/3334yf tr ansmits one h'aa data byte to host no yes yes no 1 2 3 4 5 6 7 9 h8/3334yf branches to the ram boot area (h'fc00 to h'ff2f), then checks the data in the user area of flash memory h8/3334yf receives two bytes indicating byte length (n) of program to be downloaded to on-chip ram * 1 8 after checking that all data in flash memory is h'ff, h8/3334yf transmits one h'aa data byte to host h8/3334yf br anches to h'fbe0 in ram area and executes user program downloaded into ram 10 1. program the h8/3334yf pins for boot mode, and start the h8/3334yf from a reset. 2. set the host s data format to 8 bits + 1 stop bit, select the desired bit rate (2400, 4800, or 9600 bps), and transmit h'00 data continuously. 3. the h8/3334yf repeatedly measures the low period of the rxd1 pin and calculates the host s asynchronous- communication bit rate. 4. when sci bit-rate alignment is completed, the h8/3334yf transmits one h'00 data byte to indicate completion of alignment. 5. the host should receive the byte transmitted from the h8/3334yf to indicate that bit-rate alignment is completed, check that this byte is received normally, then transmit one h'55 byte. 6. after receiving h'55, h8/3334yf sends part of the boot program to h'fb80 to h'fbdf and h'fc00 to h'ff2f of ram. 7. after branching to the boot program area (h'fc00 to h'ff2f) in ram, the h8/3334yf checks whether the flash memory already contains any programmed data. if so, all blocks are erased. 8. after the h8/3334yf transmits one h'aa data byte, the host transmits the byte length of the user program to be transferred to the h8/3334yf. the byte length must be sent as two-byte data, upper byte first and lower byte second. after that, the host proceeds to transmit the user program. as verification, the h8/3334yf echoes each byte of the received byte-length data and user program back to the host. 9. the h8/3334yf stores the received user program in on- chip ram in a 910-byte area from h'fbe0 to h'ff6d. 10. after transmitting one h'aa data byte, the h8/3334yf branches to address h'fbe0 in on-chip ram and executes the user program stored in the area from h'fbe0 to h'ff6d. notes: * 1 the user can use 910 bytes of ram. the number of bytes transferred must not exceed 910 bytes. be sure to transmit the byte length in two bytes, upper byte first and lower byte second. for example, if the byte length of the program to be transferred is 256 bytes (h'0100), transmit h'01 as the upper byte, followed by h'00 as the lower byte. * 2 the part of the user program that controls the flash memory should be coded according to the flash memory write/erase algorithms given later. * 3 if a memory cell malfunctions and cannot be erased, the h8/3334yf transmits one h'ff byte to report an erase error, halts erasing, and halts further operations. figure 19.4 boot mode flowchart 386 automatic alignment of sci bit rate d0 d1 d2 d3 d4 d5 d6 d7 start bit stop bit this low period (9 bits) is measured (h'00 data) high for at least 1 bit figure 19.5 measurement of low period in data transmitted from host when started in boot mode, the h8/3334yf measures the low period in asynchronous sci data transmitted from the host (figure 19.5). the data format is eight data bits, one stop bit, and no parity bit. from the measured low period (9 bits), the h8/3334yf computes the host s bit rate. after aligning its own bit rate, the h8/3334yf sends the host 1 byte of h'00 data to indicate that bit-rate alignment is completed. the host should check that this alignment-completed indication is received normally and send one byte of h'55 back to the h8/3334yf. if the alignment-completed indication is not received normally, the h8/3334yf should be reset, then restarted in boot mode to measure the low period again. there may be some alignment error between the host s and h8/3334yf s bit rates, depending on the host s bit rate and the h8/3334yf s system clock frequency. to have the sci operate normally, set the host s bit rate to 2400, 4800, or 9600 bps *1 . table 19.8 lists typical host bit rates and indicates the clock-frequency ranges over which the h8/3334yf can align its bit rate automatically. boot mode should be used within these frequency ranges *2 . table 19.8 system clock frequencies permitting automatic bit-rate alignment by h8/3334yf host bit rate * 1 system clock frequencies permitting automatic bit-rate alignment by h8/3334yf 9600 bps 8 mhz to 16 mhz 4800 bps 4 mhz to 16 mhz 2400 bps 2 mhz to 16 mhz notes: * 1 use a host bit rate setting of 2400, 4800, or 9600 bps only. no other setting should be used. * 2 although the h8/3334yf may also perform automatic bit-rate alignment with bit rate and system clock combinations other than those shown in table 19.8, there will be a slight difference between the bit rates of the host and the h8/3334yf, and subsequent transfer will not be performed normally. therefore, only a combination of bit rate and system clock frequency within one of the ranges shown in table 19.8 can be used for boot mode execution. 387 ram area allocation in boot mode: in boot mode, the 96 bytes from h'fb80 to h'fbdf and the 18 bytes from h'ff6e to h'ff7f are reserved for use by the boot program, as shown in figure 19.6. the user program is transferred into the area from h'fbe0 to h'ff6d (910 bytes). the boot program area can be used after the transition to execution of the user program transferred into ram. if a stack area is needed, set it within the user program. user program transfer area (910 bytes) boot program area * (18 bytes) boot program area * (96 bytes) h'fb80 h'fbe0 h'ff6e h'ff7f note: * this area cannot be used until the h8/3334yf starts to execute the user program transferred to ram (until it has branched to h'fbe0 in ram). note that even after the branch to the user program, the boot program area (h'fb80 to h'fbdf, h'ff6e to h'ff7f) still contains the boot program. note also that 16 bytes (h'fb80 to h'fb8f) of this area cannot be used if an interrupt handling routine is executed within the boot program. for details see section 19.4.9, interrupt handling during flash memory programming and erasing. figure 19.6 ram areas in boot mode 388 notes on use of boot mode 1. when the h8/3334yf comes out of reset in boot mode, it measures the low period of the input at the sci s rxd 1 pin. the reset should end with rxd 1 high. after the reset ends, it takes about 100 states for the h8/3334yf to get ready to measure the low period of the rxd 1 input. 2. in boot mode, if any data has been programmed into the flash memory (if all data is not h'ff), all flash memory blocks are erased. boot mode is for use when user programming mode is unavailable, e.g. the first time on-board programming is performed, or if the update program activated in user programming mode is accidentally erased. 3. interrupts cannot be used while the flash memory is being programmed or erased. 4. the rxd 1 and txd 1 pins should be pulled up on-board. 5. before branching to the user program (at address h'fbe0 in the ram area), the h8/3334yf terminates transmit and receive operations by the on-chip sci (by clearing the re and te bits of the serial control register to 0 in channel 1), but the auto-aligned bit rate remains set in bit rate register brr. the transmit data output pin (txd 1 ) is in the high output state (in port 8, the bits p8 4 ddr of the port 8 data direction register and p8 4 dr of the port 8 data register are set to 1). at this time, the values of general registers in the cpu are undetermined. thus these registers should be initialized immediately after branching to the user program. especially in the case of the stack pointer, which is used implicitly in subroutine calls, the stack area used by the user program should be specified. there are no other changes to the initialized values of other registers. 6. boot mode can be entered by starting from a reset after 12 v is applied to the md 1 and fv pp pins according to the mode setting conditions listed in table 19.7. note the following points when turning the v pp power on. when reset is released (at the rise from low to high), the h8/3334yf checks for 12-v input at the md 1 and fv pp pins. if it detects that these pins are programmed for boot mode, it saves that status internally. the threshold point of this voltage-level check is in the range from approximately v cc + 2 v to 11.4 v, so boot mode will be entered even if the applied voltage is insufficient for programming or erasure (11.4 v to 12.6 v). when the boot program is executed, the v pp power supply must therefore be stabilized within the range of 11.4 v to 12.6 v before the branch to the ram area occurs. see figure 19.20. make sure that the programming voltage v pp does not exceed 12.6 v during the transition to boot mode (at the reset release timing) and does not go outside the range of 12 v 389 addition, make sure that v pp is not released or shut off while the boot program is executing or the flash memory is being programmed or erased. *1 boot mode can be released by driving the reset pin low, waiting at least ten system clock cycles, then releasing the application of 12 v to the md 1 and fv pp pins and releasing the reset. the settings of external pins must not change during operation in boot mode. during boot mode, if input of 12 v to the md 1 pin stops but no reset input occurs at the res pin, the boot mode state is maintained within the chip and boot mode continues (but do not stop applying 12 v to the fv pp pin during boot mode *1 ). if a watchdog timer reset occurs during boot mode, this does not release the internal mode state, but the internal boot program is restarted. therefore, to change from boot mode to another mode, the boot-mode state within the chip must be released by a reset input at the res pin before the mode transition can take place. 7. if the input level of the md 1 pin is changed during a reset (e.g., from 0 v to 5 v then to 12 v while the input to the res pin is low), the resultant switch in the microcontroller s operating mode will affect the bus control output signals ( as , rd , and wr ) and the status of ports that can be used for address output *2 . therefore, either set these pins so that they do not output signals during the reset, or make sure that their output signals do not collide with other signals outside the microcontroller. 8. when applying 12 v to the md 1 and fv pp pins, make sure that peak overshoot does not exceed the rated limit of 13 v. also, be sure to connect a decoupling capacitor to the fv pp and md 1 pins. notes: *1 for details on applying, releasing, and shutting off v pp , see note (5) in section 19.7, flash memory programming and erasing precautions. *2 these ports output low-level address signals if the mode pins are set to mode 1 during the reset. in all other modes, these ports are in the high-impedance state. the bus control output signals are high if the mode pins are set for mode 1 or 2 during the reset. in mode 3, they are at high impedance. 390 19.3.2 user programming mode when set to user programming mode, the h8/3334yf can erase and program its flash memory by executing a user program. on-board updates of the on-chip flash memory can be carried out by providing on-board circuits for supplying v pp and data, and storing an update program in part of the program area. to select user programming mode, select a mode that enables the on-chip rom (mode 2 or 3) and apply 12 v to the fv pp pin, either during a reset, or after the reset has ended (been released) but while flash memory is not being accessed. in user programming mode, the on-chip supporting modules operate as they normally would in mode 2 or 3, except for the flash memory. however, hardware standby mode cannot be set while 12 v is applied to the fv pp pin. the flash memory cannot be read while it is being programmed or erased, so the update program must either be stored in external memory, or transferred temporarily to the ram area and executed in ram. 391 user programming mode execution procedure (example)*: figure 19.7 shows the execution procedure for user programming mode when the on-board update routine is executed in ram. note: * do not apply 12 v to the fv pp pin during normal operation. to prevent flash memory from being accidentally programmed or erased due to program runaway etc., apply 12 v to fv pp only when programming or erasing flash memory. overprogramming or overerasing due to program runaway can cause memory cells to malfunction. while 12 v is applied, the watchdog timer should be running and enabled to halt runaway program execution, so that program runaway will not lead to overprogramming or overerasing. for details on applying, releasing, and shutting off v pp , see section 19.7, flash memory programming and erasing precautions (5). set md 1 and md 0 to 10 or 11 (apply v ih to v cc to md 1 ) start from reset branch to flash memory on-board update routine in ram fv pp = 12 v (user programming mode) execute flash memory on-board update routine in ram (update flash memory) 1 2 3 4 5 branch to flash memory on-board update program transfer on-board update routine into ram 6 7 8 release fv pp (exit user programming mode) branch to application program in flash memory * procedure the flash memory on-board update program is written in flash memory ahead of time by the user. 1. set md1 and md0 of the h8/3334yf to 10 or 11, and start from a reset. 2. branch to the flash memory on-board update program in flash memory. 3. transfer the on-board update routine into ram. 4. branch to the on-board update routine that was transferred into ram. 5. apply 12 v to the fv pp pin, to enter user programming mode. 6. execute the flash memory on-board update routine in ram, to perform an on-board update of the flash memory. 7. change the voltage at the fv pp pin from 12 v to v cc , to exit user programming mode. 8. after the on-board update of flash memory ends, execution branches to an application program in flash memory. note: * after the update is finished, when input of 12 v to the fv pp pin is released, the flash memory read setup time (t frs ) must elapse before any program in flash memory is executed. this is the required setup time from when the fv pp pin reaches the (v cc + 2 v) level after 12 v is released until flash memory can be read. figure 19.7 user programming mode operation (example) 392 19.4 programming and erasing flash memory the h8/3334yf s on-chip flash memory is programmed and erased by software, using the cpu. the flash memory can operate in program mode, erase mode, program-verify mode, erase-verify mode, or prewrite-verify mode. transitions to these modes can be made by setting the p, e, pv, and ev bits in the flash memory control register (flmcr). the flash memory cannot be read while being programmed or erased. the program that controls the programming and erasing of the flash memory must be stored and executed in on-chip ram or in external memory. a description of each mode is given below, with recommended flowcharts and sample programs for programming and erasing. for details on programming and erasing, refer to section 19.7, flash memory programming and erasing precautions. 19.4.1 program mode to write data into the flash memory, follow the programming algorithm shown in figure 19.8. this programming algorithm can write data without subjecting the device to voltage stress or impairing the reliability of programmed data. to program data, first specify the area to be written in flash memory with erase block registers ebr1 and ebr2, then write the data to the address to be programmed, as in writing to ram. the flash memory latches the address and data in an address latch and data latch. next set the p bit in flmcr, selecting program mode. the programming duration is the time during which the p bit is set. a software timer should be used to provide a programming duration of about 10 to 20 393 19.4.2 program-verify mode in program-verify mode, after data has been programmed in program mode, the data is read to check that it has been programmed correctly. after the programming time has elapsed, exit programming mode (clear the p bit to 0) and select program-verify mode (set the pv bit to 1). in program-verify mode, a program-verify voltage is applied to the memory cells at the latched address. if the flash memory is read in this state, the data at the latched address will be read. after selecting program-verify mode, wait 4 394 19.4.3 programming flowchart and sample program flowchart for programming one byte start n = 1 enable watchdog timer * 2 select program mode (p bit = 1 in flmcr) wait (x) figure 19.8 programming flowchart 395 sample program for programming one byte: this program uses the following registers. r0h: specifies blocks to be erased. r1h: stores data to be programmed. r1l: stores data to be read. r3: stores address to be programmed. valid addresses are h'0000 to h'7fff. r4: sets program and program-verify timing loop counters, and also stores register setting value. r5: sets program timing loop counter. r6l: used for program-verify fail count. arbitrary data can be programmed at an arbitrary address by setting the address in r3 and the data in r1h. the setting of #a and #b values depends on the clock frequency. set #a and #b values according to tables 19.9 (1) and (2). flmcr: .equ h'ff80 ebr1: .equ h'ff82 ebr2: .equ h'ff83 tcsr: .equ h'ffa8 .align 2 prgm: mov.b #h'**, r0h ; mov.b r0h, @ebr*:8 ; set ebr * mov.b #h'00, r6l ; program-verify fail counter mov.w #h'a, r5 ; set program loop counter mov.b r1h, @r3 ; dummy write prgms: inc r6l ; program-verify fail counter + 1 mov.w #h'a578, r4 ; mov.w r4, @tcsr ; start watchdog timer mov.w r5, r4 ; set program loop counter bset #0, @flmcr:8 ; set p bit loop1: subs #1, r4 ; mov.w r4, r4 ; bne loop1 ; wait loop bclr #0, @flmcr:8 ; clear p bit mov.w #h'a500, r4 ; mov.w r4, @tcsr ; stop watchdog timer mov.b #h'b , r4h ; set program-verify loop counter bset #2, @flmcr:8 ; set pv bit loop2: dec r4h ; bne loop2 ; wait loop mov.b @r3, r1l ; read programmed address cmp.b r1h, r1l ; compare programmed data with read data beq pvok ; program-verify decision bclr #2, @flmcr:8 ; clear pv bit 396 cmp.b #h'32, r6l ; program-verify executed 50 times? beq ngend ; if program-verify executed 50 times, branch to ngend bra prgms ; program again pvok: bclr #2, @flmcr:8 ; clear pv bit mov.b #h'00, r6l ; mov.b r6l, @ebr*:8 ; clear ebr * one byte programmed ngend: programming error 19.4.4 erase mode to erase the flash memory, follow the erasing algorithm shown in figure 19.11. this erasing algorithm can erase data without subjecting the device to voltage stress or impairing the reliability of programmed data. to erase flash memory, before starting to erase, first place all memory data in all blocks to be erased in the programmed state (program all memory data to h'00). if all memory data is not in the programmed state, follow the sequence described later (figure 18-17) to program the memory data to zero. select the flash memory areas to be erased with erase block registers 1 and 2 (ebr1 and ebr2). next set the e bit in flmcr, selecting erase mode. the erase time is the time during which the e bit is set. to prevent overerasing, use a software timer to divide the erase time into repeated 10 ms intervals, and perform erase operations a maximum of 3000 times so that the total erase time does not exceed 30 seconds. overerasing, due to program runaway for example, can give memory cells a negative threshold voltage and cause them to operate incorrectly. before selecting erase mode, set up the watchdog timer so as to prevent overerasing. 19.4.5 erase-verify mode in erase-verify mode, after data has been erased, it is read to check that it has been erased correctly. after the erase time has elapsed, exit erase mode (clear the e bit to 0) and select erase- verify mode (set the ev bit to 1). before reading data in erase-verify mode, write h'ff dummy data to the address to be read. this dummy write applies an erase-verify voltage to the memory cells at the latched address. if the flash memory is read in this state, the data at the latched address will be read. after the dummy write, wait 2 397 19.4.6 erasing flowchart and sample program flowchart for erasing one block start write 0 data in all addresses to be erased (prewrite) * 1 n = 1 set erase block register (set bit of block to be erased to 1) enable watchdog timer * 2 select erase mode (e bit = 1 in flmcr) wait (x) ms * 5 clear e bit disable watchdog timer set top address in block as verify address select erase-verify mode (ev bit = 1 in flmcr) wait (t vs 1) figure 19.9 erasing flowchart 398 prewrite flowchart end of prewrite n figure 19.10 prewrite flowchart 399 sample block-erase program: this program uses the following registers. r0: specifies block to be erased, and also stores address used in prewrite and erase-verify. r1h: stores data to be read, and also used for dummy write. r2: stores last address of block to be erased. r3: stores address used in prewrite and erase-verify. r4: sets timing loop counters for prewrite, prewrite-verify, erase, and erase-verify, and also stores register setting value. r5: sets prewrite and erase timing loop counters. r6l: used for prewrite-verify and erase-verify fail count. the setting of #a, #b, #c, #d, and #e values in the program depends on the clock frequency. set #a, #b, #c, #d, and #e values according tables 19.9 (1) and (2), and 19.10 erase block registers (ebr1 and ebr2) should be set according to sections 19.2.2 and 19.2.3. #blkstr and #blkend are the top and last addresses of the block to be erased. set #blkstr and #blkend according to figure 19.2. 400 flmcr: .equ h'ff80 ebr1: .equ h'ff82 ebr2: .equ h'ff83 tcsr: .equ h'ffa8 .align 2 mov.b #h'**, roh ; mov.b roh, @ebr*:8 ; set ebr* ; #blkstr is top address of block to be erased. ; #blkend is last address of block to be erased. mov.w #blkstr, r0 ; top address of block to be erased mov.w #blkend, r2 ; last address of block to be erased adds #1, r2 ; last address of block to be erased + 1 mov.w r0, r3 ; top address of block to be erased prewrt: mov.b #h'00, r6l ; prewrite-verify fail counter mov.w #h'a, r5 ; set prewrite loop counter prewrs: inc r6l ; prewrite-verify fail counter + 1 mov.b #h'00 r1h ; mov.b r1h, @r3 ; write h'00 mov.w #h'a578, r4 ; mov.w r4, @tcsr ; start watchdog timer mov.w r5, r4 ; set prewrite loop counter bset #0, @flmcr:8 ; set p bit loopr1: subs #1, r4 ; mov.w r4, r4 ; bne loopr1 ; wait loop bclr #0, @flmcr:8 ; clear p bit mov.w #h'a500, r4 ; mov.w r4, @tcsr ; stop watchdog timer mov.b #h'c, r4h ; set prewrite-verify loop counter loopr2: dec r4h ; bne loopr2 ; wait loop mov.b @r3, r1h ; read data = h'00? beq pwvfok ; if read data = h'00 branch to pwvfok cmp.b #h'32, r6l ; prewrite-verify executed 50 times? beq abend1 ; if prewrite-verify executed 50 times, branch to abend1 bra prewrs ; prewrite again abend1: programming error pwvfok: adds #1, r3 ; address + 1 cmp.w r2, r3 ; last address? bne prewrt ; if not last address, prewrite next address 401 ; execute erase erases: mov.w #h'0000, r6 ; erase-verify fail counter mov.w #h'd, r5 ; set erase loop count erase: adds #1, r6 ; erase-verify fail counter + 1 mov.w #h'e, r4 ; mov.w r4, @tcsr ; start watchdog timer mov.w r5, r4 ; set erase loop counter bset #1, @flmcr:8 ; set e bit loope: nop nop nop nop subs #1, r4 ; mov.w r4, r4 ; bne loope ; wait loop bclr #1, @flmcr:8 ; clear e bit mov.w #h'a500, r4 ; mov.w r4, @tcsr ; stop watchdog timer ; execute erase-verify mov.w r0, r3 ; top address of block to be erased mov.b #h'b, r4h ; set erase-verify loop counter bset #3, @flmcr:8 ; set ev bit loopev: dec r4h ; bne loopev ; wait loop evr2: mov.b #h'ff, r1h ; mov.b r1h, @r3 ; dummy write mov.b #h'c, r4h ; set erase-verify loop counter loopdw: dec r4h ; bne loopdw ; wait loop mov.b @r3+, r1h ; read cmp.b #h'ff, r1h ; read data = h'ff? bne rerase ; if read data cmp.w r2, r3 ; last address of block? bne evr2 bra okend rerase: bclr #3, @flmcr:8 ; clear ev bit subs #1, r3 ; erase-verify address 1 brer: mov.w #h'0bb8, r4 ; cmp.w r4, r6 ; erase-verify executed 3000 times? bne erase ; if erase-verify not executed 3000 times, erase again bra abend2 ; if erase-verify executed 3000 times, branch to abend2 okend: bclr #3, @flmcr:8 ; clear ev bit mov.b #h'00, r6l ; mov.b r6l, @ebr*:8 ; clear ebr* one block erased abend2: erase error 402 flowchart for erasing multiple blocks start write 0 data to all addresses to be erased (prewrite) * 1 n = 1 set erase block registers (set bits of blocks to be erased to 1) enable watchdog timer * 2 select erase mode (e bit = 1 in flmcr) wait (x) ms * 5 clear e bit disable watchdog timer select erase-verify mode (ev bit = 1 in flmcr) wait (t vs 1) figure 19.11 multiple-block erase flowchart 403 sample multiple-block erase program: this program uses the following registers. r0: specifies blocks to be erased (set as explained below), and also stores address used in prewrite and erase-verify. r1h: used to test bits 8 to 11 of r0 stores register read data, and also used for dummy write. r1l: used to test bits 0 to 11 of r0. r2: specifies address where address used in prewrite and erase-verify is stored. r3: stores address used in prewrite and erase-verify. r4: stores last address of block to be erased. r5: sets prewrite and erase timing loop counters. r6l: used for prewrite-verify and erase-verify fail count. arbitrary blocks can be erased by setting bits in r0. write r0 with a word transfer instruction. a bit map of r0 and a sample setting for erasing specific blocks are shown next. bit 1514131211109876543210 r0 lb3 lb2 lb1 lb0 sb7 sb6 sb5 sb4 sb3 sb2 sb1 sb0 corresponds to ebr1 corresponds to ebr2 note: clear bits 15, 14, 13, and 12 to 0. example: to erase blocks lb2, sb7, and sb0 bit 1514131211109876543210 r0 lb3 lb2 lb1 lb0 sb7 sb6 sb5 sb4 sb3 sb2 sb1 sb0 corresponds to ebr1 corresponds to ebr2 setting 0000010010000001 r0 is set as follows: mov.w #h'0481,r0 mov.w r0, @ebr1 the setting of #a, #b, #c, #d, and #e values in the program depends on the clock frequency. set #a, #b, #c, #d, and #e values according to tables 19.9 (1), (2), and 19.10. 404 notes: 1. in this sample program, the stack pointer (sp) is set at address ff80. as the stack area, on-chip ram addresses ff7e and ff7f are used. therefore, when executing this sample program, addresses ff7e and ff7f should not be used. in addition, the on-chip ram should not be disabled. 2. in this sample program, the program written in a rom area (including external space) is transferred into the ram area and executed in the ram to which the program is transferred. #ramstr in the program is the starting destination address in ram to which the program is transferred. #ramstr must be set to an even number. 3. when executing this sample program in the on-chip rom area or external space, #ramstr should be set to #start. flmcr: .rqu h'ff80 ebr1: .equ h'ff82 ebr2: .equ h'ff83 tcsr: .equ h'ffa8 stack: .equ h'ff80 .align2 start: mov.w #stack, sp ; set stack pointer ; set the bits in r0 following the description on the previous page. this program is a sample program to ; erase all blocks. mov.w #h'0fff, r0 ; select blocks to be erased (r0: ebr1/ebr2) mov.w r0, @ebr1 ; set ebr1/ebr2 ; #ramstr is starting destination address to which program is transferred in ram. ; set #ramstr to even number. mov.w #ramstr, r2 ; starting transfer destination address (ram) mov.w #ervadr, r3 ; add.w r3, r2 ; #ramstr + #ervadr mov.w #start, r3 ; sub.w r3, r2 ; address of data area used in ram mov.b #h'00, r1l : used to test r1l bit in r0 pretst: cmp.b #h'0c, r1l ; r1l = h'0c? beq erases ; if finished checking all r0 bits, branch to erases cmp.b #h'08, r1l ; bmi ebr2pw ; test ebr1 if r1l mov.b r1l, r1h ; subx #h'08, r1h ; r1l 8 btst r1h, r0h ; test r1h bit in ebr1 (r0h) bne prewrt ; if r1h bit in ebr1 (r0h) is 1, branch to prewrt bra pwadd1 ; if r1h bit in ebr1 (r0h) is 0, branch to pwadd1 ebr2pw: btst r1l, r0l ; test r1l bit in ebr2 (r0l) bne prewrt ; if r1l bit in ebr2 (r0h) is 1, branch to prewrt pwadd1: inc r1l ; r1l + 1 mov.w @r2+, r3 ; dummy-increment r2 bra pretst ; 405 ; execute prewrite prewrt: mov.w @r2+, r3 ; prewrite starting address prew: mov.b #h'00, r6l ; prewrite-verify fail counter mov.w #h'a, r5 ; prewrite-verify loop counter prewrs: inc r6l ; prewrite-verify fail counter + 1 mov.b #h'00, r1h ; mov.b r1h, @r3 ; write h'00 mov.w #h'a578, r4 ; mov.w r4, @tcsr ; start watchdog timer mov.w r5, r4 ; set prewrite loop counter bset #0, @flmcr:8 ; set p bit loopr1: subs #1, r4 ; mov.w r4, r4 ; bne loopr1 ; wait loop bclr #0, @flmcr:8 ; clear p bit mov.w #h'a500, r4 ; mov.w r4, @tcsr ; stop watchdog timer mov.b #h'c, r4h ; set prewrite-verify loop counter loopr2: dec r4h ; bne loopr2 ; wait loop mov.b @r3, r1h ; read data = h'00? beq pwvfok ; if read data = h'00 branch to pwvfok cmp.b #h'32, r6l ; prewrite-verify executed 50 times? beq abend1 ; if prewrite-verify executed 50 times, branch to abend1 bra prewrs ; prewrite again abend1: programming error pwvfok: adds #1, r3 ; address + 1 mov.w @r2, r4 ; top address of next block cmp.w r4, r3 ; last address? bne prew ; if not last address, prewrite next address pwadd2: inc r1l ; used to test r1l+1 bit in r0 bra pretst ; branch to pretst ; execute erase erases: mov.w #h'0000, r6 ; erase-verify fail counter mov.w #h'd, r5 ; set erase loop count erase: adds #1, r6 ; erase-verify fail counter + 1 mov.w #h'e, r4 ; mov.w r4, @tcsr ; start watchdog timer mov.w r5, r4 ; set erase loop counter bset #1, @flmcr:8 ; set e bit loope: nop nop nop nop subs #1, r4 ; mov.w r4, r4 ; bne loope ; wait loop bclr #1, @flmcr:8 ; clear e bit mov.w #h'a500, r4 ; mov.w r4, @tcsr ; stop watchdog timer 406 ; execute erase-verify evr: mov.w #ramstr, r2 ; starting transfer destination address (ram) mov.w #ervadr, r3 ; add.w r3, r2 ; #ramstr + #ervadr mov.w #start, r3 ; sub.w r3, r2 ; address of data area used in ram mov.b #h'00, r1l ; used to test r1l bit in r0 mov.b #h'b, r4h ; set erase-verify loop counter bset #3, @flmcr:8 ; set ev bit loopev: dec r4h ; bne loopev ; wait loop ebrtst: cmp.b #h'0c, r1l ; r1l = h'0c? beq hantei ; if finished checking all r0 bits, branch to hantei cmp.b #h'08, r1l ; bmi ebr2ev ; test ebr1 if r1l mov.b r1l, r1h ; subx #h'08, r1h ; r1l 8 btst r1h, r0h ; test r1h bit in ebr1 (r0h) bne ersevf ; if r1h bit in ebr1 (r0h) is 1, branch to ersevf bra add01 ; if r1h bit in ebr1 (r0h) is 0, branch to add01 ebr2ev: btst r1l, r0l ; test r1l bit in ebr2 (r0l) bne ersevf ; if r1l bit in ebr2 (r0h) is 1, branch to ersevf add01: inc r1l ; r1l + 1 mov.w @r2+, r3 ; dummy-increment r2 bra ebrtst ; erase1: bra erase ; branch to erase via erase 1 ersevf: mov.w @r2+, r3 ; top address of block to be erase-verified evr2: mov.b #h'ff, r1h ; mov.b r1h, @r3 ; dummy write mov.b #h'c, r4h ; set erase-verify loop counter loopep: dec r4h ; bne loopep ; wait loop mov.b @r3+, r1h ; read cmp.b #h'ff, r1h ; read data = h'ff? bne blkad ; if read data mov.w @r2, r4 ; top address of next block cmp.w r4, r3 ; last address of block? bne evr2 cmp.b #h'08, r1l bmi sbclr ; test ebr1 if r1l mov.b r1l, r1h ; subx #h'08, r1h ; r1l 8 bclr r1h, r0h ; clear r1h bit in ebr1 (r0h) bra blkad sbclr: bclr r1l, r0l ; clear r1l bit in ebr2 (r0l) blkad: inc r1l ; r1l + 1 bra ebrtst ; hantei: bclr #3, @flmcr:8 ; clear ev bit mov.w r0, @ebr1 ; beq eowari ; if ebr1/ebr2 is all 0, erasing ended normally 407 brer: mov.w #h'0bb8, r4 ; cmp.w r4, r6 ; erase-verify executed 3000 times? bne erase1 ; if erase-verify not executed 3000 times, erase again bra abend2 ; if erase-verify executed 3000 times, branch to abend2 ; < block address table used in erase-verify> .align 2 ervadr: .data.w h'0000 ; sb0 .data.w h'0080 ; sb1 .data.w h'0100 ; sb2 .data.w h'0180 ; sb3 .data.w h'0200 ; sb4 .data.w h'0400 ; sb5 .data.w h'0800 ; sb6 .data.w h'0c00 ; sb7 .data.w h'1000 ; lb0 .data.w h'2000 ; lb1 .data.w h'4000 ; lb2 .data.w h'6000 ; lb3 .data.w h'8000 ; flash end eowari: erase end abend2: erase error loop counter values in programs and watchdog timer overflow interval settings: the setting of #a, #b, #c, #d, and #e values in the programs depends on the clock frequency. tables 19.9 (1) and (2) indicate sample loop counter settings for typical clock frequencies. however, #e is set according to table 19.10. as a software loop is used, calculated values including percent errors may not be the same as actual values. therefore, the values are set so that the total programming time and total erase time do not exceed 1 ms and 30 s, respectively. the maximum number of writes in the program, n, is set to 50. programming and erasing in accordance with the flowcharts is achieved by setting #a, #b, #c, and #d in the programs as shown in tables 19.9 (1) and (2). #e should be set as shown in table 19.10. wait state insertion is inhibited in these programs. if wait states are to be used, the setting should be made after the program ends. the setting value for the watchdog timer (wdt) overflow time is calculated based on the number of instructions between starting and stopping of the wdt, including the write time and erase time. therefore, no other instructions should be added between starting and stopping of the wdt in this program example. 408 table 19.9 (1) #a, #b, #c, and #d setting values for typical clock frequencies with program running in the on-chip memory (ram) clock frequency f = 16 mhz f = 10 mhz f = 8 mhz f = 2 mhz variable time setting counter setting value counter setting value counter setting value counter setting value a (f) programming time 20 table 19.9 (2) #a, #b, #c, and #d setting values for typical clock frequencies with program running in the external device clock frequency f = 16 mhz f = 10 mhz f = 8 mhz f = 2 mhz variable time setting counter setting value counter setting value counter setting value counter setting value a (f) programming time 20 409 formula: when using a clock frequency not shown in tables 19.9 (1) and (2), follow the formula below. the calculation is based on a clock frequency of 10 mhz. after calculating a(f) and d(f) in the decimal system, omit the first decimal figures, and convert them to the hexadecimal system, so that a(f) and d(f) are set to 20 table 19.10 watchdog timer overflow interval settings (#e setting value according to clock frequency) variable clock frequency [mhz] e (f) 10 mhz 410 19.4.7 prewrite verify mode prewrite-verify mode is a verify mode used when programming all bits to equalize their threshold voltages before erasing them. program all flash memory to h'00 by writing h'00 using the prewrite algorithm shown in figure 19.10. h'00 should also be written when using ram for flash memory emulation (when prewriting a ram area). (this also applies when using ram to emulate flash memory erasing with an emulator or other support tool.) after the necessary programming time has elapsed, exit program mode (by clearing the p bit to 0) and select prewrite-verify mode (leave the p, e, pv, and ev bits all cleared to 0). in prewrite-verify mode, a prewrite-verify voltage is applied to the memory cells at the read address. if the flash memory is read in this state, the data at the read address will be read. after selecting prewrite-verify mode, wait 4 19.4.8 protect modes flash memory can be protected from programming and erasing by software or hardware methods. these two protection modes are described below. software protection: prevents transitions to program mode and erase mode even if the p or e bit is set in the flash memory control register (flmcr). details are as follows. function protection description program erase verify * 1 block protect individual blocks can be protected from erasing and programming by the erase block registers (ebr1 and ebr2). if h'f0 is set in ebr1 and h'00 in ebr2, all blocks are protected from erasing and programming. disabled disabled enabled emulation protect * 2 when the rams or ram0 bit, but not both, is set in the wait-state control register (wscr), all blocks are protected from programming and erasing. disabled disabled * 3 enabled notes: * 1 three modes: program-verify, erase-verify, and prewrite-verify. * 2 except in ram areas overlapped onto flash memory. * 3 all blocks are erase-disabled. it is not possible to specify individual blocks. 411 hardware protection: suspends or disables the programming and erasing of flash memory, and resets the flash memory control register (flmcr) and erase block registers (ebr1 and ebr2). details of hardware protection are as follows. function protection description program erase verify * 1 programing voltage (v pp ) protect when 12 v is not applied to the fv pp pin, flmcr, ebr1, and ebr2 are initialized, disabling programming and erasing. to obtain this protection, v pp should not exceed v cc . * 3 disabled disabled * 2 disabled reset and standby protect when a reset occurs (including a watchdog timer reset) or standby mode is entered, flmcr, ebr1, and ebr2 are initialized, disabling programming and erasing. note that res res ) during operation. disabled disabled * 2 disabled interrupt protect to prevent damage to the flash memory, if interrupt input occurs while flash memory is being programmed or erased, programming or erasing is aborted immediately. the settings in flmcr, ebr1, and ebr2 are retained. this type of protection can be cleared only by a reset. disabled disabled * 2 enabled notes: * 1 three modes: program-verify, erase-verify, and prewrite-verify. * 2 all blocks are erase-disabled. it is not possible to specify individual blocks. * 3 for details, see section 19.7, flash memory programming and erasing precautions. 19.4.9 interrupt handling during flash memory programming and erasing if an interrupt occurs *1 while flash memory is being programmed or erased (while the p or e bit of flmcr is set), the following operating states can occur. ? ? 412 for nmi interrupts while flash memory is being programmed or erased, these malfunction and runaway problems can be prevented by using the ram overlap function with the settings described below. 1. do not store the nmi interrupt-handling routine *3 in the flash memory area (h'0000 to h'7fff). store it elsewhere (in ram, for example). 2. set the nmi interrupt vector in address h'fc06 in ram (corresponding to h'0006 in flash memory). 3. after the above settings, set both the rams and ram0 bits to 1 in wscr. *4 due to the setting of step 3, if an interrupt signal is input while 12 v is applied to the fv pp pin, the ram overlap function is enabled and part of the ram (h'fc00 to h'fc7f) is overlapped onto the small-block area of flash memory (h'0000 to h'007f). as a result, when an interrupt is input, the vector is read from ram, not flash memory, so the interrupt is handled normally even if flash memory is being programmed or erased. this can prevent malfunction and runaway. notes: *1 when the interrupt mask bit (i) of the condition control register (ccr) is set to 1, all interrupts except nmi are masked. for details see (2) in section 2.2.2, control registers. *2 the vector table might not be read correctly for one of the following reasons: if flash memory is read while it is being programmed or erased (while the p or e bit of flmcr is set), the correct value cannot be read. if no value has been written for the nmi entry in the vector table yet, nmi exception handling will not be executed correctly. *3 this routine should be programmed so as to prevent microcontroller runaway. *4 for details on wscr settings, see section 19.2.4, wait-state control register. notes on interrupt handling in boot mode: in boot mode, the settings described above concerning nmi interrupts are carried out, and nmi interrupt handling (but not other interrupt handling) is enabled while the boot program is executing. note the following points concerning the user program. ? ? ? ? 413 19.5 flash memory emulation by ram erasing and programming flash memory takes time, which can make it difficult to tune parameters and other data in real time. if necessary, real-time updates of flash memory can be emulated by overlapping the small-block flash-memory area with part of the ram (h'fc00 to h'fd7f). this ram reassignment is performed using bits 7 and 6 of the wait-state control register (wscr). after a flash memory area has been overlapped by ram, the ram area can be accessed from two address areas: the overlapped flash memory area, and the original ram area (h'fc00 to h'fd7f). table 19.11 indicates how to reassign ram. wait-state control register (wscr) *2 bit 76543210 rams ram0 ckdbl wms1 wms0 wc1 wc0 initial value * 1 00001000 read/write r/w r/w r/w r/w r/w r/w r/w r/w notes: * 1 wscr is initialized by a reset and in hardware standby mode. it is not initialized in software standby mode. * 2 for details of wscr settings, see section 19.2.4, wait-state control register (wscr). table 19.11 ram area selectio n bit 7: rams bit 6: ramo ram area rom area 0 0 none 1 h'fc80 to h'fcff h'0080 to h'00ff 1 0 h'fc80 to h'fd7f h'0080 to h'017f 1 h'fc00 to h'fc7f h'0000 to h'007f 414 example of emulation of real-time flash-memory update h'007f h'0080 h'00ff h'0100 h'0000 h'7fff h'fb80 h'fc80 h'fcff h'ff7f small-block area (sb1) flash memory address space overlapped ram overlapped ram on-chip ram area procedure 1. overlap part of ram (h'fc80 to h'fcff) onto the area requiring real-time update (sb1). (set wscr bits 7 and 6 to 01.) 2. perform real-time updates in the overlapping ram. 3. after finalization of the update data, clear the ram overlap (by clearing the rams and ram0 bits). 4. read the data written in ram addresses h'fc80 to h'fcff out externally, then program the flash memory area, using this data as part of the program data. figure 19.12 example of ram overlap 415 notes on use of ram emulation function ? 416 19.6 flash memory writer mode (h8/3334yf) 19.6.1 writer mode setting the on-chip flash memory of the h8/3334yf can be programmed and erased not only in the on- board programming modes but also in writer mode, using a general-purpose prom programmer. 19.6.2 socket adapter and memory map programs can be written and verified by attaching a socket adapter for the relevant package to the prom programmer. table 19.12 gives ordering information for the socket adapter. figure 19.13 shows a memory map in writer mode. figure 19.14 shows the socket adapter pin interconnections. table 19.12 socket adapter microcontroller package socket adapter hd64f3334yf16 80-pin qfp hs3334eshf1h hd64f3334ytf16 80-pin tqfp hs3334esnf1h hd64f3334ycp16 84-pin plcc hs3334escf1h h8/3334yf h'0000 h'7fff h'0000 h'7fff on-chip rom area mcu mode writer mode 1 output h'1ffff figure 19.13 memory map in writer mode 417 h8/3334yf pin name fp-80a tfp-80c cp-84 18 17 27 28 29 79 80 81 82 83 84 1 3 78 77 76 75 74 73 72 71 69 68 67 66 65 63 62 61 31, 32, 36, 37, 25 15, 16, 30, 40 42 19, 60 51 2, 4, 23, 24, 41, 64, 70 12 13, 14 7 6 15 16 17 65 66 67 68 69 70 71 72 64 63 62 61 60 59 58 57 55 54 53 52 51 50 49 48 19, 20, 24, 25, 13 4, 5, 18, 28 29 8, 47 38 12, 56, 73 1 2, 3 1 26 2 3 31 13 14 15 17 18 19 20 21 12 11 10 9 8 7 6 5 27 24 23 25 4 28 29 22 32 16 hn28f101 (32 pins) pin no. pin name v pp fa 9 fa 16 fa 15 we oe socket adapter pin no. stby nmi res oe ce we figure 19.14 wiring of socket adapter 418 19.6.3 operation in writer mode the program/erase/verify specifications in writer mode are the same as for the standard hn28f101 flash memory. however, since the h8/3334yf does not support product name recognition mode, the programmer cannot be automatically set with the device name. table 19.13 indicates how to select the various operating modes. table 19.13 operating mode selection in writer mode pins mode fv pp v cc ce oe we d 7 to d 0 a 16 to a 0 read read v cc v cc l l h data output address input output disable v cc v cc l h h high impedance standby v cc v cc h x x high impedance command read v pp v cc l l h data output write output disable v pp v cc l h h high impedance standby v pp v cc h x x high impedance write v pp v cc l h l data input note: be sure to set the fv pp pin to v cc in these states. if it is set to 0 v, hardware standby mode will be entered, even when in writer mode, resulting in incorrect operation. legend: l: low level h: high level v pp :v pp level v cc :v cc level x: don t care 419 table 19.14 writer mode commands 1st cycle 2nd cycle command cycles mode address data mode address data memory read 1 write x h'00 read ra dout erase setup/erase 2 write x h'20 write x h'20 erase-verify 2 write ea h'a0 read x evd auto-erase setup/ auto-erase 2 write x h'30 write x h'30 program setup/ program 2 write x h'40 write pa pd program-verify 2 write x h'c0 read x pvd reset 2 write x h'ff write x h'ff pa: program address ea: erase-verify address ra: read address pd: program data pvd: program-verify output data evd: erase-verify output data 420 high-speed, high-reliability programming: unused areas of the h8/3334yf flash memory contain h'ff data (initial value). the h8/3334yf flash memory uses a high-speed, high-reliability programming procedure. this procedure provides enhanced programming speed without subjecting the device to voltage stress and without sacrificing the reliability of programmed data. figure 19.15 shows the basic high-speed, high-reliability programming flowchart. tables 19.15 and 19.16 list the electrical characteristics during programming. start set v pp = 12.0 v figure 19.15 high-speed, high-reliability programming 421 high-speed, high-reliability erasing: the h8/3334yf flash memory uses a high-speed, high- reliability erasing procedure. this procedure provides enhanced erasing speed without subjecting the device to voltage stress and without sacrificing data reliability . figure 19.16 shows the basic high-speed, high-reliability erasing flowchart. tables 19.15 and 19.16 list the electrical characteristics during erasing. start program all bits to 0 * address = 0 n = 0 wait (10 ms) erase setup/erase command n + 1 figure 19.16 high-speed, high-reliability erasing 422 table 19.15 dc characteristics in writer mode (conditions: v cc = 5.0 v item symbol min typ max unit test conditions input high voltage fo 7 to fo 0 , fa 16 to fa 0 , oe ce we v cc + 0.3 v input low voltage fo 7 to fo 0 , fa 16 to fa 0 , oe ce we 0.3 0.8 v output high voltage fo 7 to fo 0 v oh 2.4 vi oh = 200 0.45 v i ol = 1.6 ma input leakage current fo 7 to fo 0 , fa 16 to fa 0 , oe ce we 2 40 80 ma program i cc 40 80 ma erase i cc 40 80 ma fv pp current read i pp 10 10 20 ma v pp = 12.6 v program i pp 20 40 ma v pp = 12.6 v erase i pp 20 40 ma v pp = 12.6 v 423 table 19.16 ac characteristics in writer mode (conditions: v cc = 5.0 v item symbol min typ max unit test conditions command write cycle t cwc 120 ns figure 19.17 address setup time t as 0 ns figure 19.18 * address hold time t ah 60 ns figure 19.19 data setup time t ds 50 ns data hold time t dh 10 ns ce ns ce ns v pp setup time t vps 100 ns v pp hold time t vph 100 ns we ns we ns oe ns oe 500 ns oe ns status polling access time t spa 120 ns program wait time t ppw 25 ns erase wait time t et 9 11 ms output disable time t df 0 40 ns total auto-erase time t aet 0.5 30 s note: ce oe we 424 auto-erase setup auto-erase and status polling address command input status polling command input command input command input 5.0 v 12 v 5.0 v v cc v pp ce oe we figure 19.17 auto-erase timing 425 t vph t vps t ceh t ces t oews t wep t ceh t ces t cwc t wep t ds t dh t ds t dh t as t ah t ppw t ces t weh t ceh t wep t oers t dh t ds t va t df command input command input data input command input command input valid data output data input program setup program program-verify valid address address 5.0 v 12 v 5.0 v v cc v pp ce oe we figure 19.18 high-speed, high-reliability programming timing 426 address 5.0 v 12 v 5.0 v v cc v pp ce oe we figure 19.19 erase timing 19.7 flash memory programming and erasing precautions read these precautions before using writer mode, on-board programming mode, or flash memory emulation by ram. (1) program with the specified voltages and timing. the rated programming voltage (v pp ) of the flash memory is 12.0 v. if the prom programmer is set to hitachi hn28f101 specifications, v pp will be 12.0 v. applying voltages in excess of the rating can permanently damage the device. take particular care to ensure that the prom programmer peak overshoot does not exceed the rated limit of 13 v. (2) before programming, check that the chip is correctly mounted in the prom programmer. overcurrent damage to the device can result if the index marks on the prom programmer socket, socket adapter, and chip are not correctly aligned. (3) don? touch the socket adapter or chip while programming. touching either of these can cause contact faults and write errors. 427 (4) set h'ff as the prom programmer buffer data for addresses h'8000 to h'1ffff. the h8/3334yf prom size is 32 kbytes. addresses h'8000 to h'1ffff always read h'ff, so if h'ff is not specified as programmer data, a verify error will occur. (5) notes on applying, releasing, and shutting *1 off the programming voltage (v pp ) ? ? s v cc voltage is not within the rated voltage range (v cc = 2.7 to 5.5 v) *2 , since microcontroller operation is unstable, the flash memory may be programmed or erased by mistake. this can occur even if v cc = 0 v. to prevent changes in the v cc power supply when v pp is applied, be sure that the power supply is adequately decoupled by inserting bypass capacitors. ? res ? res ). ? 428 ? ? ? 429 t osc1 2.7 to 5.5 v * 12 (when res v cc v pp v pp res figure 19.20 v pp power-on and power-off timing (6) do not apply 12 v to the fv pp pin during normal operation. to prevent accidental programming or erasing due to microcontroller program runaway etc., apply 12 v to the v pp pin only when the flash memory is programmed or erased, or when flash memory is emulated by ram. overprogramming or overerasing due to program runaway can cause memory cells to malfunction. avoid system configurations in which 12 v is always applied to the fv pp pin. while 12 v is applied, the watchdog timer should be running and enabled to halt runaway program execution, so that program runaway will not lead to overprogramming or overerasing. 430 (7) design a current margin into the programming voltage (v pp ) power supply. ensure that v pp will not depart from 12.0 (8) ensure that peak overshoot does not exceed the rated value at the fv pp and md 1 pins. connect decoupling capacitors as close to the fv pp and md 1 pins as possible. also connect decoupling capacitors to the md 1 pin in the same way when boot mode is uesd. 0.01 figure 19.21 v pp power supply circuit design (example) (9) use the recommended algorithms for programming and erasing flash memory. these algorithms are designed to program and erase without subjecting the device to voltage stress and without sacrificing the reliability of programmed data. before setting the program (p) or erase (e) bit in the flash memory control register (flmcr), set the watchdog timer to ensure that the p or e bit does not remain set for more than the specified time. (10) for details on interrupt handling while flash memory is being programmed or erased, see the notes on nmi interrupt handling in section 19.4.9, interrupt handling during flash memory programming and erasing. 431 (11) cautions on accessing flash memory control registers 1. flash memory control register access state in each operating mode the h8/3334yf has flash memory control registers located at addresses h'ff80 (flmcr), h'ff82 (ebr1), and h'ff83 (ebr2). these registers can only be accessed when 12 v is applied to the flash memory program power supply pin, fv pp . table 19.17 shows the area accessed for the above addresses in each mode, when 12 v is and is not applied to fv pp . table 19.17 area accessed in each mode with 12v applied and not applied to fv pp mode 1 mode 2 mode 3 12 v applied to fv pp register reserved area (always h'ff) flash memory control register (initial value h'80) flash memory control (initial value h'80) 12 v not applied to fv pp external address space external address space reserved area (always h'ff) 2. when a flash memory control register is accessed in mode 2 (expanded mode with on-chip rom enabled) when a flash memory control register is accessed in mode 2, it can be read or written to if 12 v is being applied to fv pp , but if not, external address space will be accessed. it is therefore essential to confirm that 12 v is being applied to the fv pp pin before accessing these registers. 3. to check for 12 v application/non-application in mode 3 (single-chip mode) when address h'ff80 is accessed in mode 3, if 12 v is being applied to fv pp , flmcr is read/written to, and its initial value after reset is h'80. when 12 v is not being applied to fv pp , flmcr is a reserved area that cannot be modified and always reads h'ff. since bit 7 (corresponding to the v pp bit) is set to 1 at this time regardless of whether 12 v is applied to fv pp , application or release of 12 v to fv pp cannot be determined simply from the 0 or 1 status of this bit. a byte data comparison is necessary to check whether 12 v is being applied. the relevant coding is shown below. . . . label1: mov.b @h'ff80, r1l cmp.b #h'ff, r1l beq label1 . . . sample program for detection of 12 v application to fv pp (mode 3) 432 table 19.18 dc characteristics of flash memory conditions: v cc = 2.7 v to 5.5 v *2 , av cc = 2.7 v to 5.5 v *2 ,v ss = av ss = 0 v, v pp = 12.0 20 40 item symbol min typ max unit test conditions high-voltage (12 v) threshold level * 1 fv pp , md 1 v h v cc + 2 11.4 v fv pp current during read i pp 10 10 20 ma v pp = 12.6 v during programming 20 40 ma during erasure 20 40 ma notes: * 1 the listed voltages indicate the threshold level at which high-voltage application is recognized. in boot mode and while flash memory is being programmed or erased, the applied voltage should be 12.0 v table 19.19 ac characteristics of flash memory conditions: v cc = 2.7 v to 5.5 v *5 , av cc = 2.7 v to 5.5 v *5 , v ss = av ss = 0 v, v pp = 12.0 20 40 item symbol min typ max unit test conditions programming time * 1, * 2 t p 50 1000 130s number of writing/erasing count n wec 100 times verify setup time 1 * 1 t vs1 4 v cc < 4.5 v notes: * 1 set the times following the programming/erasing algorithm shown in section 19. * 2 the programming time is the time during which a byte is programmed or the p bit in the flash memory control register (flmcr) is set. it does not include the program-verify time. * 3 the erase time is the time during which all 32-kbyte blocks are erased or the e bit in the flash memory control register (flmcr) is set. it does not include the prewrite time before erasure or erase-verify time. * 4 after power-on when using an external clock source, after return from standby mode, or after switching the programming voltage (v pp ) from 12 v to v cc , make sure that this read setup time has elapsed before reading flash memory. when v pp is released, the flash memory read setup time is defined as the period from when the fv pp pin has reached v cc + 2 v until flash memory can be read. * 5 in the lh version, v cc = 3.0 v to 5.5 v, av cc = 3.0 v to 5.5 v. 433 section 20 rom (60-kbyte dual-power-supply flash memory version) 20.1 flash memory overview 20.1.1 flash memory operating principle table 20.1 illustrates the principle of operation of the h8/3337yf? on-chip flash memory. like eprom, flash memory is programmed by applying a high gate-to-drain voltage that draws hot electrons generated in the vicinity of the drain into a floating gate. the threshold voltage of a programmed memory cell is therefore higher than that of an erased cell. cells are erased by grounding the gate and applying a high voltage to the source, causing the electrons stored in the floating gate to tunnel out. after erasure, the threshold voltage drops. a memory cell is read like an eprom cell, by driving the gate to the high level and detecting the drain current, which depends on the threshold voltage. erasing must be done carefully, because if a memory cell is overerased, its threshold voltage may become negative, causing the cell to operate incorrectly. section 20.4.6 shows an optimal erase control flowchart and sample program. table 20.1 principle of memory cell operation program erase read memory cell vd vg = v pp open vs = v pp vd vg memory array vd 0 v v pp 0 v 0 v open open 0 v v pp 0 v vd 0 v v cc 0 v 0 v 434 20.1.2 mode programming and flash memory address space as its on-chip rom, the h8/3337yf has 60 kbytes of flash memory. the flash memory is connected to the cpu by a 16-bit data bus. the cpu accesses both byte data and word data in two states. the h8/3337yf? flash memory is assigned to addresses h'0000 to h'ef7f in mode2, and addresses h'0000 to h'f77f in mode3. the mode pins enable either on-chip flash memory or external memory to be selected for this area. table 20.2 summarizes the mode pin settings and usage of the memory area. table 20.2 mode pin settings and flash memory area mode pin setting mode md 1 md 0 memory area usage mode 0 0 0 illegal setting mode 1 0 1 external memory area mode 2 1 0 on-chip flash memory area (h'0000 to h'ef7f) mode 3 1 1 on-chip flash memory area (h'0000 to h'f77f) 20.1.3 features features of the flash memory are listed below. ? five flash memory operating modes the flash memory has five operating modes: program mode, program-verify mode, erase mode, erase-verify mode, and prewrite-verify mode. ? block erase designation blocks to be erased in the flash memory address space can be selected by bit settings. the address space includes a large-block area (eight blocks with sizes from 2 kbytes to 12 kbytes) and a small-block area (eight blocks with sizes from 128 bytes to 1 kbyte). ? program and erase time programming one byte of flash memory typically takes 50 s, while erasing typically takes 1 s. ? erase-program cycles flash memory contents can be erased and reprogrammed up to 100 times. ? on-board programming modes these modes can be used to program, erase, and verify flash memory contents. there are two modes: boot mode and user programming mode. 435 ? automatic bit-rate alignment in boot-mode data transfer, the h8/3337yf aligns its bit rate automatically to the host bit rate (maximum 9600 bps). ? flash memory emulation by ram part of the ram area can be overlapped onto flash memory, to emulate flash memory updates in real time. ? writer mode as an alternative to on-board programming, the flash memory can be programmed and erased in writer mode, using a general-purpose prom programmer. program, erase, verify, and other specifications are the same as for hn28f101 standard flash memory. 20.1.4 block diagram figure 20.1 shows a block diagram of the flash memory. flmcr ebr1 ebr2 h'0000 h'0002 h'0004 h'f77c h'f77e h'0001 h'0003 h'0005 h'f77d h'f77f md 1 md 0 internal data bus (upper) internal data bus (lower) bus interface and control section operating mode on-chip flash memory (60 kbytes) upper byte (even address) lower byte (odd address) legend: flmcr: ebr1: ebr2: flash memory control register erase block register 1 erase block register 2 8 8 figure 20.1 flash memory block diagram 436 20.1.5 input/output pins flash memory is controlled by the pins listed in table 20.3. table 20.3 flash memory pins pin name abbreviation input/output function programming power fv pp power supply apply 12.0 v mode 1 md 1 input h8/3337yf operating mode setting mode 0 md 0 input h8/3337yf operating mode setting transmit data txd 1 output sci1 transmit data output receive data rxd 1 input sci1 receive data input the transmit data and receive data pins are used in boot mode. 20.1.6 register configuration the flash memory is controlled by the registers listed in table 20.4. table 20.4 flash memory registers name abbreviation r/w initial value address flash memory control register flmcr r/w * 2 h'00 * 2 h'ff80 erase block register 1 ebr1 r/w * 2 h'00 * 2 h'ff82 erase block register 2 ebr2 r/w * 2 h'00 * 2 h'ff83 wait-state control register * 1 wscr r/w h'08 h'ffc2 notes: * 1 the wait-state control register controls the insertion of wait states by the wait-state controller, frequency division of clock signals for the on-chip supporting modules by the clock pulse generator, and emulation of flash-memory updates by ram in on-board programming mode. * 2 in modes 2 and 3 (on-chip flash memory enabled), the initial value is h'00 for flmcr, ebr1 and ebr2. in mode 1 (on-chip flash memory disabled), these registers cannot be modified and always read h'ff. registers flmcr, ebr1, and ebr2 are only valid when writing to or erasing flash memory, and can only be accessed while 12 v is being applied to the fv pp pin. when 12 v is not applied to the fv pp pin, in mode 2 addresses h'ff80 to h'ff83 are external address space, and in mode 3 these addresses cannot be modified and always read h'ff. 437 20.2 flash memory register descriptions 20.2.1 flash memory control register (flmcr) flmcr is an 8-bit register that controls the flash memory operating modes. transitions to program mode, erase mode, program-verify mode, and erase-verify mode are made by setting bits in this register. flmcr is initialized to h'00 by a reset, in the standby modes, and when 12 v is not applied to fv pp . when 12 v is applied to the fv pp pin, a reset or entry to a standby mode initializes flmcr to h'80. bit 76543210 v pp evpve p initial value 0 0 0 0 0 0 0 0 read/write r r/w * r/w * r/w * r/w * note: * the initial value is h'00 in modes 2 and 3 (on-chip flash memory enabled). in mode 1 (on- chip flash memory disabled), this register cannot be modified and always reads h'ff. for information on accessing this register, refer to in section 20.7, flash memory programming and erasing precautions (11). bit 7?rogramming power (v pp ): this status flag indicates that 12 v is applied to the fv pp pin. refer to section 20.7, flash memory programming and erasing precautions (5), for details on use. bit 7: v pp description 0 cleared when 12 v is not applied to fv pp (initial value) 1 set when 12 v is applied to fv pp bits 6 to 4?eserved: these bits cannot be modified, and are always read as 0. bit 3?rase-verify mode (ev): *1 selects transition to or exit from erase-verify mode. bit 3: ev description 0 exit from erase-verify mode (initial value) 1 transition to erase-verify mode bit 2?rogram-verify mode (pv): *1 selects transition to or exit from program-verify mode. bit 2: pv description 0 exit from program-verify mode (initial value) 1 transition to program-verify mode 438 bit 1?rase mode (e): *1, *2 selects transition to or exit from erase mode. bit 1: e description 0 exit from erase mode (initial value) 1 transition to erase mode bit 0?rogram mode (p): *1, *2 selects transition to or exit from program mode. bit 0: p description 0 exit from program mode (initial value) 1 transition to program mode notes: *1 do not set two or more of these bits simultaneously. do not release or shut off the v cc or v pp power supply when these bits are set. *2 set the p or e bit according to the instructions given in section 20.4, programming and erasing flash memory. set the watchdog timer beforehand to make sure that these bits do not remain set for longer than the specified times. for notes on use, see section 20.7, flash memory programming and erasing precautions. 20.2.2 erase block register 1 (ebr1) ebr1 is an 8-bit register that designates large flash-memory blocks for programming and erasure. ebr1 is initialized to h'00 by a reset, in the standby modes, and when 12 v is not applied to the fv pp pin. when a bit in ebr1 is set to 1, the corresponding block is selected and can be programmed and erased. figure 20.2 and table 20.6 show details of a block map. bit 76543210 lb7 lb6 lb5 lb4 lb3 lb2 lb1 lb0 initial value * 1 00000000 read/write r/w * 1, * 2 r/w * 1 r/w * 1 r/w * 1 r/w * 1 r/w * 1 r/w * 1 r/w * 1 notes: * 1 the initial value is h'00 in modes 2 and 3 (on-chip rom enabled). in mode 1 (on-chip rom disabled), this register cannot be modified and always reads h'ff. * 2 this bit cannot be modified mode 2. for information on accessing this register, refer to in section 20.7, flash memory programming and erasing precautions (11). 439 bits 7 to 0?arge block 7 to 0 (lb7 to lb0): these bits select large blocks (lb7 to lb0) to be programmed and erased. bits 7 to 0: lb7 to lb0 description 0 block (lb7 to lb0) is not selected (initial value) 1 block (lb7 to lb0) is selected 20.2.3 erase block register 2 (ebr2) ebr2 is an 8-bit register that designates small flash-memory blocks for programming and erasure. ebr2 is initialized to h'00 by a reset, in the standby modes, and when 12 v is not applied to the fv pp pin. when a bit in ebr2 is set to 1, the corresponding block is selected and can be programmed and erased. figure 20.2 and table 20.6 show a block map. bit 76543210 sb7 sb6 sb5 sb4 sb3 sb2 sb1 sb0 initial value * 00000000 read/write r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * note: * the initial value is h'00 in modes 2 and 3 (on-chip rom enabled). in mode 1 (on-chip rom disabled), this register cannot be modified and always reads h'ff. for information on accessing this register, refer to in section 20.7, flash memory programming and erasing precautions (11). bits 7 to 0?mall block 7 to 0 (sb7 to sb0): these bits select small blocks (sb7 to sb0) to be programmed and erased. bits 7 to 0: sb7 to sb0 description 0 block (sb7 to sb0) is not selected (initial value) 1 block (sb7 to sb0) is selected 440 20.2.4 wait-state control register (wscr) wscr is an 8-bit readable/writable register that enables flash-memory updates to be emulated in ram. it also controls frequency division of clock signals supplied to the on-chip supporting modules and insertion of wait states by the wait-state controller. wscr is initialized to h'08 by a reset and in hardware standby mode. it is not initialized in software standby mode. bit 76543210 rams ram0 ckdbl wms1 wms0 wc1 wc0 initial value 0 0 0 0 1 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w bits 7 and 6?am select and ram0 (rams and ram0): these bits are used to reassign an area to ram (see table 20.5). these bits are write-enabled and their initial value is 0. they are initialized by a reset and in hardware standby mode. they are not initialized in software standby mode. if only one of bits 7 and 6 is set, part of the ram area can be overlapped onto the small-block flash memory area. in that case, access is to ram, not flash memory, and all flash memory blocks are write/erase-protected (emulation protect *1 ). in this state, the mode cannot be changed to program or erase mode, even if the p bit or e bit in the flash memory control register (flmcr) is set (although verify mode can be selected). therefore, clear both of bits 7 and 6 before programming or erasing the flash memory area. if both of bits 7 and 6 are set, part of the ram area can be overlapped onto the small-block flash memory area, but this overlapping begins only when an interrupt signal is input while 12 v is being applied to the fv pp pin. up until that point, flash memory is accessed. use this setting for interrupt handling while flash memory is being programmed or erased. *2 table 20.5 ram area reassignment *3 bit 7: rams bit 6: ram0 ram area rom area 0 0 none 1 h'f880 to h'f8ff h'0080 to h'00ff 1 0 h'f880 to h'f97f h'0080 to h'017f 1 h'f800 to h'f87f h'0000 to h'007f 441 bit 5?lock double (ckdbl): controls frequency division of clock signals supplied to the on- chip supporting modules. for details, see section 6, clock pulse generator. bit 4?eserved: this bit is reserved, but it can be written and read. its initial value is 0. bits 3 and 2?ait mode select 1 and 0 (wms1, wms0) bits 1 and 0?ait count 1 and 0 (wc1, wc0) these bits control insertion of wait states by the wait-state controller. for details, see section 5, wait-state controller. notes: *1 for details on emulation protect, see section 20.4.8, protect modes. *2 for details on interrupt handling during programming and erasing of flash memory, see section 20.4.9, interrupt handling during flash memory programming and erasing. *3 ram area that overlaps flash memory. 442 h'0000 h'01ff h'0200 h'03ff h'0400 h'07ff h'0800 h'0bff h'0c00 h'0fff h'0000 h'0fff h'1000 h'1fff h'2000 h'3fff h'4000 h'5fff h'6000 h'9fff h'a000 h'bfff h'c000 h'ef7f h'ef80 h'7fff h'8000 h'f77f small block area (4 kbytes) large block area (58 kbytes) sb7 to sb0 4 kbytes lb0 4 kbytes lb1 8 kbytes lb7 2 kbytes sb0 128 bytes sb1 128 bytes sb2 128 bytes sb3 128 bytes lb2 8 kbytes lb3 8 kbytes sb4 512 bytes sb5 1 kbyte sb6 1 kbyte sb7 1 kbyte lb4 8 kbytes lb5 8 kbytes lb6 12 kbytes figure 20.2 erase block map 443 table 20.6 erase blocks and corresponding bits register bit block address size ebr1 0 lb0 h'1000 to h'1fff 4 kbytes 1 lb1 h'2000 to h'3fff 8 kbytes 2 lb2 h'4000 to h'5fff 8 kbytes 3 lb3 h'6000 to h'7fff 8 kbytes 4 lb4 h'8000 to h'9fff 8 kbytes 5 lb5 h'a000 to h'bfff 8 kbytes 6 lb6 h'c000 to h'ef7f 12 kbytes 7 lb7 h'ef80 to h'f77f 2 kbytes ebr2 0 sb0 h'0000 to h'007f 128 bytes 1 sb1 h'0080 to h'00ff 128 bytes 2 sb2 h'0100 to h'017f 128 bytes 3 sb3 h'0180 to h'01ff 128 bytes 4 sb4 h'0200 to h'03ff 512 bytes 5 sb5 h'0400 to h'07ff 1 kbyte 6 sb6 h'0800 to h'0bff 1 kbyte 7 sb7 h'0c00 to h'0fff 1 kbyte 20.3 on-board programming modes when an on-board programming mode is selected, the on-chip flash memory can be programmed, erased, and verified. there are two on-board programming modes: boot mode, and user programming mode. these modes are selected by inputs at the mode pins (md 1 and md 0 ) and fv pp pin. table 20.7 indicates how to select the on-board programming modes. for details on applying voltage v pp , refer to section 20.7, flash memory programming and erasing precautions (5). 444 table 20.7 on-board programming mode selection mode selections fv pp md 1 md 0 notes boot mode mode 2 12 v * 12 v * 0 0: v il mode 3 12 v * 1 1: v ih user programming mode 2 1 0 mode mode 3 1 1 note: * for details on the timing of 12 v application, see notes 6 to 8 in the notes on use of boot mode at the end of this section. in boot mode, the mode control register (mdcr) can be used to monitor the mode (mode 2 or 3) in the same way as in normal mode. example: set the mode pins for mode 2 boot mode (md 1 = 12 v, md 0 = 0 v). if the mode select bits of mdcr are now read, they will indicate mode 2 (mds1 = 1, mds0 = 0). 20.3.1 boot mode to use boot mode, a user program for programming and erasing the flash memory must be provided in advance on the host machine (which may be a personal computer). serial communication interface channel 1 is used in asynchronous mode. if the h8/3337yf is placed in boot mode, after it comes out of reset, a built-in boot program is activated. this program starts by measuring the low period of data transmitted from the host and setting the bit rate register (brr) accordingly. the h8/3337yf? built-in serial communication interface (sci) can then be used to download the user program from the host machine. the user program is stored in on-chip ram. after the program has been stored, execution branches to address h'f7e0 in the on-chip ram, and the program stored on ram is executed to program and erase the flash memory. figure 20.4 shows the boot-mode execution procedure. host receive data to be programmed transmit verification data h8/3337yf rxd 1 txd 1 sci figure 20.3 boot-mode system configuration 445 boot-mode execution procedure: figure 20.4 shows the boot-mode execution procedure. start program h8/3337yf pins for boot mode, and reset host transmits h'00 data continuously at desired bit rate h8/3337yf measures low period of h'00 data transmitted from host h8/3337yf computes bit rate and sets bit rate register after completing bit-rate alignment, h8/3337yf sends one h'00 data byte to host to indicate that alignment is completed host checks that this byte, indicating completion of bit-rate alignment, is received normally, then transmits one h'55 byte after receiving h'55, h8/3337yf sends part of the boot program to ram h8/3337yf transfers one user program byte to ram * 2 h8/3337yf calculates number of bytes left to be transferred (n = n 1) all bytes transferred? (n = 0?) all data = h'ff? * 4 erase all flash memory blocks * 3, * 4 after transferring the user program to ram, h8/3337yf tr ansmits one h'aa data byte to host no yes yes no 1 2 3 4 5 6 7 9 h8/3337yf branches to the ram boot area (h'f800 to h'ff2f), then checks the data in the user area of flash memory h8/3337yf receives two bytes indicating byte length (n) of program to be downloaded to on-chip ram * 1 8 after checking that all data in flash memory is h'ff, h8/3337yf transmits one h'aa data byte to host h8/3337yf br anches to h'f7e0 in ram area and executes user program downloaded into ram 10 1. program the h8/3337yf pins for boot mode, and start the h8/3337yf from a reset. 2. set the host s data format to 8 bits + 1 stop bit, select the desired bit rate (2400, 4800, or 9600 bps), and transmit h'00 data continuously. 3. the h8/3337yf repeatedly measures the low period of the rxd1 pin and calculates the host s asynchronous- communication bit rate. 4. when sci bit-rate alignment is completed, the h8/3337yf transmits one h'00 data byte to indicate completion of alignment. 5. the host should receive the byte transmitted from the h8/3337yf to indicate that bit-rate alignment is completed, check that this byte is received normally, then transmit one h'55 byte. 6. after receiving h'55, h8/3337yf sends part of the boot program to h'f780 to h'f7df and h'f800 to h'ff2f of ram. 7. after branching to the boot program area (h'f800 to h'ff2f) in ram, the h8/3337yf checks whether the flash memory already contains any programmed data. if so, all blocks are erased. 8. after the h8/3337yf transmits one h'aa data byte, the host transmits the byte length of the user program to be transferred to the h8/3337yf. the byte length must be sent as two-byte data, upper byte first and lower byte second. after that, the host proceeds to transmit the user program. as verification, the h8/3337yf echoes each byte of the received byte-length data and user program back to the host. 9. the h8/3337yf stores the received user program in on- chip ram in a 1934-byte area from h'f7e0 to h'ff6d. 10. after transmitting one h'aa data byte, the h8/3337yf branches to address h'f7e0 in on-chip ram and executes the user program stored in the area from h'f7e0 to h'ff6d. notes: * 1 the user can use 1934 bytes of ram. the number of bytes transferred must not exceed 1934 bytes. be sure to transmit the byte length in two bytes, upper byte first and lower byte second. for example, if the byte length of the program to be transferred is 256 bytes (h'0100), transmit h'01 as the upper byte, followed by h'00 as the lower byte. * 2 the part of the user program that controls the flash memory should be coded according to the flash memory write/erase algorithms given later. * 3 if a memory cell malfunctions and cannot be erased, the h8/3337yf transmits one h'ff byte to report an erase error, halts erasing, and halts further operations. * 4h 0000 to h'ef7f in mode2 and h'0000 to h'f77f in mode 3. figure 20.4 boot mode flowchart 446 automatic alignment of sci bit rate d0 d1 d2 d3 d4 d5 d6 d7 start bit stop bit this low period (9 bits) is measured (h'00 data) high for at least 1 bit figure 20.5 measurement of low period in data transmitted from host when started in boot mode, the h8/3337yf measures the low period in asynchronous sci data transmitted from the host (figure 20.5). the data format is eight data bits, one stop bit, and no parity bit. from the measured low period (9 bits), the h8/3337yf computes the host s bit rate. after aligning its own bit rate, the h8/3337yf sends the host 1 byte of h'00 data to indicate that bit-rate alignment is completed. the host should check that this alignment-completed indication is received normally and send one byte of h'55 back to the h8/3337yf. if the alignment-completed indication is not received normally, the h8/3337yf should be reset, then restarted in boot mode to measure the low period again. there may be some alignment error between the host s and h8/3337yf s bit rates, depending on the host s bit rate and the h8/3337yf s system clock frequency. to have the sci operate normally, set the host s bit rate to 2400, 4800, or 9600 bps *1 . table 20.8 lists typical host bit rates and indicates the clock-frequency ranges over which the h8/3337yf can align its bit rate automatically. boot mode should be used within these frequency ranges *2 . table 20.8 system clock frequencies permitting automatic bit-rate alignment by h8/3337yf host bit rate * 1 system clock frequencies permitting automatic bit-rate alignment by h8/3337yf 9600 bps 8 mhz to 16 mhz 4800 bps 4 mhz to 16 mhz 2400 bps 2 mhz to 16 mhz notes: * 1 use a host bit rate setting of 2400, 4800, or 9600 bps only. no other setting should be used. * 2 although the h8/3337yf may also perform automatic bit-rate alignment with bit rate and system clock combinations other than those shown in table 20.8, there will be a slight difference between the bit rates of the host and the h8/3337yf, and subsequent transfer will not be performed normally. therefore, only a combination of bit rate and system clock frequency within one of the ranges shown in table 20.8 can be used for boot mode execution. 447 ram area allocation in boot mode: in boot mode, the 96 bytes from h'f780 to h'f7df and the 18 bytes from h'ff6e to h'ff7f are reserved for use by the boot program, as shown in figure 20.6. the user program is transferred into the area from h'f7e0 to h'ff6d (1934 bytes). the boot program area can be used after the transition to execution of the user program transferred into ram. if a stack area is needed, set it within the user program. user program transfer area (1934 bytes) boot program area * (18 bytes) boot program area * (96 bytes) h'f780 h'f7e0 h'ff6e h'ff7f note: * this area cannot be used until the h8/3337yf starts to execute the user program transferred to ram (until it has branched to h'f7e0 in ram). note that even after the branch to the user program, the boot program area (h'f780 to h'f7df, h'ff6e to h'ff7f) still contains the boot program. note also that 16 bytes (h'f780 to h'f78f) of this area cannot be used if an interrupt handling routine is executed within the boot program. for details see section 20.4.9, interrupt handling during flash memory programming and erasing. figure 20.6 ram areas in boot mode 448 notes on use of boot mode 1. when the h8/3337yf comes out of reset in boot mode, it measures the low period of the input at the sci s rxd 1 pin. the reset should end with rxd 1 high. after the reset ends, it takes about 100 states for the h8/3337yf to get ready to measure the low period of the rxd 1 input. 2. in boot mode, if any data has been programmed into the flash memory (if all data *3 is not h'ff), all flash memory blocks are erased. boot mode is for use when user programming mode is unavailable, e.g. the first time on-board programming is performed, or if the update program activated in user programming mode is accidentally erased. 3. interrupts cannot be used while the flash memory is being programmed or erased. 4. the rxd 1 and txd 1 pins should be pulled up on-board. 5. before branching to the user program (at address h'f7e0 in the ram area), the h8/3337yf terminates transmit and receive operations by the on-chip sci (by clearing the re and te bits of the serial control register to 0 in channel 1), but the auto-aligned bit rate remains set in bit rate register brr. the transmit data output pin (txd 1 ) is in the high output state (in port 8, the bits p8 4 ddr of the port 8 data direction register and p8 4 dr of the port 8 data register are set to 1). at this time, the values of general registers in the cpu are undetermined. thus these registers should be initialized immediately after branching to the user program. especially in the case of the stack pointer, which is used implicitly in subroutine calls, the stack area used by the user program should be specified. there are no other changes to the initialized values of other registers. 6. boot mode can be entered by starting from a reset after 12 v is applied to the md 1 and fv pp pins according to the mode setting conditions listed in table 20.7. note the following points when turning the v pp power on. when reset is released (at the rise from low to high), the h8/3337yf checks for 12-v input at the md 1 and fv pp pins. if it detects that these pins are programmed for boot mode, it saves that status internally. the threshold point of this voltage-level check is in the range from approximately v cc + 2 v to 11.4 v, so boot mode will be entered even if the applied voltage is insufficient for programming or erasure (11.4 v to 12.6 v). when the boot program is executed, the v pp power supply must therefore be stabilized within the range of 11.4 v to 12.6 v before the branch to the ram area occurs. see figure 20.20. make sure that the programming voltage v pp does not exceed 12.6 v during the transition to boot mode (at the reset release timing) and does not go outside the range of 12 v 449 addition, make sure that v pp is not released or shut off while the boot program is executing or the flash memory is being programmed or erased. *1 boot mode can be released by driving the reset pin low, waiting at least ten system clock cycles, then releasing the application of 12 v to the md 1 and fv pp pins and releasing the reset. the settings of external pins must not change during operation in boot mode. during boot mode, if input of 12 v to the md 1 pin stops but no reset input occurs at the res pin, the boot mode state is maintained within the chip and boot mode continues (but do not stop applying 12 v to the fv pp pin during boot mode *1 ). if a watchdog timer reset occurs during boot mode, this does not release the internal mode state, but the internal boot program is restarted. therefore, to change from boot mode to another mode, the boot-mode state within the chip must be released by a reset input at the res res s operating mode will affect the bus control output signals ( as rd wr 450 20.3.2 user programming mode when set to user programming mode, the h8/3337yf can erase and program its flash memory by executing a user program. on-board updates of the on-chip flash memory can be carried out by providing on-board circuits for supplying v pp and data, and storing an update program in part of the program area. to select user programming mode, select a mode that enables the on-chip rom (mode 2 or 3) and apply 12 v to the fv pp pin, either during a reset, or after the reset has ended (been released) but while flash memory is not being accessed. in user programming mode, the on-chip supporting modules operate as they normally would in mode 2 or 3, except for the flash memory. however, hardware standby mode cannot be set while 12 v is applied to the fv pp pin. the flash memory cannot be read while it is being programmed or erased, so the update program must either be stored in external memory, or transferred temporarily to the ram area and executed in ram. 451 user programming mode execution procedure (example)*: figure 20.7 shows the execution procedure for user programming mode when the on-board update routine is executed in ram. note: * do not apply 12 v to the fv pp pin during normal operation. to prevent flash memory from being accidentally programmed or erased due to program runaway etc., apply 12 v to fv pp only when programming or erasing flash memory. overprogramming or overerasing due to program runaway can cause memory cells to malfunction. while 12 v is applied, the watchdog timer should be running and enabled to halt runaway program execution, so that program runaway will not lead to overprogramming or overerasing. for details on applying, releasing, and shutting off v pp , see section 20.7, flash memory programming and erasing precautions (5). set md 1 and md 0 to 10 or 11 (apply v ih to v cc to md 1 ) start from reset branch to flash memory on-board update routine in ram fv pp = 12 v (user program ming mode) execute flash memory on-board update routine in ram (update flash memory) 1 2 3 4 5 branch to flash memory on-board update program transfer on-board update routine into ram 6 7 8 release fv pp (exit user program ming mode) branch to application program in flash memory * procedure the flash memory on-board update program is written in flash memory ahead of time by the user. 1. set md1 and md0 of the h8/3334yf to 10 or 11, and start from a reset. 2. branch to the flash memory on-board update program in flash memory. 3. transfer the on-board update routine into ram. 4. branch to the on-board update routine that was transferred into ram. 5. apply 12 v to the fv pp pin, to enter user programming mode. 6. execute the flash memory on-board update routine in ram, to perform an on-board update of the flash memory. 7. change the voltage at the fv pp pin from 12 v to v cc , to exit user programming mode. 8. after the on-board update of flash memory ends, execution branches to an application program in flash memory. note: * after the update is finished, when input of 12 v to the fv pp pin is released, the flash memory read setup time (t frs ) must elapse before any program in flash memory is executed. this is the required setup time from when the fv pp pin reaches the (v cc + 2 v) level after 12 v is released until flash memory can be read. figure 20.7 user programming mode operation (example) 452 20.4 programming and erasing flash memory the h8/3337yf s on-chip flash memory is programmed and erased by software, using the cpu. the flash memory can operate in program mode, erase mode, program-verify mode, erase-verify mode, or prewrite-verify mode. transitions to these modes can be made by setting the p, e, pv, and ev bits in the flash memory control register (flmcr). the flash memory cannot be read while being programmed or erased. the program that controls the programming and erasing of the flash memory must be stored and executed in on-chip ram or in external memory. a description of each mode is given below, with recommended flowcharts and sample programs for programming and erasing. for details on programming and erasing, refer to section 20.7, flash memory programming and erasing precautions. 20.4.1 program mode to write data into the flash memory, follow the programming algorithm shown in figure 20.8. this programming algorithm can write data without subjecting the device to voltage stress or impairing the reliability of programmed data. to program data, first specify the area to be written in flash memory with erase block registers ebr1 and ebr2, then write the data to the address to be programmed, as in writing to ram. the flash memory latches the address and data in an address latch and data latch. next set the p bit in flmcr, selecting program mode. the programming duration is the time during which the p bit is set. the total programming time does not exceed 1 ms. programming for too long a time, due to program runaway for example, can cause device damage. before selecting program mode, set up the watchdog timer so as to prevent overprogramming. for details of the programming method, refer to section 20.4.3, programming flowchart and sample programs. 453 20.4.2 program-verify mode in program-verify mode, after data has been programmed in program mode, the data is read to check that it has been programmed correctly. after the programming time has elapsed, exit programming mode (clear the p bit to 0) and select program-verify mode (set the pv bit to 1). in program-verify mode, a program-verify voltage is applied to the memory cells at the latched address. if the flash memory is read in this state, the data at the latched address will be read. after selecting program-verify mode, wait 4 454 20.4.3 programming flowchart and sample program flowchart for programming one byte start n = 1 enable watchdog timer * 2 select program mode (p bit = 1 in flmcr) wait (x) 1 (n =1, 2, 3, 4, 5, 6), increases in proportion to n. thus, set the initial time to 15.8 figure 20.8 programming flowchart 455 sample program for programming one byte: this program uses the following registers. r0h: specifies blocks to be erased. r1h: stores data to be programmed. r1l: stores data to be read. r3: stores address to be programmed. valid address specifications are h'0000 to h'ef7f in mode 2, and h'0000 to h'f77f in mode 3. r4: sets program and program-verify timing loop counters, and also stores register setting value. r5: sets program timing loop counter. r6l: used for program-verify fail count. arbitrary data can be programmed at an arbitrary address by setting the address in r3 and the data in r1h. the setting of #a and #b values depends on the clock frequency. set #a and #b values according to tables 20.9 (1) and (2). flmcr: .equ h'ff80 ebr1: .equ h'ff82 ebr2: .equ h'ff83 tcsr: .equ h'ffa8 .align 2 prgm: mov.b #h'**, r0h ; mov.b r0h, @ebr*:8 ; set ebr * mov.b #h'00, r6l ; program-verify fail counter mov.w #h'a, r5 ; set program loop counter mov.b r1h, @r3 ; dummy write prgms: inc r6l ; program-verify fail counter + 1 mov.w #h'a579, r4 ; mov.w r4, @tcsr ; start watchdog timer mov.w r5, r4 ; set program loop counter bset #0, @flmcr:8 ; set p bit loop1: subs #1, r4 ; mov.w r4, r4 ; bne loop1 ; wait loop bclr #0, @flmcr:8 ; clear p bit mov.w #h'a500, r4 ; mov.w r4, @tcsr ; stop watchdog timer mov.b #h'b , r4h ; set program-verify loop counter bset #2, @flmcr:8 ; set pv bit loop2: dec r4h ; bne loop2 ; wait loop mov.b @r3, r1l ; read programmed address cmp.b r1h, r1l ; compare programmed data with read data beq pvok ; program-verify decision bclr #2, @flmcr:8 ; clear pv bit 456 cmp.b #h'32, r6l ; program-verify executed 6 times? beq ngend ; if program-verify executed 6 times, branch to ngend add.w r5, r5 ; programming time bra prgms ; program again pvok: bclr #2, @flmcr:8 ; clear pv bit mov.b #h'00, r6l ; mov.b r6l, @ebr*:8 ; clear ebr * one byte programmed ngend: programming error 20.4.4 erase mode to erase the flash memory, follow the erasing algorithm shown in figure 20.9. this erasing algorithm can erase data without subjecting the device to voltage stress or impairing the reliability of programmed data. to erase flash memory, before starting to erase, first place all memory data in all blocks to be erased in the programmed state (program all memory data to h'00). if all memory data is not in the programmed state, follow the sequence described later to program the memory data to zero. select the flash memory areas to be erased with erase block registers 1 and 2 (ebr1 and ebr2). next set the e bit in flmcr, selecting erase mode. the erase time is the time during which the e bit is set. to prevent overerasing, to prevent overerasing, use a software timer to divide the time for a single erase, and ensure that the total time does not exceed 30 seconds. for the time for a single erase, refer to section 20.4.6, erase flowchart and sample programs. overerasing, due to program runaway for example, can give memory cells a negative threshold voltage and cause them to operate incorrectly. before selecting erase mode, set up the watchdog timer so as to prevent overerasing. 20.4.5 erase-verify mode in erase-verify mode, after data has been erased, it is read to check that it has been erased correctly. after the erase time has elapsed, exit erase mode (clear the e bit to 0) and select erase- verify mode (set the ev bit to 1). before reading data in erase-verify mode, write h'ff dummy data to the address to be read. this dummy write applies an erase-verify voltage to the memory cells at the latched address. if the flash memory is read in this state, the data at the latched address will be read. after the dummy write, wait 2 457 20.4.6 erasing flowchart and sample program flowchart for erasing one block start write 0 data in all addresses to be erased (prewrite) * 1 n = 1 set erase block register (set bit of block to be erased to 1) enable watchdog timer * 2 select erase mode (e bit = 1 in flmcr) wait (x) ms * 5 clear e bit disable watchdog timer set top address in block as verify address select erase-verify mode (ev bit = 1 in flmcr) wait (t vs 1) > 1 (n = 1, 2, 3, 4). an initial value of 6.25 ms or less should be set, and the time for one erasure should be 50 ms or less. * 6t vs 1: 4 figure 20.9 erasing flowchart 458 prewrite flowchart end of prewrite n 1 (n = 1, 2, 3, 4, 5, 6), increases in proportion to n. thus, set the initial time to 15.8 figure 20.10 prewrite flowchart 459 sample block-erase program: this program uses the following registers. r0: specifies block to be erased, and also stores address used in prewrite and erase-verify. r1h: stores data to be read, and also used for dummy write. r2: stores last address of block to be erased. r3: stores address used in prewrite and erase-verify. r4: sets timing loop counters for prewrite, prewrite-verify, erase, and erase-verify, and also stores register setting value. r5: sets prewrite and erase timing loop counters. r6l: used for prewrite-verify and erase-verify fail count. the setting of #a, #b, #c, #d, and #e values in the program depends on the clock frequency. set #a, #b, #c, #d, and #e values according tables 20.9 (1) and (2), and 20.10. erase block registers (ebr1 and ebr2) should be set according to sections 20.2.2 and 20.2.3. #blkstr and #blkend are the top and last addresses of the block to be erased. set #blkstr and #blkend according to figure 20.2. 460 flmcr: .equ h'ff80 ebr1: .equ h'ff82 ebr2: .equ h'ff83 tcsr: .equ h'ffa8 .align 2 mov.b #h'**, roh ; mov.b roh, @ebr*:8 ; set ebr* ; #blkstr is top address of block to be erased. ; #blkend is last address of block to be erased. mov.w #blkstr, r0 ; top address of block to be erased mov.w #blkend, r2 ; last address of block to be erased adds #1, r2 ; last address of block to be erased + 1 mov.w r0, r3 ; top address of block to be erased prewrt: mov.b #h'00, r6l ; prewrite-verify fail counter mov.w #h'a, r5 ; set prewrite loop counter prewrs: inc r6l ; prewrite-verify fail counter + 1 mov.b #h'00 r1h ; mov.b r1h, @r3 ; write h'00 mov.w #h'a579, r4 ; mov.w r4, @tcsr ; start watchdog timer mov.w r5, r4 ; set prewrite loop counter bset #0, @flmcr:8 ; set p bit loopr1: subs #1, r4 ; mov.w r4, r4 ; bne loopr1 ; wait loop bclr #0, @flmcr:8 ; clear p bit mov.w #h'a500, r4 ; mov.w r4, @tcsr ; stop watchdog timer mov.b #h'c, r4h ; set prewrite-verify loop counter loopr2: dec r4h ; bne loopr2 ; wait loop mov.b @r3, r1h ; read data = h'00? beq pwvfok ; if read data = h'00 branch to pwvfok cmp.b #h'06, r6l ; prewrite-verify executed 6 times? beq abend1 ; if prewrite-verify executed 6 times, branch to abend1 add.w r5, r5 ; programming time bra prewrs ; prewrite again abend1: programming error pwvfok: adds #1, r3 ; address + 1 cmp.w r2, r3 ; last address? bne prewrt ; if not last address, prewrite next address ; execute erase erases: mov.w #h'0000, r6 ; erase-verify fail counter mov.w #h'd, r5 ; set erase loop count 461 erase: adds #1, r6 ; erase-verify fail counter + 1 mov.w #h'e, r4 ; mov.w r4, @tcsr ; start watchdog timer mov.w r5, r4 ; set erase loop counter bset #1, @flmcr:8 ; set e bit loope: nop nop nop nop subs #1, r4 ; mov.w r4, r4 ; bne loope ; wait loop bclr #1, @flmcr:8 ; clear e bit mov.w #h'a500, r4 ; mov.w r4, @tcsr ; stop watchdog timer ; execute erase-verify mov.w r0, r3 ; top address of block to be erased mov.b #h'b, r4h ; set erase-verify loop counter bset #3, @flmcr:8 ; set ev bit loopev: dec r4h ; bne loopev ; wait loop evr2: mov.b #h'ff, r1h ; mov.b r1h, @r3 ; dummy write mov.b #h'c, r4h ; set erase-verify loop counter loopdw: dec r4h ; bne loopdw ; wait loop mov.b @r3+, r1h ; read cmp.b #h'ff, r1h ; read data = h'ff? bne rerase ; if read data cmp.w r2, r3 ; last address of block? bne evr2 bra okend rerase: bclr #3, @flmcr:8 ; clear ev bit subs #1, r3 ; erase-verify address 1 mov.w #h'0004, r4 ; cmp.w r4, r6 ; erase-verify fail count executed 4 times? bpl brer ; if r6 add.w r5, r5 ; if r6 < 4, erase time brer: mov.w #h'025a, r4 ; cmp.w r4, r6 ; erase-verify executed 602 times? bne erase ; if erase-verify not executed 602 times, erase again bra abend2 ; if erase-verify executed 602 times, branch to abend2 okend: bclr #3, @flmcr:8 ; clear ev bit mov.b #h'00, r6l ; mov.b r6l, @ebr*:8 ; clear ebr* one block erased abend2: erase error 462 flowchart for erasing multiple blocks start write 0 data to all addresses to be erased (prewrite) * 1 n = 1 set erase block registers (set bits of block to be erased to 1) enable watchdog timer * 2 select erase mode (e bit = 1 in flmcr) wait (x)ms * 5 clear e bit disable watchdog timer select erase-verify mode (ev bit = 1 in flmcr) wait (t vs 1) 1 (n = 1, 2, 3, 4). an initial value of 6.25 ms or less should be set, and the time for one erasure should be 50 ms or less. * 6t vs 1: 4 figure 20.11 multiple-block erase flowchart 463 sample multiple-block erase program: this program uses the following registers. r0: specifies blocks to be erased (set as explained below), and also stores address used in prewrite and erase-verify. r1h: used to test bits 8 to 15 of r0 stores register read data, and also used for dummy write. r1l: used to test bits 0 to 15 of r0. r2: specifies address where address used in prewrite and erase-verify is stored. r3: stores address used in prewrite and erase-verify. r4: stores last address of block to be erased. r5: sets prewrite and erase timing loop counters. r6l: used for prewrite-verify and erase-verify fail count. arbitrary blocks can be erased by setting bits in r0. write r0 with a word transfer instruction. a bit map of r0 and a sample setting for erasing specific blocks are shown next. bit 1514131211109876543210 r0 lb7 lb6 lb5 lb4 lb3 lb2 lb1 lb0 sb7 sb6 sb5 sb4 sb3 sb2 sb1 sb0 corresponds to ebr1 corresponds to ebr2 example: to erase blocks lb2, sb7, and sb0 bit 1514131211109876543210 r0 lb7 lb6 lb5 lb4 lb3 lb2 lb1 lb0 sb7 sb6 sb5 sb4 sb3 sb2 sb1 sb0 corresponds to ebr1 corresponds to ebr2 setting 0000010010000001 r0 is set as follows: mov.w #h'0481,r0 mov.w r0, @ebr1 the setting of #a, #b, #c, #d, and #e values in the program depends on the clock frequency. set #a, #b, #c, #d, and #e values according to tables 20.9 (1), (2), and 20.10. 464 notes: 1. in this sample program, the stack pointer (sp) is set at address ff80. as the stack area, on-chip ram addresses ff7e and ff7f are used. therefore, when executing this sample program, addresses ff7e and ff7f should not be used. in addition, the on-chip ram should not be disabled. 2. in this sample program, the program written in a rom area (including external space) is transferred into the ram area and executed in the ram to which the program is transferred. #ramstr in the program is the starting destination address in ram to which the program is transferred. #ramstr must be set to an even number. 3. when executing this sample program in the on-chip rom area or external space, #ramstr should be set to #start. flmcr: .rqu h'ff80 ebr1: .equ h'ff82 ebr2: .equ h'ff83 tcsr: .equ h'ffa8 stack: .equ h'ff80 .align2 start: mov.w #stack, sp ; set stack pointer ; set the bits in r0 following the description on the previous page. this program is a sample program to erase ; all blocks. mov.w #h'ffff, r0 ; select blocks to be erased (r0: ebr1/ebr2) mov.w r0, @ebr1 ; set ebr1/ebr2 ; #ramstr is starting destination address to which program is transferred in ram. ; set #ramstr to even number. mov.w #ramstr, r2 ; starting transfer destination address (ram) mov.w #ervadr, r3 ; add.w r3, r2 ; #ramstr + #ervadr mov.w #start, r3 ; sub.w r3, r2 ; address of data area used in ram mov.b #h'00, r1l : used to test r1l bit in r0 pretst: cmp.b #h'10, r1l ; r1l = h'10? beq erases ; if finished checking all r0 bits, branch to erases cmp.b #h'08, r1l ; bmi ebr2pw ; test ebr1 if r1l mov.b r1l, r1h ; subx #h'08, r1h ; r1l 8 btst r1h, r0h ; test r1h bit in ebr1 (r0h) bne prewrt ; if r1h bit in ebr1 (r0h) is 1, branch to prewrt bra pwadd1 ; if r1h bit in ebr1 (r0h) is 0, branch to pwadd1 ebr2pw: btst r1l, r0l ; test r1l bit in ebr2 (r0l) bne prewrt ; if r1l bit in ebr2 (r0h) is 1, branch to prewrt pwadd1: inc r1l ; r1l + 1 mov.w @r2+, r3 ; dummy-increment r2 bra pretst ; 465 ; execute prewrite prewrt: mov.w @r2+, r3 ; prewrite starting address prew: mov.b #h'00, r6l ; prewrite-verify fail counter mov.w #h'a, r5 ; prewrite-verify loop counter prewrs: inc r6l ; prewrite-verify fail counter + 1 mov.b #h'00, r1h ; mov.b r1h, @r3 ; write h'00 mov.w #h'a579, r4 ; mov.w r4, @tcsr ; start watchdog timer mov.w r5, r4 ; set prewrite loop counter bset #0, @flmcr:8 ; set p bit loopr1: subs #1, r4 ; mov.w r4, r4 ; bne loopr1 ; wait loop bclr #0, @flmcr:8 ; clear p bit mov.w #h'a500, r4 ; mov.w r4, @tcsr ; stop watchdog timer mov.b #h'c, r4h ; set prewrite-verify loop counter loopr2: dec r4h ; bne loopr2 ; wait loop mov.b @r3, r1h ; read data = h'00? beq pwvfok ; if read data = h'00 branch to pwvfok cmp.b #h'06, r6l ; prewrite-verify executed 6 times? beq abend1 ; if prewrite-verify executed 6 times, branch to abend1 add.w r5, r5 ; programming time bra prewrs ; prewrite again abend1: programming error pwvfok: adds #1, r3 ; address + 1 mov.w @r2, r4 ; top address of next block cmp.w r4, r3 ; last address? bne prew ; if not last address, prewrite next address pwadd2: inc r1l ; used to test r1l+1 bit in r0 bra pretst ; branch to pretst ; execute erase erases: mov.w #h'0000, r6 ; erase-verify fail counter mov.w #h'd, r5 ; set erase loop count erase: adds #1, r6 ; erase-verify fail counter + 1 mov.w #h'e, r4 ; mov.w r4, @tcsr ; start watchdog timer mov.w r5, r4 ; set erase loop counter bset #1, @flmcr:8 ; set e bit loope: nop nop nop nop subs #1, r4 ; mov.w r4, r4 ; bne loope ; wait loop bclr #1, @flmcr:8 ; clear e bit mov.w #h'a500, r4 ; mov.w r4, @tcsr ; stop watchdog timer 466 ; execute erase-verify evr: mov.w #ramstr, r2 ; starting transfer destination address (ram) mov.w #ervadr, r3 ; add.w r3, r2 ; #ramstr + #ervadr mov.w #start, r3 ; sub.w r3, r2 ; address of data area used in ram mov.b #h'00, r1l ; used to test r1l bit in r0 mov.b #h'b, r4h ; set erase-verify loop counter bset #3, @flmcr:8 ; set ev bit loopev: dec r4h ; bne loopev ; wait loop ebrtst: cmp.b #h'10, r1l ; r1l = h'10? beq hantei ; if finished checking all r0 bits, branch to hantei cmp.b #h'08, r1l ; bmi ebr2ev ; test ebr1 if r1l mov.b r1l, r1h ; subx #h'08, r1h ; r1l 8 btst r1h, r0h ; test r1h bit in ebr1 (r0h) bne ersevf ; if r1h bit in ebr1 (r0h) is 1, branch to ersevf bra add01 ; if r1h bit in ebr1 (r0h) is 0, branch to add01 ebr2ev: btst r1l, r0l ; test r1l bit in ebr2 (r0l) bne ersevf ; if r1l bit in ebr2 (r0h) is 1, branch to ersevf add01: inc r1l ; r1l + 1 mov.w @r2+, r3 ; dummy-increment r2 bra ebrtst ; erase1: bra erase ; branch to erase via erase 1 ersevf: mov.w @r2+, r3 ; top address of block to be erase-verified evr2: mov.b #h'ff, r1h ; mov.b r1h, @r3 ; dummy write mov.b #h'c, r4h ; set erase-verify loop counter loopep: dec r4h ; bne loopep ; wait loop mov.b @r3+, r1h ; read cmp.b #h'ff, r1h ; read data = h'ff? bne blkad ; if read data mov.w @r2, r4 ; top address of next block cmp.w r4, r3 ; last address of block? bne evr2 cmp.b #h'08, r1l bmi sbclr ; test ebr1 if r1l mov.b r1l, r1h ; subx #h'08, r1h ; r1l 8 bclr r1h, r0h ; clear r1h bit in ebr1 (r0h) bra blkad sbclr: bclr r1l, r0l ; clear r1l bit in ebr2 (r0l) blkad: inc r1l ; r1l + 1 bra ebrtst ; 467 hantei: bclr #3, @flmcr:8 ; clear ev bit mov.w r0, @ebr1 ; beq eowari ; if ebr1/ebr2 is all 0, erasing ended normally mov.w #h'0004, r4 ; cmp.w r4 r6 ; erase-verify fail count executed 4 times? bpl brer ; if r6 add.w r5 r5 ; if r6 < 4, erase time brer: mov.w #h'025a, r4 ; cmp.w r4, r6 ; erase-verify executed 602 times? bne erase1 ; if erase-verify not executed 602 times, erase again bra abend2 ; if erase-verify executed 602 times, branch to abend2 ; < block address table used in erase-verify> .align 2 ervadr: .data.w h'0000 ; sb0 .data.w h'0080 ; sb1 .data.w h'0100 ; sb2 .data.w h'0180 ; sb3 .data.w h'0200 ; sb4 .data.w h'0400 ; sb5 .data.w h'0800 ; sb6 .data.w h'0c00 ; sb7 .data.w h'1000 ; lb0 .data.w h'2000 ; lb1 .data.w h'4000 ; lb2 .data.w h'6000 ; lb3 .data.w h'8000 ; lb4 .data.w h'a000 ; lb5 .data.w h'c000 ; lb6 .data.w h'ef80 ; lb7 .data.w h'f780 ; flash end eowari: erase end abend2: erase error loop counter values in programs and watchdog timer overflow interval settings: the setting of #a, #b, #c, #d, and #e values in the programs depends on the clock frequency. tables 20.9 (1) and (2) indicate sample loop counter settings for typical clock frequencies. however, #e is set according to table 20.10. as a software loop is used, calculated values including percent errors may not be the same as actual values. therefore, the values are set so that the total programming time and total erase time do not exceed 1 ms and 30 s, respectively. the maximum number of writes in the program, n, is set to 6. 468 programming and erasing in accordance with the flowcharts is achieved by setting #a, #b, #c, and #d in the programs as shown in tables 20.9 (1) and (2). #e should be set as shown in table 20.10. wait state insertion is inhibited in these programs. if wait states are to be used, the setting should be made after the program ends. the setting value for the watchdog timer (wdt) overflow time is calculated based on the number of instructions between starting and stopping of the wdt, including the write time and erase time. therefore, no other instructions should be added between starting and stopping of the wdt in this program example. table 20.9 (1) #a, #b, #c, and #d setting values for typical clock frequencies with program running in the on-chip memory (ram) clock frequency f = 16 mhz f = 10 mhz f = 8 mhz f = 2 mhz variable time setting counter setting value counter setting value counter setting value counter setting value a (f) programming time (initial setting value) 15.8 table 20.9 (2) #a, #b, #c, and #d setting values for typical clock frequencies with program running in the external device clock frequency f = 16 mhz f = 10 mhz f = 8 mhz f = 2 mhz variable time setting counter setting value counter setting value counter setting value counter setting value a (f) programming time (initial setting value) 15.8 469 formula: when using a clock frequency not shown in tables 20.9 (1) and (2), follow the formula below. the calculation is based on a clock frequency of 10 mhz. after calculating a(f) and d(f) in the decimal system, omit the first decimal figures, and convert them to the hexadecimal system, so that a(f) and d(f) are set to 15.8 table 20.10 watchdog timer overflow interval settings (#e setting value according to clock frequency) variable clock frequency [mhz] e (f) 10 mhz 470 20.4.7 prewrite verify mode prewrite-verify mode is a verify mode used when programming all bits to equalize their threshold voltages before erasing them. program all flash memory to h'00 by writing h'00 using the prewrite algorithm shown in figure 20.10. h'00 should also be written when using ram for flash memory emulation (when prewriting a ram area). (this also applies when using ram to emulate flash memory erasing with an emulator or other support tool.) after the necessary programming time has elapsed, exit program mode (by clearing the p bit to 0) and select prewrite-verify mode (leave the p, e, pv, and ev bits all cleared to 0). in prewrite-verify mode, a prewrite-verify voltage is applied to the memory cells at the read address. if the flash memory is read in this state, the data at the read address will be read. after selecting prewrite-verify mode, wait 4 20.4.8 protect modes flash memory can be protected from programming and erasing by software or hardware methods. these two protection modes are described below. software protection: prevents transitions to program mode and erase mode even if the p or e bit is set in the flash memory control register (flmcr). details are as follows. function protection description program erase verify * 1 block protect individual blocks can be protected from erasing and programming by the erase block registers (ebr1 and ebr2). if h'00 is set in ebr1 and in ebr2, all blocks are protected from erasing and programming. disabled disabled enabled emulation protect * 2 when the rams or ram0 bit, but not both, is set in the wait-state control register (wscr), all blocks are protected from programming and erasing. disabled disabled * 3 enabled notes: * 1 three modes: program-verify, erase-verify, and prewrite-verify. * 2 except in ram areas overlapped onto flash memory. * 3 all blocks are erase-disabled. it is not possible to specify individual blocks. 471 hardware protection: suspends or disables the programming and erasing of flash memory, and resets the flash memory control register (flmcr) and erase block registers (ebr1 and ebr2). details of hardware protection are as follows. function protection description program erase verify * 1 programing voltage (v pp ) protect when 12 v is not applied to the fv pp pin, flmcr, ebr1, and ebr2 are initialized, disabling programming and erasing. to obtain this protection, v pp should not exceed v cc . * 3 disabled disabled * 2 disabled reset and standby protect when a reset occurs (including a watchdog timer reset) or standby mode is entered, flmcr, ebr1, and ebr2 are initialized, disabling programming and erasing. note that res res ) during operation. disabled disabled * 2 disabled interrupt protect to prevent damage to the flash memory, if interrupt input occurs while flash memory is being programmed or erased, programming or erasing is aborted immediately. the settings in flmcr, ebr1, and ebr2 are retained. this type of protection can be cleared only by a reset. disabled disabled * 2 enabled notes: * 1 three modes: program-verify, erase-verify, and prewrite-verify. * 2 all blocks are erase-disabled. it is not possible to specify individual blocks. * 3 for details, see section 20.7, flash memory programming and erasing precautions. 20.4.9 interrupt handling during flash memory programming and erasing if an interrupt occurs *1 while flash memory is being programmed or erased (while the p or e bit of flmcr is set), the following operating states can occur. ? ? 472 for nmi interrupts while flash memory is being programmed or erased, these malfunction and runaway problems can be prevented by using the ram overlap function with the settings described below. 1. do not store the nmi interrupt-handling routine *3 in the flash memory area (neither h'0000 to h'ef7f in mode2. nor h'0000 to h'f77f in mode3). store it elsewhere (in ram, for example) 2. set the nmi interrupt vector in address h'f806 in ram (corresponding to h'0006 in flash memory). 3. after the above settings, set both the rams and ram0 bits to 1 in wscr. *4 due to the setting of step 3, if an interrupt signal is input while 12 v is applied to the fv pp pin, the ram overlap function is enabled and part of the ram (h'f800 to h'f87f) is overlapped onto the small-block area of flash memory (h'0000 to h'007f). as a result, when an interrupt is input, the vector is read from ram, not flash memory, so the interrupt is handled normally even if flash memory is being programmed or erased. this can prevent malfunction and runaway. notes: *1 when the interrupt mask bit (i) of the condition control register (ccr) is set to 1, all interrupts except nmi are masked. for details see (2) in section 2.2.2, control registers. *2 the vector table might not be read correctly for one of the following reasons: if flash memory is read while it is being programmed or erased (while the p or e bit of flmcr is set), the correct value cannot be read. if no value has been written for the nmi entry in the vector table yet, nmi exception handling will not be executed correctly. *3 this routine should be programmed so as to prevent microcontroller runaway. *4 for details on wscr settings, see section 20.2.4, wait-state control register. notes on interrupt handling in boot mode: in boot mode, the settings described above concerning nmi interrupts are carried out, and nmi interrupt handling (but not other interrupt handling) is enabled while the boot program is executing. note the following points concerning the user program. ? ? ? ? 473 20.5 flash memory emulation by ram erasing and programming flash memory takes time, which can make it difficult to tune parameters and other data in real time. if necessary, real-time updates of flash memory can be emulated by overlapping the small-block flash-memory area with part of the ram (h'f800 to h'f97f). this ram reassignment is performed using bits 7 and 6 of the wait-state control register (wscr). see figure 20.11. after a flash memory area has been overlapped by ram, the ram area can be accessed from two address areas: the overlapped flash memory area, and the original ram area (h'f800 to h'f97f). table 20.11 indicates how to reassign ram. wait-state control register (wscr) *2 bit 76543210 rams ram0 ckdbl wms1 wms0 wc1 wc0 initial value * 1 00001000 read/write r/w r/w r/w r/w r/w r/w r/w r/w notes: * 1 wscr is initialized by a reset and in hardware standby mode. it is not initialized in software standby mode. * 2 for details of wscr settings, see section 20.2.4, wait-state control register (wscr). table 20.11 ram area selection bit 7: rams bit 6: ramo ram area rom area 0 0 none 1 h'f880 to h'f8ff h'0080 to h'00ff 1 0 h'f880 to h'f97f h'0080 to h'017f 1 h'f800 to h'f87f h'0000 to h'007f 474 example of emulation of real-time flash-memory update h'007f h'0080 h'00ff h'0100 h'0000 h'f77f h'f780 h'f880 h'f8ff h'ff7f small-block area (sb1) flash memory address space overlapped ram overlapped ram on-chip ram area procedure 1. overlap part of ram (h'f880 to h'f8ff) onto the area requiring real-time update (sb1). (set wscr bits 7 and 6 to 01.) 2. perform real-time updates in the overlapping ram. 3. after finalization of the update data, clear the ram overlap (by clearing the rams and ram0 bits). 4. read the data written in ram addresses h'f880 to h'f8ff out externally, then program the flash memor y area, usin g this data as part of the pro g ram data. figure 20.12 example of ram overlap 475 notes on use of ram emulation function ? 476 20.6 flash memory writer mode (h8/3337yf) 20.6.1 writer mode setting the on-chip flash memory of the h8/3337yf can be programmed and erased not only in the on- board programming modes but also in writer mode, using a general-purpose prom programmer. 20.6.2 socket adapter and memory map programs can be written and verified by attaching a socket adapter for the relevant package to the prom programmer. table 20.12 gives ordering information for the socket adapter. figure 20.13 shows a memory map in writer mode. figure 20.14 shows the socket adapter pin interconnections. table 20.12 socket adapter microcontroller package socket adapter hd64f3337yf16 80-pin qfp hs3334eshf1h hd64f3337ytf16 80-pin tqfp hs3334esnf1h hd64f3337ycp16 84-pin plcc hs3334escf1h h8/3337yf h'0000 h'f77f h'0000 h'f77f on-chip rom area mcu mode writer mode 1 output h'1ffff figure 20.13 memory map in writer mode 477 h8/3337yf pin name fp-80a tfp-80c cp-84 18 17 27 28 29 79 80 81 82 83 84 1 3 78 77 76 75 74 73 72 71 69 68 67 66 65 63 62 61 31, 32, 36, 37, 25 15, 16, 30, 40 42 19, 60 51 2, 4, 23, 24, 41, 64, 70 12 13, 14 7 6 15 16 17 65 66 67 68 69 70 71 72 64 63 62 61 60 59 58 57 55 54 53 52 51 50 49 48 19, 20, 24, 25, 13 4, 5, 18, 28 29 8, 47 38 12, 56, 73 1 2, 3 1 26 2 3 31 13 14 15 17 18 19 20 21 12 11 10 9 8 7 6 5 27 24 23 25 4 28 29 22 32 16 hn28f101 (32 pins) pin no. pin name v pp fa 9 fa 16 fa 15 we oe socket adapter pin no. stby nmi res oe ce we figure 20.14 wiring of socket adapter 478 20.6.3 operation in writer mode the program/erase/verify specifications in writer mode are the same as for the standard hn28f101 flash memory. however, since the h8/3337yf does not support product name recognition mode, the programmer cannot be automatically set with the device name. table 20.13 indicates how to select the various operating modes. table 20.13 operating mode selection in writer mode pins mode fv pp v cc ce oe we d 7 to d 0 a 16 to a 0 read read v cc v cc l l h data output address input output disable v cc v cc l h h high impedance standby v cc v cc h x x high impedance command read v pp v cc l l h data output write output disable v pp v cc l h h high impedance standby v pp v cc h x x high impedance write v pp v cc l h l data input note: be sure to set the fv pp pin to v cc in these states. if it is set to 0 v, hardware standby mode will be entered, even when in writer mode, resulting in incorrect operation. legend: l: low level h: high level v pp :v pp level v cc :v cc level x: don t care 479 table 20.14 writer mode commands 1st cycle 2nd cycle command cycles mode address data mode address data memory read 1 write x h'00 read ra dout erase setup/erase 2 write x h'20 write x h'20 erase-verify 2 write ea h'a0 read x evd auto-erase setup/ auto-erase 2 write x h'30 write x h'30 program setup/ program 2 write x h'40 write pa pd program-verify 2 write x h'c0 read x pvd reset 2 write x h'ff write x h'ff pa: program address ea: erase-verify address ra: read address pd: program data pvd: program-verify output data evd: erase-verify output data 480 high-speed, high-reliability programming: unused areas of the h8/3337yf flash memory contain h'ff data (initial value). the h8/3337yf flash memory uses a high-speed, high-reliability programming procedure. this procedure provides enhanced programming speed without subjecting the device to voltage stress and without sacrificing the reliability of programmed data. figure 20.15 shows the basic high-speed, high-reliability programming flowchart. tables 20.15 and 20.16 list the electrical characteristics during programming. start set v pp = 12.0 v figure 20.15 high-speed, high-reliability programming 481 high-speed, high-reliability erasing: the h8/3337yf flash memory uses a high-speed, high- reliability erasing procedure. this procedure provides enhanced erasing speed without subjecting the device to voltage stress and without sacrificing data reliability . figure 20.16 shows the basic high-speed, high-reliability erasing flowchart. tables 20.15 and 20.16 list the electrical characteristics during erasing. start program all bits to 0 * address = 0 n = 0 wait (10 ms) erase setup/erase command n + 1 figure 20.16 high-speed, high-reliability erasing 482 table 20.15 dc characteristics in writer mode (conditions: v cc = 5.0 v item symbol min typ max unit test conditions input high voltage fo 7 to fo 0 , fa 16 to fa 0 , oe ce we v cc + 0.3 v input low voltage fo 7 to fo 0 , fa 16 to fa 0 , oe ce we 0.3 0.8 v output high voltage fo 7 to fo 0 v oh 2.4 vi oh = 200 0.45 v i ol = 1.6 ma input leakage current fo 7 to fo 0 , fa 16 to fa 0 , oe ce we 2 40 80 ma program i cc 40 80 ma erase i cc 40 80 ma fv pp current read i pp 10 10 20 ma v pp = 12.6 v program i pp 20 40 ma v pp = 12.6 v erase i pp 20 40 ma v pp = 12.6 v 483 table 20.16 ac characteristics in writer mode (conditions: v cc = 5.0 v item symbol min typ max unit test conditions command write cycle t cwc 120 ns figure 20.17 address setup time t as 0 ns figure 20.18 * address hold time t ah 60 ns figure 20.19 data setup time t ds 50 ns data hold time t dh 10 ns ce ns ce ns v pp setup time t vps 100 ns v pp hold time t vph 100 ns we ns we ns oe ns oe 500 ns oe ns status polling access time t spa 120 ns program wait time t ppw 25 ns erase wait time t et 9 11 ms output disable time t df 0 40 ns total auto-erase time t aet 0.5 30 s note: ce oe we 484 auto-erase setup auto-erase and status polling address command input status polling command input command input command input 5.0 v 12 v 5.0 v v cc v pp ce oe we figure 20.17 auto-erase timing 485 t vph t vps t ceh t ces t oews t wep t ceh t ces t cwc t wep t ds t dh t ds t dh t as t ah t ppw t ces t weh t ceh t wep t oers t dh t ds t va t df command input command input data input command input command input valid data output data input program setup program program-verify valid address address 5.0 v 12 v 5.0 v v cc v pp ce oe we figure 20.18 high-speed, high-reliability programming timing 486 address 5.0 v 12 v 5.0 v v cc v pp ce oe we figure 20.19 erase timing 20.7 flash memory programming and erasing precautions read these precautions before using writer mode, on-board programming mode, or flash memory emulation by ram. (1) program with the specified voltages and timing. the rated programming voltage (v pp ) of the flash memory is 12.0 v. if the prom programmer is set to hitachi hn28f101 specifications, v pp will be 12.0 v. applying voltages in excess of the rating can permanently damage the device. take particular care to ensure that the prom programmer peak overshoot does not exceed the rated limit of 13 v. (2) before programming, check that the chip is correctly mounted in the prom programmer. overcurrent damage to the device can result if the index marks on the prom programmer socket, socket adapter, and chip are not correctly aligned. (3) don? touch the socket adapter or chip while programming. touching either of these can cause contact faults and write errors. 487 (4) set h'ff as the prom programmer buffer data for addresses h'f780 to h'1ffff. the h8/3337yf prom size is 60 kbytes. addresses h'f780 to h'1ffff always read h'ff, so if h'ff is not specified as programmer data, a verify error will occur. (5) notes on applying, releasing, and shutting off *1 the programming voltage (v pp ) ? ? s v cc voltage is not within the rated voltage range (v cc = 2.7 to 5.5 v) *2 , since microcontroller operation is unstable, the flash memory may be programmed or erased by mistake. this can occur even if v cc = 0 v. to prevent changes in the v cc power supply when v pp is applied, be sure that the power supply is adequately decoupled by inserting bypass capacitors. ? res ? res ). ? 488 ? ? ? stby 489 t osc1 2.7 to 5.5 v * 12 (when res v cc v pp v pp res figure 20.20 v pp power-on and power-off timing (6) do not apply 12 v to the fv pp pin during normal operation. to prevent accidental programming or erasing due to microcontroller program runaway etc., apply 12 v to the v pp pin only when the flash memory is programmed or erased, or when flash memory is emulated by ram. overprogramming or overerasing due to program runaway can cause memory cells to malfunction. avoid system configurations in which 12 v is always applied to the fv pp pin. while 12 v is applied, the watchdog timer should be running and enabled to halt runaway program execution, so that program runaway will not lead to overprogramming or overerasing. 490 (7) design a current margin into the programming voltage (v pp ) power supply. ensure that v pp will not depart from 12.0 (8) ensure that peak overshoot does not exceed the rated value at the fv pp and md 1 pins. connect decoupling capacitors as close to the fv pp and md 1 pins as possible. also connect decoupling capacitors to the md 1 pin in the same way when boot mode is uesd. 0.01 figure 20.21 v pp power supply circuit design (example) (9) use the recommended algorithms for programming and erasing flash memory. these algorithms are designed to program and erase without subjecting the device to voltage stress and without sacrificing the reliability of programmed data. before setting the program (p) or erase (e) bit in the flash memory control register (flmcr), set the watchdog timer to ensure that the p or e bit does not remain set for more than the specified time. (10) for details on interrupt handling while flash memory is being programmed or erased, see the notes on nmi interrupt handling in section 20.4.9, interrupt handling during flash memory programming and erasing. (11) cautions on accessing flash memory control registers 1. flash memory control register access state in each operating mode the h8/3337yf has flash memory control registers located at addresses h'ff80 (flmcr), h'ff82 (ebr1), and h'ff83 (ebr2). these registers can only be accessed when 12 v is applied to the flash memory program power supply pin, fv pp . table 1 shows the area accessed for the above addresses in each mode, when 12 v is and is not applied to fv pp . 491 table 20.17 area accessed in each mode with 12v applied and not applied to fv pp mode 1 mode 2 mode 3 12 v applied to fv pp register reserved area (always h'ff) flash memory control register (initial value h'80) flash memory control (initial value h'80) 12 v not applied to fv pp external address space external address space reserved area (always h'ff) 2. when a flash memory control register is accessed in mode 2 (expanded mode with on-chip rom enabled) when a flash memory control register is accessed in mode 2, it can be read or written to if 12 v is being applied to fv pp , but if not, external address space will be accessed. it is therefore essential to confirm that 12 v is being applied to the fv pp pin before accessing these registers. 3. to check for 12 v application/non-application in mode 3 (single-chip mode) when address h'ff80 is accessed in mode 3, if 12 v is being applied to fv pp , flmcr is read/written to, and its initial value after reset is h'80. when 12 v is not being applied to fv pp , flmcr is a reserved area that cannot be modified and always reads h'ff. since bit 7 (corresponding to the v pp bit) is set to 1 at this time regardless of whether 12 v is applied to fv pp , application or release of 12 v to fv pp cannot be determined simply from the 0 or 1 status of this bit. a byte data comparison is necessary to check whether 12 v is being applied. the relevant coding is shown below. . . . label1: mov.b @h'ff80, r1l cmp.b #h'ff, r1l beq label1 . . . sample program for detection of 12 v application to fv pp (mode 3) 492 table 20.18 dc characteristics of flash memory conditions: v cc = 2.7 v to 5.5 v *2 , av cc = 2.7 v to 5.5 v *2 ,v ss = av ss = 0 v, v pp = 12.0 20 40 item symbol min typ max unit test conditions high-voltage (12 v) threshold level * 1 fv pp , md 1 v h v cc + 2 11.4 v fv pp current during read i pp 10 10 20 ma v pp = 12.6 v during programming 20 40 ma during erasure 20 40 ma notes: * 1 the listed voltages indicate the threshold level at which high-voltage application is recognized. in boot mode and while flash memory is being programmed or erased, the applied voltage should be 12.0 v 493 table 20.19 ac characteristics of flash memory conditions: v cc = 2.7 v to 5.5 v *5 , av cc = 2.7 v to 5.5 v *5 , v ss = av ss = 0 v, v pp = 12.0 20 40 item symbol min typ max unit test conditions programming time * 1, * 2 t p 50 1000 130s number of writing/erasing count n wec 100 times verify setup time 1 * 1 t vs1 4 v cc < 4.5 v notes: * 1 set the times following the programming/erasing algorithm shown in section 20. * 2 the programming time is the time during which a byte is programmed or the p bit in the flash memory control register (flmcr) is set. it does not include the program-verify time. * 3 the erase time is the time during which all 60-kbyte blocks are erased or the e bit in the flash memory control register (flmcr) is set . it does not include the prewrite time before erasure or erase-verify time. * 4 after power-on when using an external colck source, after return from standby mode, or after switching the programming voltage (v pp ) from 12 v to v cc , make sure that this read setup time has elapsed before reading flash memory. when v pp is released, the flash memory read setup time is defined as the period from when the fv pp pin has reached v cc + 2 v until flash memory can be read. * 5 in the lh version, v cc = 3.0 v to 5.5 v, av cc = 3.0 v to 5.5 v 494 495 section 21 rom (60-kbyte single-power-supply flash memory version) 21.1 flash memory overview 21.1.1 mode pin settings and rom space the h8/3337sf has 60 kbytes of on-chip flash memory. the rom is connected to the cpu by a 16-bit data bus. the cpu accesses both byte data and word data in two states. even addresses are connected to the upper 8 bits, and odd addresses to the lower 8 bits. word data must start at an even address. enabling and disabling of the on-chip rom is performed by the mode pins (md 1 and md 2 ) and the expe bit in mdcr. the h8/3337sf flash memory can be programmed and erased on-board as well as with a prom programmer. table 21.1 mode pin settings and rom space operating mode mode pin settings mcu operating mode description md 1 md 0 on-chip rom mode 1 expanded mode with on-chip rom disabled 0 1 disabled mode 2 expanded mode with on-chip rom enabled 1 0 enabled mode 3 single-chip mode 1 enabled 496 21.1.2 features features of the flash memory are listed below. ? four flash memory operating modes the flash memory has four operating modes: program mode, program-verify mode, erase mode, and erase-verify mode. ? programming and erasing 32 bytes are programmed at a time. erasing is performed in block units. to erase multiple blocks, individual blocks must be erased sequentially. in block erasing, 1-kbyte, 28-kbyte, 16- kbyte, 12-kbyte, and 2-kbyte blocks can be set arbitrarily. ? program and erase times the flash memory programming time is 10 ms (typ.) for simultaneous 32-byte programming, equivalent to 300 s (typ.) per byte, and the erase time for one block is 100 ms (typ.). ? erase-program cycles flash memory contents can be erased and reprogrammed up to 100 times. ? on-board programming modes these modes can be used to program, erase, and verify flash memory contents. there are two modes: boot mode and user programming mode. ? automatic bit rate alignment in boot-mode data transfer, the h8/3337sf aligns its bit rate automatically to the host bit rate. ? protect modes there are three modes that enable flash memory to be protected from program, erase, and verify operations: hardware protect mode, software protect mode, and error protect mode. ? writer mode as an alternative to on-board programming, the flash memory can be programmed and erased in writer mode, using a general-purpose prom programmer. 497 21.1.3 block diagram figure 21.1 shows a block diagram of the flash memory. internal data bus (lower) bus interface and control section flmcr1 flmcr2 ebr2 8 internal data bus (upper) 8 md 1 md 0 operating mode upper byte (even address) legend: flmcr1: flash memory control register 1 flmcr2: flash memory control register 2 ebr2: erase block register 2 on-chip flash memory (60 kbytes) h'0000 h'0002 h'0004 h'0001 h'0003 h'0005 h'f77c h'f77e h'f77d h'f77f lower byte (odd address) figure 21.1 flash memory block diagram 498 21.1.4 input/output pins flash memory is controlled by the pins listed in table 21.2. table 21.2 flash memory pins pin name abbreviation input/ output function reset res input reset mode 1 md 1 input h8/3337sf operating mode setting mode 0 md 0 input h8/3337sf operating mode setting port 92 p9 2 input h8/3337sf operating mode setting when md1 = md0 = 0 port 91 p9 1 input h8/3337sf operating mode setting when md1 = md0 = 0 port 90 p9 0 input h8/3337sf operating mode setting when md1 = md0 = 0 transmit data txd 1 output sci1 transmit data output receive data rxd 1 input sci1 receive data input the transmit data and receive data pins are used in boot mode. 21.1.5 register configuration the flash memory is controlled by the registers listed in table 21.3. table 21.3 flash memory registers name abbreviation r/w initial value address flash memory control register 1 flmcr1 r/w * 2 h'80 h'ff80 flash memory control register 2 flmcr2 r/w * 2 h'00 * 3 h'ff81 erase block register 2 ebr2 r/w * 2 h'00 * 3 h'ff83 wait-state control register * 1 wscr r/w h'08 h'ffc2 notes: * 1 the wait-state control register is used to control the insertion of wait states by the wait- state controller and frequency division of clock signals for the on-chip supporting modules by the clock pulse generator. selection of the respective registers (or flmcr1, flmcr2, and ebr2) is performed by means of the flshe bit in the wait state control register (wscr). * 2 in modes in which the on-chip flash memory is disabled, these registers cannot be modified and return h'00 if read. * 3 initialized to h'00 when the swe bit is not set in flmcr1. 499 21.1.6 mode control register (mdcr) register configuration: the operating mode of the h8/3337sf is controlled by the mode pins and the mode control register (mdcr). table 21.4 shows the mdcr register configuration. table 21.4 register configuration name abbreviation r/w initial value address mode control register mdcr r/w undefined (depends on operating mode) h'ffc5 mode control register (mdcr) bit 76543210 expe * 1 mds1 mds0 initial value * 2 11 00 1 * 2 * 2 read/write r/w * 2 r r notes: * 1 h8/3337sf (s-mask model, single-power-supply on-chip flash memory version) only. otherwise, this is a reserved bit that is always read as 1. * 2 determined by the mode pins (md 1 and md 0 ). mdcr is an 8-bit register used to set the operating mode of the h8/3337sf and to monitor the current operating mode. bit 7?xpanded mode enable (expe): sets expanded mode. in mode 1, this bit is fixed at 1 and cannot be modified. in modes 2 and 3, this bit has a fixed initial value of 0 and cannot be modified. this bit can be read and written only in boot mode. bit 7: expe description 0 single-chip mode is selected 1 expanded mode is selected (writable in boot mode only) bits 6 and 5?eserved: these bits cannot be modified and are always read as 1. bits 4 and 3?eserved: these bits cannot be modified and are always read as 0. bit 2?eserved: this bit cannot be modified and is always read as 1. 500 bits 1 and 0?ode select 1 and 0 (mds1, mds0): these bits indicate the input levels at mode pins md 1 and md 0 (the current operating mode). bits mds1 and mds0 correspond to pins md 1 and md 0 , respectively. mds1 and mds0 are read-only bits, and cannot be modified. the mode pin (md 1 and md 0 ) input levels are latched into these bits when mdcr is read. 21.1.7 flash memory operating modes mode transition diagram: when the mode pins are set in the reset state and a reset start is effected, the microcontroller enters one of the operating modes as shown in figure 21.2. in user mode, the flash memory can be read but cannot be programmed or erased. modes in which the flash memory can be programmed and erased are boot mode, user programming mode, and writer mode. boot mode on-board programming mode user programming mode user mode with on-chip rom enabled reset state writer mode res * 1 * 2 notes: transitions between user mode and user programming mode should only be made when the cpu is not accessing the flash memory. * 1md 0 = md 1 = 0, p92 = p91 = p90 = 1 * 2md 0 = md 1 = 0, p92 = 0, p91 = p90 = 1 res res res figure 21.2 flash memory related state transitions 501 on-board programming modes ? boot mode flash memory h8/3337sf ram host on-board update routine sci application program (old version) new application program flash memory h8/3337sf ram host sci application program (old version) new application program flash memory h8/3337sf ram host sci flash memory erase boot program new application program flash memory h8/3337sf : program execution state ram host sci new application program boot program boot program area on-board update routine on-board update routine on-board update routine boot program area boot program boot program 1. initial state the flash memory is in the erased state when shipped. the procedure for rewriting an old version of an application program or data is described here. the user should prepare an on-board update routine and the new application program beforehand in the host. 2. sci communication check when boot mode is entered, the boot program in the h8/3337sf (already incorporated in the chip) is started, an sci communication check is carried out, and the boot program required for flash memory erasing is automatically transferred to the ram boot program area. 3. flash memory initialization the erase program in the boot program area (in ram) is executed, and the flash memory is initialized (to h'ff). in boot mode, total flash memory erasure is performed, without regard to blocks. 4. writing new application program the on-board update routine in the host to ram is transferred to ram by sci communication and executed, and the new application program in the host is written into the flash memory. figure 21.3 boot mode 502 ? user programming mode flash memory h8/3337sf ram host on-board update routine sci boot program new application program flash memory h8/3337sf ram host sci new application program flash memory h8/3337sf ram host sci flash memory erase boot program new application program flash memory h8/3337sf : program execution state ram host sci boot program on-board update routine boot program transfer program application program (old version) application program (old version) transfer program new application program transfer program transfer program on-board update routine on-board update routine 1. initial state (1) the program that will transfer the on-board update routine to on-chip ram should be written into the flash memory by the user beforehand. (2) the on-board update routine should be prepared in the host or in the flash memory. 2. on-board update routine transfer the transfer program in the flash memory is executed, and the on-board update routine is transferred to ram. 3. flash memory initialization the update routine in ram is executed, and the flash memory is initialized (to h'ff). erasing can be performed in block units, but not in byte units. 4. writing new application program next, the new application program in the host is written into the erased flash memory blocks. do not write to unerased blocks. figure 21.4 user programming mode (example) 503 differences between boot mode and user programming mode boot mode user programming mode total erase yes yes block erase no yes on-board update routine * program/program-verify erase/erase-verify program/program-verify note: * to be provided by the user, in accordance with the recommended algorithm. block configuration: the flash memory is divided into one 2-kbyte block, one 12-kbyte block, one 16-kbyte block, one 28-kbyte block, and four 1-kbyte blocks. address h'00000 address h'f77f 2 kbytes 28 kbytes 16 kbytes 12 kbytes 1 kbyte 1 kbyte 1 kbyte 1 kbyte 60 kbytes figure 21.5 flash memory blocks 504 21.2 flash memory register descriptions 21.2.1 flash memory control register 1 (flmcr1) bit 76543210 fwe swe ev pv e p initial value 1 0 0 0 0 0 0 0 read/write r r/w r/w r/w r/w r/w note: the flshe bit in wscr must be set to 1 in order for this register to be accessed. flmcr1 is an 8-bit register that controls the flash memory operating modes. program-verify mode or erase-verify mode is entered by setting swe to 1. program mode is entered by setting swe to 1 when fwe = 1, then setting the psu bit in flmcr2, and finally setting the p bit. erase mode is entered by setting swe to 1, then setting the esu bit in flmcr2, and finally setting the e bit. flmcr1 is initialized to h'80 by a reset, and in hardware standby mode and software standby mode. when on-chip flash memory is disabled, a read will return h'00, and writes are invalid. writes to bits ev and pv in flmcr1 are enabled only when swe = 1; writes to the e bit only when fwe = 1, swe = 1, and esu = 1; and writes to the p bit only when swe = 1 and psu = 1. bit 7?lash write enable (fwe): controls programming and erasing of on-chip flash memory. in the h8/3337sf, this bit cannot be modified and is always read as 1. bit 6?oftware write enable (swe): enables or disables the flash memory. this bit should be set before setting bits esu, psu, ev, pv, e, p, and eb7 to eb0, and should not be cleared at the same time as these bits. bit 6: swe description 0 writes disabled (initial value) 1 writes enabled bits 6 to 4?eserved: these bits cannot be modified and are always read as 0. 505 bit 3?rase-verify mode (ev): selects transition to or exit from erase-verify mode. (do not set the swe, esu, psu, pv, e, or p bit at the same time.) bit 3: ev description 0 exit from erase-verify mode (initial value) 1 transition to erase-verify mode [setting condition] when swe = 1 bit 2?rogram-verify mode (pv): selects transition to or exit from program-verify mode. (do not set the swe, esu, psu, ev, e, or p bit at the same time.) bit 2: pv description 0 exit from program-verify mode (initial value) 1 transition to program-verify mode [setting condition] when swe = 1 bit 1?rase mode (e): selects transition to or exit from erase mode. (do not set the swe, esu, psu, ev, pv, or p bit at the same time.) bit 1: e description 0 exit from erase mode (initial value) 1 transition to erase mode [setting condition] when swe = 1 and esu = 1 bit 0?rogram mode (p): selects transition to or exit from program mode. (do not set the swe, esu, psu, ev, pv, or e bit at the same time.) bit 0: p description 0 exit from program mode (initial value) 1 transition to program mode [setting condition] when swe = 1 and psu = 1 506 21.2.2 flash memory control register 2 (flmcr2) bit 76543210 fler esu psu initial value 0 0 0 0 0 0 0 0 read/write r r/w r/w note: the flshe bit in wscr must be set to 1 in order for this register to be accessed. flmcr2 is an 8-bit register used for monitoring of flash memory program/erase protection (error protection) and flash memory program/erase mode setup. flmcr2 is initialized to h'00 by a reset and in hardware standby mode. the esu and psu bits are cleared to 0 in software standby mode, hardware protect mode, and software protect mode. when on-chip flash memory is disabled, a read will return h'00. bit 7?lash memory error (fler): indicates that an error has occurred during an operation on flash memory (programming or erasing). when fler is set to 1, flash memory goes to the error- protection state. bit 7: fler description 0 flash memory is operating normally flash memory program/erase protection (error protection) is disabled [clearing conditions] reset, hardware standby mode, subactive mode, subsleep mode, watch mode (initial value) 1 an error occurred during flash memory programming/erasing flash memory program/erase protection (error protection) is enabled [setting condition] see error protection in section 21.4.5 bits 6 to 2?eserved: these bits cannot be modified and are always read as 0. 507 bit 1?rase setup (esu): prepares for a transition to erase mode. set this bit to 1 before setting the e bit in flmcr1. (do not set the swe, psu, ev, pv, e, or p bit at the same time.) bit 1: esu description 0 erase setup cleared (initial value) 1 erase setup [setting condition] when swe = 1 bit 0?rogram setup (psu): prepares for a transition to program mode. set this bit to 1 before setting the p bit in flmcr1. (do not set the swe, esu, ev, pv, e, or p bit at the same time.) bit 0: psu description 0 program setup cleared (initial value) 1 program setup [setting condition] when swe = 1 21.2.3 erase block register 2 (ebr2) bit 76543210 eb7 eb6 eb5 eb4 eb3 eb2 eb1 eb0 initial value 0 0 0 0 1 0 0 0 read/write r/w * r/w r/w r/w r/w r/w r/w r/w note: the flshe bit in wscr must be set to 1 in order for this register to be accessed. * writes to bit 7 are invalid in mode 2. ebr2 is an 8-bit register that designates flash-memory erase blocks for erasure. ebr2 is initialized to h'00 by a reset, in hardware standby mode and software standby mode, and when the swe bit in flmcr1 is not set. when a bit in ebr2 is set to 1, the corresponding block can be erased. other blocks are erase-protected. only one bit should be set in ebr2; do not set two or more bits. when on-chip flash memory is disabled, a read will return h'00, and writes are invalid. the flash memory block configuration is shown in table 21.5. 508 table 21.5 flash memory erase blocks block (size) 60-kbyte version addresses eb0 (1 kbyte) h'0000 h'03ff eb1 (1 kbyte) h'0400 h'07ff eb2 (1 kbyte) h'0800 h'0bff eb3 (1 kbyte) h'0c00 h'0fff eb4 (28 kbytes) h'1000 h'7fff eb5 (16 kbytes) h'8000 h'bfff eb6 (12 kbytes) h'c000 h'ef7f eb7 (2 kbytes) h'ef80 h'f77f 21.2.4 wait-state control register (wscr) bit 76543210 ckdbl flshe wms1 wms0 wc1 wc0 initial value 0 0 0 0 1 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w wscr is an 8-bit readable/writable register that controls frequency division of the clock signals supplied to the supporting modules. it also controls wait state controller wait settings, ram area setting for dual-power-supply flash memory, and selection/non-selection of single-power-supply flash memory control registers. wscr is initialized to h'08 by a reset and in hardware standby mode. it is not initialized in software standby mode. bits 7 and 6?eserved: these bits are reserved, but can be written and read. their initial value is 0. bit 5?lock double (ckdbl): controls frequency division of clock signals supplied to the on- chip supporting modules. for details, see section 6, clock pulse generator. 509 bit 4?lash memory control register enable (flshe): when the flshe bit is set to 1, the flash memory control registers can be read and written to. when flshe is cleared to 0, the flash memory control registers are unselected. in this case, the contents of the flash memory contents are retained. bit 4: flshe description 0 flash memory control registers are in unselected state (initial value) 1 flash memory control registers are in selected state bits 3 and 2?ait mode select 1 and 0 (wms1, wms0) bits 1 and 0?ait count 1 and 0 (wc1, wc0) these bits control insertion of wait states by the wait-state controller. for details, see section 5, wait-state controller. 21.3 on-board programming modes when an on-board programming mode is selected, the on-chip flash memory can be programmed, erased, and verified. there are two on-board programming modes: boot mode and user programming mode. table 21.6 indicates how to select the on-board programming modes. user programming mode operation can be performed by setting control bits with software. a state transition diagram for flash memory related modes is shown in figure 21.2. table 21.6 on-board programming mode selection mode selection md 1 md 0 p9 2 p9 1 p9 0 boot mode 00111 user programming 1 0 mode 1 21.3.1 boot mode to use boot mode, a user program for programming and erasing the flash memory must be provided in advance on the host machine (which may be a personal computer). serial communication interface (sci) channel 1 is used in asynchronous mode. when a reset state is executed after the h8/3337sf pins have been set to boot mode, the built-in boot program is activated, and the on-board update routine provided in the host is transferred sequentially to the h8/3337sf using the serial communication interface (sci). the h8/3337sf writes the on-board update routine received via the sci to the on-board update routine area in the on-chip ram. after the transfer is completed, execution branches to the first address of the on- 510 board update routine area, and the on-board update routine execution state is entered (flash memory programming is performed). therefore, a routine conforming to the programming algorithm described later must be provided in the on-board update routine transferred from the host. figure 21.6 shows the system configuration in boot mode, and figure 21.7 shows the boot mode execution procedure. rxd1 txd1 sci1 h8/3337sf flash memory reception of programming data transmission of verification data host on-chip ram figure 21.6 boot-mode system configuration boot-mode execution procedure: figure 21.7 shows the boot-mode execution procedure. 511 n = n? note: if a memory cell malfunctions and cannot be erased, the h8/3337sf transmits one h'ff byte to report an erase error, halts erasing, and halts further operations. yes no program h8/3337sf pins for boot mode, and reset n = 1 n + 1 figure 21.7 boot mode flowchart 512 automatic alignment of sci bit rate start bit d0 d1 d2 d3 d4 d5 d6 d7 stop bit this low period (9 bits) is measured (h'00 data) high for at least 1 bit figure 21.8 measurement of low period in data transmitted from host when started in boot mode, the h8/3337sf measures the low period in asynchronous sci data (h'00) transmitted from the host. the data format is eight data bits, one stop bit, and no parity bit. from the measured low period (9 bits), the h8/3337sf computes the host? bit rate. after aligning its own bit rate, the h8/3337sf sends the host one byte of h'00 data to indicate that bit-rate alignment is completed. the host should check that this alignment-completed indication is received normally and send one h'55 byte back to the h8/3337sf. if the alignment-completed indication is not received normally, the h8/3337f should be reset, then restarted in boot mode to measure the low period again. there may be some alignment error between the host? and h8/3337sf? bit rates, depending on the host? transmission bit rate and the h8/3337sf? system clock frequency (f osc ). to have the sci operate normally, set the host? transfer bit rate to 2400, 4800, or 9600 bps. table 21.7 lists typical host transfer bit rates and indicates the system clock frequency ranges over which the h8/3337sf can align its bit rate automatically. boot mode should be used within these frequency ranges. table 21.7 system clock frequencies permitting automatic bit-rate alignment by h8/3337sf host bit rate system clock frequencies (f osc ) permitting automatic bit-rate alignment by h8/3337sf 9600 bps 8 mhz to 16 mhz 4800 bps 4 mhz to 16 mhz 2400 bps 2 mhz to 16 mhz ram area allocation in boot mode: in boot mode, the 128 bytes from h'ff00 to h'ff7f are reserved for use by the boot program, as shown in figure 21.9. the user program is transferred into the area from h'f780 to h'fdff (1664 bytes). the boot program area can be used after the transition to execution of the user program transferred into ram. if a stack area is needed, set it within the user program. 513 h'ff00 h'ff7f h'f780 boot program area * (128 bytes) user program transfer area (1664 bytes) h'fdff note: * this area cannot be used until the h8/3337sf starts to execute the user program transferred to ram. note that even after the branch to the user program, the boot program area still contains the boot program. figure 21.9 ram areas in boot mode notes on use of boot mode 1. when the h8/3337sf comes out of reset in boot mode, it measures the low period of the input at the sci s rxd 1 pin. the reset should end with rxd 1 high. after the reset ends, it takes about 100 states for the h8/3337sf to get ready to measure the low period of the rxd 1 input. 2. in boot mode, if any data has been programmed into the flash memory (if all data is not h'ff), all flash memory blocks are erased. boot mode is for use when user programming mode is unavailable, such as the first time on-board programming is performed, or if the program activated in user programming mode is accidentally erased. 3. interrupts cannot be used while the flash memory is being programmed or erased. 4. the rxd 1 and txd 1 pins should be pulled up on-board. 5. before branching to the user program (at address h'e880 in the ram area), the h8/3337sf terminates transmit and receive operations by the on-chip sci (by clearing the re and te bits of serial control register scr to 0 in channel 1), but the auto-aligned bit rate remains set in bit rate register brr. the transmit data output pin (txd 1 ) is in the high output state (in port 8, bits p8 4 ddr of the port 8 data direction register and p8 4 dr of the port 8 data register are set to 1). 514 at this time, the values of general registers in the cpu are undetermined. thus these registers should be initialized immediately after branching to the user program. especially in the case of the stack pointer (sp), which is used implicitly in subroutine calls, etc., the stack area used by the user program should be specified. there are no other changes to the initialized values of other registers. 6. boot mode can be entered by starting from a reset after pin settings are made according to the mode setting conditions listed in table 21.6. in the h8/3337sf, p9 2 , p9 1 , and p9 0 can be used as i/o ports if boot mode selection is detected when reset is released *1 . boot mode can be released by driving the reset pin low, waiting at least 20 system clock cycles, then setting the mode pins and releasing the reset *1 . boot mode can also be released if a watchdog timer overflow reset occurs. the mode pin input levels must not be changed during boot mode. 7. if the input level of a mode pin is changed during a reset (e.g., from low to high), the resultant switch in the microcontroller s operating mode will affect the bus control output signals ( as rd wr res figure 21.10 programming mode timing 515 21.3.2 user programming mode when set to user programming mode, the h8/3337sf can erase and program its flash memory by executing a user program. on-board updates of the on-chip flash memory can be carried out by providing an on-board circuit for supplying programming data, and storing an update program in part of the program area. to select user programming mode, start up in a mode that enables the on-chip flash memory (mode 2 or 3). in user programming mode, the on-chip supporting modules operate as they normally would in mode 2 or 3, except for the flash memory. the flash memory cannot be read while the swe bit is set to 1 in order to perform programming or erasing, so the update program must be executed in on-chip ram or external memory. user programming mode execution procedure (example): figure 21.11 shows the execution procedure for user programming mode when the on-board update routine is executed in ram. branch to flash memory on-board update routine in ram execute flash memory on-board update routine (update flash memory) branch to application program in flash memory the transfer program (and on-board update program as required) is written in flash memory ahead of time by the user. note: start the watchdog timer to prevent over-erasing due to program runaway, etc. transfer on-board update routine into ram set md 1 and md 0 to 10 or 11 start from reset figure 21.11 user programming mode operation (example) 516 21.4 programming/erasing flash memory in the on-board programming modes, flash memory programming and erasing is performed by software, using the cpu. there are four flash memory operating modes: program mode, erase mode, program-verify mode, and erase-verify mode. transitions to these modes can be made by setting the psu and esu bits in flmcr2, and the p, e, pv, and ev bits in flmcr1. the flash memory cannot be read while being programmed or erased. therefore, the program that controls flash memory programming/erasing (the programming control program) should be located and executed in on-chip ram or external memory. notes: 1. operation is not guaranteed if setting/resetting of the swe, ev, pv, e, and p bits in flmcr1, and the esu and psu bits in flmcr2, is executed by a program in flash memory. 2. perform programming in the erased state. do not perform additional programming on previously programmed addresses. 21.4.1 program mode follow the procedure shown in the program/program-verify flowchart in figure 21.12 to write data or programs to flash memory. performing program operations according to this flowchart will enable data or programs to be written to flash memory without subjecting the device to voltage stress or sacrificing program data reliability. programming should be carried out 32 bytes at a time. for the wait times (x, y, z, , , ) 517 21.4.2 program-verify mode in program-verify mode, the data written in program mode is read to check whether it has been correctly written in the flash memory. after the elapse of a given programming time, the programming mode is exited (the p bit in flmcr1 is cleared, then the psu bit in flmcr2 is cleared at least ( 518 set swe bit in flmcr1 wait (x) still in erased state; no action ram program data storage area (32 bytes) reprogram data storage area (32 bytes) transfer reprogram data to reprogram data area verify data 1 0 1 1 0 1 0 1 0 0 1 1 end of programming perform programming in the erased state. do not perform additional programming on previously programmed addresses. figure 21.12 program/program-verify flowchart 519 21.4.3 erase mode flash memory erasing should be performed block by block following the procedure shown in the erase/erase-verify flowchart (single-block erase) shown in figure 21.13. the wait times (x, y, z, , , ) 21.4.4 erase-verify mode in erase-verify mode, data is read after memory has been erased to check whether it has been correctly erased. after the elapse of the erase time, erase mode is exited (the e bit in flmcr1 is cleared, then the esu bit in flmcr2 is cleared at least ( 520 end of erasing start set swe bit in flmcr1 set esu bit in flmcr2 set e bit in flmcr1 wait (x) figure 21.13 erase/erase-verify flowchart (single-block erase) 521 21.4.5 protect modes there are three modes for protecting flash memory from programming and erasing: software protection, hardware protection, and error protection. these protection modes are described below. software protection: software protection can be implemented by setting the swe bit in flash memory control register 1 (flmcr1), and setting erase block register 2 (ebr2). software protection prevents transitions to program mode and erase mode even if the p or e bit is set in flmcr1. details of software protection are shown in table 21.8. table 21.8 software protection functions item description program erase swe bit protect clearing the swe bit to 0 in flmcr1 sets the program/erase-protected state for all blocks. (execute in on-chip ram or external memory.) yes yes block protect individual blocks can be protected from erasing and programming by erase block register 2 (ebr2). if h'00 is set in ebr2, all blocks are protected from erasing and programming. yes hardware protection: hardware protection refers to a state in which programming and erasing of flash memory is forcibly suspended or disabled. at this time, the flash memory control registers 1 and 2 (flmcr1, flmcr2) and erase block register 2 (ebr2) settings are reset. details of hardware protection are shown in table 21.9. table 21.9 hardware protection functions item description program erase reset and standby protect when a reset occurs (including a watchdog timer reset) or standby mode is entered, flmcr1, flmcr2, and ebr2 are initialized, disabling programming and erasing. note that res res res 522 error protection: in error protection, an error is detected when microcontroller runaway occurs during flash memory programming/erasing, or operation is not performed in accordance with the program/erase algorithm, and the program/erase operation is aborted. aborting the program/erase operation prevents damage to the flash memory due to overprogramming or overerasing. if the microcontroller malfunctions during flash memory programming/erasing, the fler bit is set to 1 in flmcr2 and the error protection state is entered. the flmcr1, flmcr2, and ebr2 settings are retained, but program mode or erase mode is aborted at the point at which the error occurred. program mode or erase mode cannot be re-entered by re-setting the p or e bit. however, pv and ev bit setting is enabled, and a transition can be made to verify mode. fler bit setting conditions are as follows: 1. when flash memory is read during programming/erasing (including a vector read or instruction fetch) 2. immediately after the start of exception handling (excluding a reset) during programming/erasing 3. when a sleep instruction (including software standby) is executed during programming/erasing 4. when the bus is released during programming/erasing error protection is released only by a power-on reset. figure 21.14 shows the flash memory state transition diagram. 523 rd vf res stby res stby rd vf pr er pr er rd vf pr er rd vf pr er res stby figure 21.14 flash memory state transitions 21.4.6 interrupt handling during flash memory programming and erasing all interrupts, including nmi input, should be disabled when flash memory is being programmed or erased (while the p or e bit is set in flmcr1) and while the boot program is executing in boot mode *1 , to give priority to the program or erase operation. there are three reasons for this: 1. interrupt occurrence during programming or erasing might cause a violation of the programming or erasing algorithm, with the result that normal operation could not be assured. 2. in the interrupt exception handling sequence during programming or erasing, the vector would not be read correctly *2 , possibly resulting in microcontroller runaway. 3. if an interrupt occurred during boot program execution, it would not be possible to execute the normal boot mode sequence. for these reasons, there are conditions for disabling interrupts in the on-board programming modes alone, as an exception to the general rule. however, this provision does not guarantee normal erasing and programming or microcontroller operation. all requests, including nmi, must therefore be disabled inside and outside the microcontroller when flash memory is programmed or erased. interrupts are also disabled in the error protection state while the p or e bit setting in flmcr1 is held. 524 notes: *1 interrupt requests must be disabled inside and outside the microcontroller until programming by the update program has been completed. *2 the vector may not be read correctly in this case for the following two reasons: if flash memory is read while being programmed or erased (while the p or e bit is set in flmcr1), correct read data will not be obtained (undetermined values will be returned). if a value has not yet been written in the interrupt vector table, interrupt exception handling will not be executed correctly. 21.5 flash memory writer mode (h8/3337sf) 21.5.1 writer mode setting programs and data can be written and erased in writer mode as well as in the on-board programming modes. in writer mode, the on-chip rom can be freely programmed using a prom programmer that supports the hitachi microcomputer device type* with 64-kbyte on-chip flash memory*. flash memory read mode, auto-program mode, auto-erase mode, and status read mode are supported with this device type. in auto-program mode, auto-erase mode, and status read mode, a status polling procedure is used, and in status read mode, detailed internal signals are output after execution of an auto-program or auto-erase operation. note: * the h8/3437 should be used with the prom programmer programming voltage set to 5.0 v. table 21.10 writer mode pin settings pin names settings mode pins: md 1 , md 0 low level input to md 1 and md 0 stby res 21.5.2 socket adapter and memory map in writer mode, a socket adapter for the relevant kind of package is attached to the prom programmer. socket adapters are available for all prom programmer manufacturers supporting the hitachi microcomputer device type with 64-kbyte on-chip flash memory. 525 figure 21.15 shows the memory map in writer mode, and table 21.10 shows writer mode pin settings. for pin names in writer mode, see section 1.3.2, pin functions in each operating mode. on-chip rom area h8/3337sf writer mode h'0000 h'f77f h'0000 h'f77f h'1ffff mcu mode undetermined values output figure 21.15 memory map in writer mode 21.5.3 operation in writer mode table 21.11 shows how to select the various operating modes when using writer mode, and table 21.12 lists the commands used in writer mode. details of each mode are given below. ? ? ? ? 526 table 21.11 operating mode selection in writer mode pins mode ce oe we fo7?o0 fa17?a0 read l l h data output ain * 2 output disable l h h high impedance x command write l h l data input ain * 2 chip disable * 1 h x x high impedance x notes: * 1 chip disable is not a standby state; internally, it is an operation state. * 2 ain indicates that there is also address input in auto-program mode. table 21.12 writer mode commands 1st cycle 2nd cycle command cycles mode address data mode address data memory read mode 1 + n write x h'00 read ra dout auto-program mode 129 write x h'40 write wa din auto-erase mode 2 write x h'20 write x h'20 status read mode 2 write x h'71 write x h'71 notes: 1. in auto-program mode, 129 cycles are required for command writing by a simultaneous 128-byte write. 2. in memory read mode, the number of cycles depends on the number of address write cycles (n). 527 memory read mode 1. after completion of auto-program/auto-erase/status read operations, a transition is made to the command wait state. when reading memory contents, a transition to memory read mode must first be made with a command write, after which the memory contents are read. 2. in memory read mode, command writes can be performed in the same way as in the command wait state. 3. once memory read mode has been entered, consecutive reads can be performed. 4. after powering up, memory read mode is entered. table 21.13 ac characteristics in memory read mode (conditions: v cc = 5.0 v 10%, v ss = 0 v, t a = 25 c 5 c) item symbol min max unit notes command write cycle t nxtc 20 ce ce we we ce oe we we figure 21.16 timing waveforms for memory read after command write 528 table 21.14 ac characteristics in transition from memory read mode to another mode (conditions: v cc = 5.0 v 10%, v ss = 0 v, t a = 25 c 5 c) item symbol min max unit notes command write cycle t nxtc 20 ce ce we we ce oe we we oe figure 21.17 timing waveforms for transition from memory read mode to another mode 529 table 21.15 ac characteristics in memory read mode (conditions: v cc = 5.0 v 10%, v ss = 0 v, t a = 25 c 5 c) item symbol min max unit notes access time t acc 20 ce oe ce oe we figure 21.18 timing waveforms for ce and oe enable state read ce oe we figure 21.19 timing waveforms for ce and oe clocked read 530 auto-program mode ? ac characteristics table 21.16 ac characteristics in auto-program mode (conditions: v cc = 5.0 v 10%, v ss = 0 v, t a = 25 c 5 c) item symbol min max unit notes command write cycle t nxtc 20 ce ce we we ce oe we figure 21.20 auto-program mode timing waveforms 531 ? notes on use of auto-program mode 1. in auto-program mode, 128 bytes are programmed simultaneously. this should be carried out by executing 128 consecutive byte transfers. 2. a 128-byte data transfer is necessary even when programming fewer than 128 bytes. in this case, h'ff data must be written to the extra addresses. 3. the lower 8 bits of the transfer address must be h'00 or h'80. if a value other than a valid address is input, processing will switch to a memory write operation but a write error will be flagged. 4. memory address transfer is performed in the second cycle (figure 21.19). do not perform transfer after the second cycle. 5. do not perform a command write during a programming operation. 6. perform one auto-programming operation for a 128-byte block for each address. characteristics are not guaranteed for two or more programming operations. 7. confirm normal end of auto-programming by checking fo6. alternatively, status read mode can also be used for this purpose (in fo7 status polling, the pin is the auto-program operation end identification pin). 8. status polling fo6 and fo7 pin information is retained until the next command write. as long as the next command write has not been performed, reading is possible by enabling ce oe 532 auto-erase mode ? ac characteristics table 21.17 ac characteristics in auto-erase mode (conditions: v cc = 5.0 v 10%, v ss = 0 v, t a = 25 c 5 c) item symbol min max unit notes command write cycle t nxtc 20 ce ce we we ce oe we figure 21.21 auto-erase mode timing waveforms 533 ? notes on use of erase-program mode 1. auto-erase mode supports only total memory erasing. 2. do not perform a command write during auto-erasing. 3. confirm normal end of auto-erasing by checking fo6. alternatively, status read mode can also be used for this purpose (in fo7 status polling, the pin is the auto-erase operation end identification pin). 4. status polling fo6 and fo7 pin information is retained until the next command write. as long as the next command write has not been performed, reading is possible by enabling ce oe status read mode 1. status read mode is used to identify what kind of abnormal end has occurred. this mode should be used if an abnormal end occurs in auto-program or auto-erase mode. 2. the return code is retained until a command write for a mode other than status read mode is executed. table 21.18 ac characteristics in status read mode (conditions: v cc = 5.0 v 10%, v ss = 0 v, t a = 25 c 5 c) item symbol min max unit notes command write cycle t nxtc 20 ce ce oe ce we we 534 ce oe we figure 21.22 status read mode timing waveforms table 21.19 status read mode return codes pin fo7 fo6 fo5 fo4 fo3 fo2 fo1 fo0 attribute normal end identification command error programming error erase error programming or erase count exceeded valid address error initial value 0 0 0 0 0 0 0 0 indications normal end: 0 abnormal end: 1 command error: 1 otherwise: 0 programming error: 1 otherwise: 0 erase error: 1 otherwise: 0 count exceeded: 1 otherwise: 0 valid address error: 1 otherwise: 0 note: fo2 and fo3 are undefined. status polling 1. in fo7 status polling, fo7 is a flag that indicates the operating status in auto-program or auto- erase mode. 2. in fo6 status polling, fo6 is a flag that indicates a normal or abnormal end in auto-program or auto-erase mode. table 21.20 status polling output truth table pin internal operation in progress abnormal end normal end fo7 0 1 0 1 fo6 0 0 1 1 fo0 fo5 0 0 0 0 535 writer mode transition time: commands cannot be accepted during the oscillation settling period or the writer mode setup period. after the writer mode setup time, a transition is made to memory read mode. table 21.21 stipulated transition times to command wait state item symbol min max unit notes standby release (oscillation settling time) t osc1 10 ms writer mode setup time t bmv 10 ms v cc hold time t dwn 0ms v cc res figure 21.23 oscillation settling time, boot program transfer time, and power-down sequence cautions on memory programming 1. when programming addresses which have previously been programmed, carry out auto- erasing before auto-programming. 2. when performing programming using writer mode on a chip that has been programmed/erased in an on-board programming mode, auto-erasing is recommended before carrying out auto- programming. notes: 1. the flash memory is initially in the erased state when the device is shipped by hitachi. for other chips for which the erasure history is unknown, it is recommended that auto- erasing be executed to check and supplement the initialization (erase) level. 2. auto-programming should be performed once only on the same address block. 536 21.6 flash memory programming and erasing precautions read these precautions before using writer mode, on-board programming mode, or flash memory emulation by ram. (1) program with the specified voltage and timing. when using a prom programmer to reprogram the on-chip flash memory in the single-power- supply model (s-mask model), use a prom programmer that supports the hitachi microcomputer device type with 64-kbyte on-chip flash memory (5.0 v programming voltage), do not set the programmer to the hn28f101 3.3 v programming voltage and only use the specified socket adapter. failure to observe these precautions may result in damage to the device. (2) before programming, check that the chip is correctly mounted in the prom programmer. overcurrent damage to the device can occur if the index marks on the prom programmer socket, socket adapter, and chip are not correctly aligned. (3) don? touch the socket adapter or chip while programming. touching either of these can cause contact faults and write errors. (4) set h'ff as the prom programmer buffer data for addresses h'f780 to h'1ffff. the h8/3337sf prom size is 60 kbytes. addresses h'f780 to h'1ffff always read h'ff, so if h'ff is not specified as programmer data, a block error will occur. (5) use the recommended algorithms for programming and erasing flash memory. these algorithms are designed to program and erase without subjecting the device to voltage stress and without sacrificing the reliability of programmed data. before setting the program (p) or erase (e) bit in flash memory control register 1 (flmcr1), set the watchdog timer to ensure that the p or e bit does not remain set for more than the specified time. (6) for details on interrupt handling while flash memory is being programmed or erased, see section 21.4.6, interrupt handling during flash memory programming and erasing. (7) cautions on accessing flash memory control registers 1. flash memory control register access state in each operating mode the h8/3337sf has flash memory control registers located at addresses h'ff80 (flmcr1), h'ff81 (flmcr2), and h'ff83 (ebr2). these registers can only be accessed when the flshe bit is set to 1 in the wait-state control register (wscr). table 21.22 shows the area accessed for the above addresses in each mode, when flshe = 0 and when flshe = 1. 537 table 21.22 area accessed in each mode with flshe = 0 and flshe = 1 mode 1 mode 2 mode 3 flshe = 1 reserved area (always h'ff) flash memory control register initial values fllmcr1 = h'80 flmcr2 = h'00 ebr2 = h'00 flshe = 0 external address space external address space reserved area (always h'ff) 2. when a flash memory control register is accessed in mode 2 (expanded mode with on-chip rom enabled) when a flash memory control register is accessed in mode 2, it can be read or written to if flshe = 1, but if flshe = 0, external address space will be accessed. it is therefore essential to confirm that flshe is set to 1 before accessing these registers. 3. to check whether flshe = 0 or 1 in mode 3 (single-chip mode) when address h'ff80 is accessed in mode 3, if flshe = 1, flmcr1 is read/written to, and its initial value after a reset is h'80. when flshe = 0, however, this address is a reserved area that cannot be modified and always reads h'ff. 538 539 section 22 power-down state 22.1 overview the h8/3337 series and h8/3397 series have a power-down state that greatly reduces power consumption by stopping some or all of the chip functions. the power-down state includes three modes: 1. sleep mode 2. software standby mode 3. hardware standby mode table 22.1 lists the conditions for entering and leaving the power-down modes. it also indicates the status of the cpu, on-chip supporting modules, etc. in each power-down mode. table 22.1 power-down state state mode entering procedure clock cpu cpu reg?. sup. mod. ram i/o ports exiting methods sleep mode execute sleep instruction active halted held active held held ? interrupt ? res ? stby software standby mode set ssby bit in syscr to 1, then execute sleep instruction halted halted held halted and initialized held held ? nmi ? irq 0 irq 2 irq 6 (incl. keyin 0 keyin 7 ) ? res ? stby hardware standby mode set stby pin to low level halted halted undeter- mined halted and initialized held high impe- dance state ? stby and res note: syscr: system control register ssby: software standby bit 540 22.1.1 system control register (syscr) four of the eight bits in the system control register (syscr) control the power-down state. these are bit 7 (ssby) and bits 6 to 4 (sts2 to sts0). see table 22.2. table 22.2 system control register name abbreviation r/w initial value address system control register syscr r/w h'09 h'ffc4 bit 76543210 ssby sts2 sts1 sts0 xrst nmieg hie rame initial value 0 0 0 0 1 0 0 1 read/write r/w r/w r/w r/w r r/w r/w r/w bit 7?oftware standby (ssby): this bit enables or disables the transition to software standby mode. on recovery from the software standby mode by an external interrupt, ssby remains set to 1. to clear this bit, software must write a 0. bit 7: ssby description 0 the sleep instruction causes a transition to sleep mode. (initial value) 1 the sleep instruction causes a transition to software standby mode. 541 bits 6 to 4?tandby timer select 2 to 0 (sts2 to sts0): these bits select the clock settling time when the chip recovers from software standby mode by an external interrupt. during the selected time, the clock oscillator runs but the cpu and on-chip supporting modules remain in standby. set bits sts2 to sts0 according to the clock frequency to obtain a settling time of at least 8 ms. see table 22.3. ? ztat and mask rom versions bit 6: sts2 bit 5: sts1 bit 4: sts0 description 0 0 0 settling time = 8,192 states (initial value) 1 settling time = 16,384 states 1 0 settling time = 32,768 states 1 settling time = 65,536 states 1 0 settling time = 131,072 states 1 unused ? f-ztat version bit 6: sts2 bit 5: sts1 bit 4: sts0 description 0 0 0 settling time = 8,192 states (initial value) 1 settling time = 16,384 states 1 0 settling time = 32,768 states 1 settling time = 65,536 states 1 0 0 settling time = 131,072 states 1 settling time = 1,024 states 1 unused notes: when 1,024 states (sts2 to sts0 = 101) is selected, the following points should be noted. if a period exceeding ?/1,024 (e.g. ?/2,048) is specified when selecting the 8-bit timer, pwm timer, or watchdog timer clock, the counter in the timer will not count up normally when 1,024 states is specified for the setting time. to avoid this problem, set the sts value just before the transition to software standby mode (before executing the sleep instruction), and re-set the value of sts2 to sts0 to a value from 000 to 100 directly after software standby mode is cleared by an interrupt. 542 22.2 sleep mode 22.2.1 transition to sleep mode when the ssby bit in the system control register is cleared to 0, execution of the sleep instruction causes a transition from the program execution state to sleep mode. after executing the sleep instruction, the cpu halts, but the contents of its internal registers remain unchanged. the on-chip supporting modules continue to operate normally. 22.2.2 exit from sleep mode the chip exits sleep mode when it receives an internal or external interrupt request, or a low input at the res or stby pin. exit by interrupt: an interrupt releases sleep mode and starts the cpu? interrupt-handling sequence. if an interrupt from an on-chip supporting module is disabled by the corresponding enable/disable bit in the module? control register, the interrupt cannot be requested, so it cannot wake the chip up. similarly, the cpu cannot be awakened by an interrupt other than nmi if the i (interrupt mask) bit is set when the sleep instruction is executed. exit by res pin: when the res pin goes low, the chip exits from sleep mode to the reset state. exit by stby pin: when the stby pin goes low, the chip exits from sleep mode to hardware standby mode. 543 22.3 software standby mode 22.3.1 transition to software standby mode to enter software standby mode, set the standby bit (ssby) in the system control register (syscr) to 1, then execute the sleep instruction. in software standby mode, the system clock stops and chip functions halt, including both cpu functions and the functions of the on-chip supporting modules. power consumption is reduced to an extremely low level. the on-chip supporting modules and their registers are reset to their initial states, but as long as a minimum necessary voltage supply is maintained, the contents of the cpu registers and on-chip ram remain unchanged. i/o ports retain their states. 22.3.2 exit from software standby mode the chip can be brought out of software standby mode by an res input, stby input, or external interrupt input at the nmi pin, irq 0 to irq 2 pins, or irq 6 pin (including keyin 0 to keyin 7 ). exit by interrupt: when an nmi, irq 0 , irq 1 , irq 2 , or irq 6 interrupt request signal is input, the clock oscillator begins operating. after the waiting time set in bits sts2 to sts0 of syscr, a stable clock is supplied to the entire chip, software standby mode is released, and interrupt exception-handling begins. irq 3 , irq 4 , irq 5 , and irq 7 interrupts should be disabled before the transition to software standby (clear irq3e, irq4e, irq5e, and irq7e to 0). exit by res pin: when the res input goes low, the clock oscillator begins operating. when res is brought to the high level (after allowing time for the clock oscillator to settle), the cpu starts reset exception handling. be sure to hold res low long enough for clock oscillation to stabilize. exit by stby pin: when the stby input goes low, the chip exits from software standby mode to hardware standby mode. 544 22.3.3 clock settling time for exit from software standby mode set bits sts2 to sts0 in syscr as follows: ? crystal oscillator set sts2 to sts0 for a settling time of at least 8 ms. table 22.3 lists the settling times selected by these bits at several clock frequencies. ? external clock the sts bits can be set to any value. the shortest time setting (sts2=sts1=sts0=0) is recommended in most cases. when 1,024 states (sts2 to sts0 = 101) is selected, the following points should be noted. if a period exceeding ?/1,024 (e.g. ?/2,048) is specified when selecting the 8-bit timer, pwm timer, or watchdog timer clock, the counter in the timer will not count up normally when 1,024 states is specified for the setting time. to avoid this problem, set the sts value just before the transition to software standby mode (before executing the sleep instruction), and re-set the value of sts2 to sts0 to a value from 000 to 100 directly after software standby mode is cleared by an interrupt. table 22.3 times set by standby timer select bits (unit: ms) settling time system clock frequency (mhz) sts2 sts1 sts0 (states) 16 12 10 864210.5 0 0 0 8,192 0.51 0.65 0.8 1.0 1.3 2.0 4.1 8.2 16.4 0 0 1 16,384 1.0 1.3 1.6 2.0 2.7 4.1 8.2 16.4 32.8 0 1 0 32,768 2.0 2.7 3.3 4.1 5.5 8.2 16.4 32.8 65.5 0 1 1 65,536 4.1 5.5 6.6 8.2 10.9 16.4 32.8 65.5 131.1 1 0 0/ * 131,072 8.2 10.9 13.1 16.4 21.8 32.8 65.5 131.1 262.1 note: recommended values are printed in boldface. * f-ztat version/ztat and mask-rom versions. 545 22.3.4 sample application of software standby mode in this example the chip enters the software standby mode when nmi goes low and exits when nmi goes high, as shown in figure 22.1. the nmi edge bit (nmieg) in the system control register is originally cleared to 0, selecting the falling edge. when nmi goes low, the nmi interrupt handling routine sets nmieg to 1, sets ssby to 1 (selecting the rising edge), then executes the sleep instruction. the chip enters software standby mode. it recovers from software standby mode on the next rising edge of nmi . n mi figure 22.1 nmi timing in software standby mode (application example) 546 22.3.5 application notes 1. the i/o ports retain their present states in software standby mode. thus, current dissipation caused by the output current is not reduced. ; set the ssby bit ; execute the sleep instruction bset sleep #7, @syscr:8 ; set the ssby bit ; write the sleep code (h'0180) ; to ram ; write the rts code (h'5470) ; to ram ; subroutine branch to that location * registers and ram addresses are arbitrary. bset mov. w mov. w mov. w mov. w jsr #7, @syscr:8 #h' 0180, r0 r0, @h'ff00 #h' 5470, r0 r0, @h'ff02 @h'ff00 replace the underlined part (sleep instruction) with the code shown below. note: when a sleep instruction is executed in rom, the current responsible for this bug also flows when a sleep mode transition is made. therefore, to further reduce current dissipation in sleep mode, also, software should be modified so that the sleep instruction is executed in ram when making a sleep mode transition. 547 22.4 hardware standby mode 22.4.1 transition to hardware standby mode regardless of its current state, the chip enters hardware standby mode whenever the stby pin goes low. hardware standby mode reduces power consumption drastically by halting the cpu, stopping all the functions of the on-chip supporting modules, and placing i/o ports in the high-impedance state. the registers of the on-chip supporting modules are reset to their initial values. only the on- chip ram is held unchanged, provided the minimum necessary voltage supply is maintained. notes: 1. the rame bit in the system control register should be cleared to 0 before the stby 22.4.2 recovery from hardware standby mode recovery from the hardware standby mode requires inputs at both the stby res res res 548 22.4.3 timing relationships in hardware standby mode figure 22.2 shows the timing relationships in hardware standby mode. in the sequence shown, first res stby stby res res stby figure 22.2 hardware standby mode timing 549 section 23 electrical characteristics 23.1 absolute maximum ratings table 23.1 lists the absolute maximum ratings. table 23.1 absolute maximum ratings item symbol rating unit supply voltage v cc ?.3 to +7.0 v flash memory programming voltage (dual-power-supply f-ztat version) fv pp ?.3 to +13.0 v programming voltage v pp ?.3 to +13.5 v input voltage pins other than ports 7, md 1 , v in ?.3 to v cc + 0.3 v port 7 v in ?.3 to av cc + 0.3 v md 1 v in dual-power-supply f-ztat version: ?.3 to +13.0 other versions: ?.3 to v cc + 0.3 v analog supply voltage av cc ?.3 to +7.0 v analog input voltage v an ?.3 to av cc + 0.3 v operating temperature t opr regular specifications: ?0 to +75 ?c wide-range specifications: ?0 to +85 ?c storage temperature t stg ?5 to +125 ?c note: exceeding the absolute maximum ratings shown in table 23.1 can permanently destroy the chip. * * fv pp must not exceed 13 v and v pp must not exceed 13.5 v, including peak overshoot. in the dual-power-supply f-ztat version, md 1 must not exceed 13 v, including peak overshoot. 550 23.2 electrical characteristics 23.2.1 dc characteristics table 23.2 lists the dc characteristics of the 5-v version. table 23.3 lists the dc characteristics of 4-v version. table 23.4 lists the dc characteristics of the 3-v version. table 23.5 gives the allowable current output values of the 5-v and 4-v versions. table 23.6 gives the allowable current output values of the 3-v version. bus drive characteristics common to 5 v, 4 v and 3 v versions are listed in table 23.7. table 23.2 dc characteristics (5-v version) conditions: v cc = 5.0 v 10%, av cc = 5.0 v 10% *1 , v ss = av ss = 0 v, ta = ?0?c to +75?c (regular specifications), ta = ?0?c to +85?c (wide-range specifications) item symbol min typ max unit test conditions schmitt p6 7 to p6 0 * 4 , (1) v t 1.0 v trigger input irq 2 to irq 0 * 5 , v t + v cc 0.7 voltage irq 7 to irq 3 v t + ?v t 0.4 input high voltage res , stby , md 1 , md 0 , extal, nmi (2) v ih v cc ?0.7 v cc + 0.3 v scl, sda v cc 0.7 v cc + 0.3 p7 7 to p7 0 2.0 av cc + 0.3 all input pins other than (1) and (2) above 2.0 v cc + 0.3 input low voltage res , stby , md 1 , md 0 (3) v il ?.3 0.5 v scl, sda ?.3 1.0 all input pins other than (1) and (3) above ?.3 0.8 output high all output pins * 6 v oh v cc ?0.5 v i oh = ?00 a voltage 3.5 i oh = ?.0ma 551 item symbol min typ max unit test conditions output low all output pins * 6 v ol 0.4 v i ol = 1.6 ma voltage p1 7 to p1 0 , p2 7 to p2 0 1.0 i ol = 10.0 ma input res , stby | i in | 10.0 a vin = 0.5 v to leakage nmi , md 1 , md 0 1.0 v cc ?0.5 v current p7 7 to p7 0 1.0 vin = 0.5 v to av cc ?0.5 v leakage current in three-state (off state) ports 1 to 6, 8, 9 | i tsi | 1.0 a vin = 0.5 v to v cc ?0.5 v input pull-up ports 1 to 3 i p 30 250 a vin = 0 v mos current ports 6 60 500 input capacitance stby (dual-power- supply f-ztat version) (4) c in 120 pf vin = 0 v, f = 1 mhz, ta = 25 c res , stby (except dual- power-supply f-ztat version) 60 nmi , md 1 50 f = 1 mhz, p9 7 , p8 6 20 ta = 25 c all input pins other than (4) 15 current normal operation i cc 27 45 ma f = 12 mhz dissipation * 2 36 60 f = 16 mhz sleep mode 18 30 f = 12 mhz 24 40 f = 16 mhz standby modes * 3 0.01 5.0 a ta 50 c 20.0 50 c < ta 552 item symbol min typ max unit test conditions analog supply during a/d conversion ai cc 2.0 5.0 ma current during a/d and d/a conversion 2.0 5.0 a/d and d/a conversion idle 0.01 5.0 aav cc = 2.0 v to 5.5 v analog supply voltage * 1 av cc 4.5 5.5 v during operation 2.0 5.5 while idle or when not in use ram standby voltage v ram 2.0 v notes: * 1 even when the a/d and d/a converters are not used, connect av cc to power supply v cc and keep the applied voltage between 2.0 v and 5.5 v. * 2 current dissipation values assume that v ih min = v cc ?0.5 v, v il max = 0.5 v, all output pins are in the no-load state, and all input pull-up transistors are off. * 3 for these values it is assumed that v ram v cc < 4.5 v and v ih min = v cc 0.9, v il max = 0.3 v. * 4p6 7 to p6 0 include supporting module inputs multiplexed with them. * 5 irq 2 includes adtrg multiplexed with it. * 6 applies when iice = 0. the output low level is determined separately when the bus drive function is selected. 553 table 23.3 dc characteristics (4-v version) conditions: v cc = 4.0 v to 5.5 v, av cc = 4.0 v to 5.5 v *1 , v ss = av ss = 0 v, ta = ?0?c to +75?c (regular specifications), ta = ?0?c to +85?c (wide-range specifications) item symbol min typ max unit test conditions schmitt p6 7 to p6 0 * 4 , (1) v t 1.0 v v cc = 4.5 v to trigger input irq 2 to irq 0 * 5 , v t + v cc 0.7 5.5 v voltage irq 7 to irq 3 v t + ?v t 0.4 v t 0.8 v cc = 4.0 v to v t + v cc 0.7 4.5 v v t + ?v t 0.3 input high voltage res , stby , md 1 , md 0 , extal, nmi (2) v ih v cc ?0.7 v cc + 0.3 v scl, sda v cc 0.7 v cc + 0.3 p7 7 to p7 0 2.0 av cc + 0.3 all input pins other than (1) and (2) above 2.0 v cc + 0.3 input low voltage res , stby , md 1 , md 0 (3) v il ?.3 0.5 v scl, sda ?.3 1.0 v cc = 4.5 v to 5.5 v ?.3 0.8 v cc = 4.0 v to 4.5 v all input pins other than (1) and (3) ?.3 0.8 v cc = 4.5 v to 5.5 v above ?.3 0.6 v cc = 4.0 v to 4.5 v output high all output pins * 6 v oh v cc ?0.5 v i oh = ?00 a voltage 3.5 i oh = ?.0 ma, v cc = 4.5 v to 5.5 v 2.8 i oh = ?.0 ma, v cc = 4.0 v to 4.5 v 554 item symbol min typ max unit test conditions output low all output pins * 6 v ol 0.4 v i ol = 1.6 ma voltage p1 7 to p1 0 , p2 7 to p2 0 1.0 i ol = 10.0 ma input res , stby | i in | 10.0 a vin = 0.5 v to leakage nmi , md 1 , md 0 1.0 v cc ?0.5 v current p7 7 to p7 0 1.0 vin = 0.5 v to av cc ?0.5 v leakage current in three-state (off state) ports 1 to 6, 8, 9 | i tsi | 1.0 a vin = 0.5 v to v cc ?0.5 v input pull-up ports 1 to 3 i p 30 250 a vin = 0 v, mos current ports 6 60 500 v cc = 4.5 v to 5.5 v ports 1 to 3 20 200 vin = 0 v, ports 6 40 400 v cc = 4.0 v to 4.5 v input capacitance stby (dual-power- supply f-ztat version) (4) c in 120 pf vin = 0 v, f = 1 mhz, ta = 25 c res , stby (except dual- power-supply f-ztat version) 60 nmi , md 1 50 f = 1 mhz, p9 7 , p8 6 20 ta = 25 c all input pins other than (4) above 15 555 item symbol min typ max unit test conditions current normal operation i cc 27 45 ma f = 12 mhz dissipation * 2 36 60 f = 16 mhz, v cc = 4.5 v to 5.5 v sleep mode 18 30 f = 12 mhz 24 40 f = 16 mhz, v cc = 4.5 v to 5.5 v standby modes * 3 0.01 5.0 a ta 50 c 20.0 50 c < ta analog supply during a/d conversion ai cc 2.0 5.0 ma current during a/d and d/a conversion 2.0 5.0 a/d and d/a conversion idle 0.01 5.0 aav cc = 2.0 v to 5.5 v analog supply voltage * 1 av cc 4.0 5.5 v during operation 2.0 5.5 while idle or when not in use ram standby voltage v ram 2.0 v notes: * 1 even when the a/d and d/a converters are not used, connect av cc to power supply v cc and keep the applied voltage between 2.0 v and 5.5 v. * 2 current dissipation values assume that v ih min = v cc ?0.5 v, v il max = 0.5 v, all output pins are in the no-load state, and all input pull-up transistors are off. * 3 for these values it is assumed that v ram v cc < 4.0 v and v ih min = v cc 0.9, v il max = 0.3 v. * 4p6 7 to p6 0 include supporting module inputs multiplexed with them. * 5 irq 2 includes adtrg multiplexed with it. * 6 applies when iice = 0. the output low level is determined separately when the bus drive function is selected. 556 table 23.4 dc characteristics (3-v version) conditions: v cc = 2.7 v to 5.5 v *7 , av cc = 2.7 v to 5.5 v *1, *7 , v ss = av ss = 0 v, ta = ?0?c to +75?c item symbol min typ max unit test conditions schmitt p6 7 to p6 0 * 4 , (1) v t v cc 0.15 v trigger input irq 2 to irq 0 * 5 , v t + v cc 0.7 voltage irq 7 to irq 3 v t + ?v t 0.2 input high voltage res , stby , md 1 , md 0 , extal, nmi (2) v ih v cc 0.9 v cc + 0.3 v scl, sda v cc 0.7 v cc + 0.3 p7 7 to p7 0 av cc 0.7 av cc + 0.3 all input pins other than (1) and (2) above v cc 0.7 v cc + 0.3 input low voltage * 4 res , stby , md 1 , md 0 (3) v il ?.3 v cc 0.1 v scl, sda ?.3 v cc 0.15 all input pins other than (1) and (3) above ?.3 v cc 0.15 output high all output pins * 6 v oh v cc ?0.5 v i oh = ?00 a voltage v cc ?1.0 i oh = ? ma output low all output pins * 6 v ol 0.4 v i ol = 0.8 ma voltage p1 7 to p1 0 , p2 7 to p2 0 0.4 i ol = 1.6 ma input res , stby | i in | 10.0 a vin = 0.5 v to leakage nmi , md 1 , md 0 1.0 v cc ?0.5 v current p7 7 to p7 0 1.0 vin = 0.5 v to av cc ?0.5 v leakage current in three-state (off state) ports 1 to 6, 8, 9 | i tsi | 1.0 a vin = 0.5 v to v cc ?0.5 v 557 item symbol min typ max unit test conditions input pull-up ports 1 to 3 i p 3 120 a vin = 0 v, mos current ports 6 30 250 v cc = 2.7 v to 3.6 v input capacitance stby (dual-power- supply f-ztat version) (4) c in 120 pf vin = 0 v, f = 1mhz, ta = 25 c res , stby (except dual- power-supply f-ztat version) 60 nmi , md 1 50 f = 1 mhz, p9 7 , p8 6 20 ta = 25 c all input pins other than (4) above 15 current dissipation * 2 normal operation i cc 7 ma f = 6 mhz, 2.7 v to 3.6 v 12 22 f = 10 mhz, v cc = 2.7 v to 3.6 v 25 f = 10 mhz, v cc = 4.0 v to 5.5 v sleep mode 5 f = 6 mhz, 2.7 v to 3.6 v 9 16 f = 10 mhz, v cc = 2.7 v to 3.6 v 18 f = 10 mhz, v cc = 4.0 v to 5.5 v standby modes * 3 0.01 5.0 a ta 50 c 20.0 50 c < ta 558 item symbol min typ max unit test conditions analog supply during a/d conversion ai cc 2.0 5.0 ma current during a/d and d/a conversion 2.0 5.0 a/d and d/a conversion idle 0.01 5.0 aav cc = 2.0 v to 5.5 v analog supply voltage * 1 av cc 2.7 5.5 v during operation 2.0 5.5 while idle or when not in use ram standby voltage v ram 2.0 v notes: * 1 even when the a/d and d/a converters are not used, connect av cc to power supply v cc and keep the applied voltage between 2.0 v and 5.5 v. * 2 current dissipation values assume that v ih min = v cc ?0.5 v, v il max = 0.5 v, all output pins are in the no-load state, and all input pull-up transistors are off. * 3 for these values it is assumed that v ram v cc < 2.7 v and v ih min = v cc 0.9, v il max = 0.3 v. * 4p6 7 to p6 0 include supporting module inputs multiplexed with them. * 5 irq 2 includes adtrg multiplexed with it. * 6 applies when iice = 0. the output low level is determined separately when the bus drive function is selected. * 7 in the f-ztat lh version, v cc = 3.0 v to 5.5 v, av cc = 3.0 v to 5.5 v. 559 table 23.5 allowable output current values (5-v and 4-v versions) conditions: v cc = 4.0 v to 5.5 v, av cc = 4.0 v to 5.5 v, v ss = av ss = 0 v, ta = ?0?c to +75?c (regular specifications), ta = ?0?c to +85?c (wide-range specifications) item symbol min typ max unit allowable output low current (per pin) scl, sda (bus drive selection) i ol 20 ma ports 1 and 2 10 other output pins 2 allowable output low ports 1 and 2, total i ol 80 ma current (total) total of all output 120 allowable output high current (per pin) all output pins ? oh 2 ma allowable output high current (total) total of all output ? oh 40 ma table 23.6 allowable output current values (3-v version) conditions: v cc = 2.7 to 5.5 v*, av cc = 2.7 v to 5.5 v*, v ss = av ss = 0 v, ta = ?0?c to +75?c item symbol min typ max unit allowable output low current (per pin) scl, sda (bus drive selection) i ol 10 ma ports 1 and 2 2 other output pins 1 allowable output low ports 1 and 2, total i ol 40 ma current (total) total of all output 60 allowable output high current (per pin) all output pins ? oh 2 ma allowable output high current (total) total of all output ? oh 30 ma note: * in the f-ztat lh version, v cc = 3.0 v to 5.5 v, av cc = 3.0 v to 5.5 v. 560 h8/3337 series or h8/3397 series port 2 k ? darlington transistor figure 23.1 example of circuit for driving a darlington transistor (5-v version) h8/3337 series or h8/3397 series ports 1 or 2 led 600 ? v cc figure 23.2 example of circuit for driving an led (5-v version) table 23.7 bus drive characteristics conditions: v ss = 0 v, ta = ?0 to 75?c item symbol min typ max unit test condition output low voltage scl, sda (bus drive selection) v ol 0.5 v v cc = 5 v 10% i ol = 16 ma 0.5 v cc = 2.7 v to 5.5 v * i ol = 8 ma 0.4 v cc = 2.7 v to 5.5 v * i ol = 3 ma note: * in the f-ztat lh version, v cc = 3.0 v to 5.5 v. 561 23.2.2 ac characteristics the ac characteristics are listed in following tables. bus timing parameters are given in table 23.8, control signal timing parameters in table 23.9, timing parameters of the on-chip supporting modules in table 23.10, i 2 c bus timing parameters in table 23.11, and external clock output delay timing parameters in table 23.12. 562 table 23.8 bus timing condition a: v cc = 5.0 v 10%, v ss = 0 v, ?= 2.0 mhz to maximum operating frequency, ta = ?0?c to +75?c (regular specifications), ta = ?0?c to +85?c (wide-range specifications) condition b: v cc = 4.0 v to 5.5 v, v ss = 0 v, ?= 2.0 mhz to maximum operating frequency, ta = ?0?c to +75?c (regular specifications), ta = ?0?c to +85?c (wide-range specifications) condition c: v cc = 2.7 v to 5.5 v *3 , v ss = 0 v, ?= 2.0 mhz to maximum operating frequency, ta = ?0?c to +75?c condition c condition b condition a 10 mhz 12 mhz 16 mhz test item symbol min max min max min max unit conditions clock cycle time t cyc 100 500 83.3 500 62.5 500 ns fig. 23.7 clock pulse width low t cl 30 30 20 ns clock pulse width high t ch 30 30 20 ns clock rise time t cr 20 10 10 ns clock fall time t cf 20 10 10 ns address delay time t ad 50 35 30 ns address hold time t ah 20 15 10 ns address strobe delay time t asd 50 35 30 ns write strobe delay time t wsd 50 35 30 ns strobe delay time t sd 50 35 30 ns write strobe pulse width * 1 t wsw 110 90 60 ns address setup time 1 * 1 t as1 15 10 10 ns address setup time 2 * 1 t as2 65 50 40 ns read data setup time t rds 35 20 20 ns read data hold time * 1 t rdh 0 0 0 ns read data access time * 1 t acc 170 160 110 ns write data delay time t wdd 80/75 * 2 65/60 * 2 60 ns write data setup time t wds 0/5 * 2 0/5 * 2 0/5 * 2 ns write data hold time t wdh 20 20 20 ns wait setup time t wts 40 35 30 ns fig. 23.8 wait hold time t wth 10 10 10 ns notes: * 1 values at maximum operating frequency * 2 h8/3337yf-ztat version/other products * 3 in the f-ztat lh version, v cc = 3.0 v to 5.5 v 563 table 23.9 control signal timing condition a: v cc = 5.0 v 10%, v ss = 0 v, ?= 2.0 mhz to maximum operating frequency, ta = ?0?c to +75?c (regular specifications), ta = ?0?c to +85?c (wide-range specifications) condition b: v cc = 4.0 v to 5.5 v, v ss = 0 v, ?= 2.0 mhz to maximum operating frequency, ta = ?0?c to +75?c (regular specifications), ta = ?0?c to +85?c (wide-range specifications) condition c: v cc = 2.7 v to 5.5 v*, v ss = 0 v, ?= 2.0 mhz to maximum operating frequency, ta = ?0?c to +75?c condition c condition b condition a 10 mhz 12 mhz 16 mhz test item symbol min max min max min max unit conditions res setup time t ress 300 200 200 ns fig. 23.9 res pulse width t resw 10 10 10 t cyc nmi setup time ( nmi , irq 0 to irq 7 ) t nmis 300 150 150 ns fig. 23.10 nmi hold time ( nmi , irq 0 to irq 7 ) t nmih 10 10 10 ns interrupt pulse width for recovery from soft- ware standby mode ( nmi , irq 0 to irq 2 , irq 6 ) t nmiw 300 200 200 ns crystal oscillator settling time (reset) t osc1 20 20 20 ms fig. 23.11 crystal oscillator settling time (software standby) t osc2 8 8 8 ms fig. 23.12 note: * in the f-ztat lh version, v cc = 3.0 v to 5.5 v. 564 measurement conditions for ac characteristics c r h 5 v r l lsi output pin c = input/output timing measurement levels low: 0.8 v high: 2.0 v r l = r h = 90 pf: ports 1 4, 6, 9 30 pf: ports 5, 8 2.4 k ? 12 k ? figure 23.3 output load circuit 565 table 23.10 timing conditions of on-chip supporting modules condition a: v cc = 5.0 v 10%, v ss = 0 v, ?= 2.0 mhz to maximum operating frequency, ta = ?0?c to +75?c (regular specifications), ta = ?0?c to +85?c (wide-range specifications) condition b: v cc = 4.0 v to 5.5 v, v ss = 0 v, ?= 2.0 mhz to maximum operating frequency, ta = ?0?c to +75?c (regular specifications), ta = ?0?c to +85?c (wide-range specifications) condition c: v cc = 2.7 v to 5.5 v*, v ss = 0 v, ?= 2.0 mhz to maximum operating frequency, ta = ?0?c to +75?c condition c condition b condition a 10 mhz 12 mhz 16 mhz test item symbol min max min max min max unit conditions frt timer output delay time t ftod 150 100 100 ns fig. 23.13 timer input setup time t ftis 80 50 50 ns timer clock input setup time t ftcs 80 50 50 ns fig. 23.14 timer clock pulse width t ftcwh t ftcwl 1.5 1.5 1.5 t cyc tmr timer output delay time t tmod 150 100 100 ns fig. 23.15 timer reset input setup time t tmrs 80 50 50 ns fig. 23.17 timer clock input setup time t tmcs 80 50 50 ns fig. 23.16 timer clock pulse width (single edge) t tmcwh 1.5 1.5 1.5 t cyc timer clock pulse width (both edges) t tmcwl 2.5 2.5 2.5 t cyc pwm timer output delay time t pwod 150 100 100 ns fig. 23.18 sci input clock (async) t scyc 4 4 4 t cyc fig. 23.19 cycle (sync) 6 6 6 t cyc transmit data delay time (sync) t txd 200 100 100 ns receive data setup time (sync) t rxs 150 100 100 ns receive data hold time (sync) t rxh 150 100 100 ns input clock pulse width t sckw 0.4 0.6 0.4 0.6 0.4 0.6 t scyc fig. 23.20 566 condition c condition b condition a 10 mhz 12 mhz 16 mhz test item symbol min max min max min max unit conditions ports output data delay time t pwd 150 100 100 ns fig. 23.21 input data setup time t prs 80 50 50 ns input data hold time t prh 80 50 50 ns hif cs /ha 0 setup time t har 10 10 10 ns fig. 23.22 read cs /ha 0 hold time t hra 10 10 10 ns cycle ior pulse width t hrpw 220 120 120 ns hdb delay time t hrd 200 100 100 ns hdb hold time t hrf 040 025 025ns hirq delay time t hirq 200 120 120 ns hif cs /ha 0 setup time t haw 10 10 10 ns fig. 23.23 write cs /ha 0 hold time t hwa 10 10 10 ns cycle iow pulse width t hwpw 100 60 60 ns high-speed gate a 20 not uesd t hdw 50 30 30 ns high-speed gate a 20 uesd 85 55 45 hdb hold time t hwd 25 15 15 ns ga 20 delay time t hga 180 90 90 ns note: * in the f-ztat lh version, v cc = 3.0 v to 5.5 v. 567 table 23.11 i 2 c bus timing conditions: v cc = 2.7 v to 5.5 v*, v ss = 0 v, ta = ?0?c to +75?c, ? 5 mhz rating item symbol min typ max unit test condition note scl clock cycle time t scl 12t cyc ns figure 23.24 scl clock high pulse width t sclh 3t cyc ns scl clock low pulse width t scll 5t cyc ns scl, sda rise time t sr 1000 ns normal mode 100 kbit/s (max) 20 + 0.1c b 300 high-speed mode 400 kbit/s (max) scl, sda fall time t sf 300 ns normal mode 100 kbit/s (max) 20 + 0.1c b 300 high-speed mode 400 kbit/s (max) sda bus free time t buf 5t cyc ns scl start condition hold time t stah 3t cyc ns scl resend start condition hold time t stas 3t cyc ns sda stop condition setup time t stos 3t cyc ns sda data setup time t sdas 0.5t cyc ns sda data hold time t sdah 0 ns sda load capacitance c b 400 pf note: * in the f-ztat lh version, v cc = 3.0 v to 5.5 v. 568 table 23.12 external clock output delay timing conditions: v cc = 2.7 v to 5.5 v *2 , av cc = 2.7 v to 5.5 v *2 , v ss = av ss = 0v, ta = ?0?c to +85?c item symbol min max unit notes external clock output delay time t dext * 1 500 s figure 23.25 notes: * 1t dext includes to res pulse width t resw (10 tcyc). * 2 in the f-ztat lh version, v cc = 3.0 v to 5.5 v, av cc = 3.0 v to 5.5 v. 569 23.2.3 a/d converter characteristics table 23.13 lists the characteristics of the on-chip a/d converter. table 23.13 a/d converter characteristics condition a: v cc = 5.0 v 10%, av cc = 5.0 v 10%, v ss = av ss = 0 v, ?= 2.0 mhz to maximum operating frequency, ta = ?0?c to +75?c (regular specifications), ta = ?0?c to +85?c (wide-range specifications) condition b: v cc = 4.0 v to 5.5 v, av cc = 4.0 v to 5.5 v, v ss = av ss = 0 v, ?= 2.0 mhz to maximum operating frequency, ta = ?0?c to +75?c (regular specifications), ta = ?0?c to +85?c (wide-range specifications) condition c: v cc = 2.7 v to 5.5 v *2 , av cc = 2.7 v to 5.5 v *2 , v ss = av ss = 0 v, ?= 2.0 mhz to maximum operating frequency, ta = ?0?c to +75?c condition c condition b condition a 10 mhz 12 mhz 16 mhz item min typ max min typ max min typ max unit resolution 10 10 10 10 10 10 10 10 10 bits conversion (single mode) * 1 13.4 11.2 8.4 s analog input capacitance 20 20 20 pf allowable signal source impedance 5 10 10 k ? nonlinearity error 6.0 3.0 3.0 lsb offset error 4.0 3.5 3.5 lsb full-scale error 4.0 3.5 3.5 lsb quantizing error 0.5 0.5 0.5 lsb absolute accuracy 8.0 4.0 4.0 lsb notes: * 1 values at maximum operating frequency * 2 in the f-ztat lh version, v cc = 3.0 v to 5.5 v, av cc = 3.0 v to 5.5 v. 570 23.2.4 d/a converter characteristics (h8/3337 series only) table 23.14 lists the characteristics of the on-chip d/a converter. table 23.14 d/a converter characteristics condition a: v cc = 5.0 v 10%, av cc = 5.0 v 10%, v ss = av ss = 0 v, ?= 2.0 mhz to maximum operating frequency, ta = ?0?c to +75?c (regular specifications), ta = ?0?c to +85?c (wide-range specifications) condition b: v cc = 4.0 v to 5.5 v, av cc = 4.0 v to 5.5 v, v ss = av ss = 0 v, ?= 2.0 mhz to maximum operating frequency, ta = ?0?c to +75?c (regular specifications), ta = ?0?c to +85?c (wide-range specifications) condition c: v cc = 2.7 v to 5.5 v*, av cc = 2.7 v to 5.5 v*, v ss = av ss = 0 v, ?= 2.0 mhz to maximum operating frequency, ta = ?0?c to +75?c condition c condition b condition a 10 mhz 12 mhz 16 mhz test item min typ max min typ max min typ max unit conditions resolution 8 8 8 8 8 8 8 8 8 bits conversion time (settling time) 10.0 10.0 10.0 s 30 pf load capacitance absolute accuracy 2.0 3.0 1.0 1.5 1.0 1.5 lsb 2 m ? load resistance 2.0 1.0 1.0 lsb 4 m ? load resistance note: * in the f-ztat lh version, v cc = 3.0 v to 5.5 v, av cc = 3.0 v to 5.5 v. 571 23.2.5 flash memory characteristics (h8/3337sf only) table 23.15 shows the flash memory characteristics. table 23.15 flash memory characteristics conditions: v cc = 5.0 v 10%, av cc = 5.0 v 10%, v ss = av ss = 0 v, t a = 0 to +75 c item symbol min typ max unit test condition programming time * 1 * 2 * 4 tp 10 200 ms/ 32 bytes erase time * 1 * 3 * 5 te 100 1200 ms/ block reprogramming count n wec 100 times programming wait time after swe-bit setting * 1 x10 s wait time after psu-bit setting * 1 y50 s wait time after p-bit setting * 1 * 4 z 150 500 s wait time after p-bit clear * 1 10 s wait time after psu-bit clear * 1 10 s wait time after pv-bit setting * 1 4 s wait time after dummy write * 1 2 s wait time after pv-bit clear * 1 4 s maximum programming count * 1 * 4 * 5 n 403 times 572 item symbol min typ max unit test condition erase wait time after swe-bit setting * 1 x10 s wait time after esu-bit setting * 1 y 200 s wait time after e-bit setting * 1 * 6 z5 10 ms wait time after e-bit clear * 1 10 s wait time after esu-bit clear * 1 10 s wait time after ev-bit setting * 1 20 s wait time after dummy write * 1 2 s wait time after ev-bit clear * 1 5 s maximum erase count * 1 * 6 * 7 n 120 times te = 10 ms notes: * 1 set the times according to the program/erase algorithms. * 2 programming time per 32 bytes (shows the total period for which the p-bit in flmcr1 is set. it does not include the programming verification time.) * 3 block erase time (shows the total period for which the e-bit in flmcr1 is set. it does not include the erase verification time.) * 4 maximum programming time (tp (max) = wait time after p-bit setting (z) maximum programming count (n)) set the wait time after p-bit setting (z) to the minimum value of 150 s when the write counter in the 32-byte write algorithm is between 1 and 4. * 5 number of times when the wait time after p-bit setting (z) = 150 us or 500 s. the number of writes should be set according to the actual set value of (z) to allow programming within the maximum programming time (tp). * 6 maximum erase time (te (max) = wait time after e-bit setting (z) maximum erase count (n)) * 7 number of times when the wait time after e-bit setting (z) = 10 ms. the number of erases should be set according to the actual set value of (z) to allow erasing within the maximum erase time (te). 573 23.3 absolute maximum ratings (h8/3337sf low-voltage version) table 23.16 lists the absolute maximum ratings. table 23.16 absolute maximum ratings item symbol rating unit supply voltage v cc 0.3 to +7.0 v input voltage pins other than port 7 v in 0.3 to v cc + 0.3 v port 7 v in 0.3 to av cc + 0.3 v analog supply voltage av cc 0.3 to +7.0 v analog input voltage v an 0.3 to av cc + 0.3 v operating temperature t opr regular specifications: 20 to +75 ? c wide-range specifications: 40 to +85 ? c storage temperature t stg 55 to +125 ? c note: exceeding the absolute maximum ratings shown in table 23.16 can permanently destroy the chip. * 574 23.4 electrical characteristics (h8/3337sf low-voltage version) 23.4.1 dc characteristics table 23.17 lists the dc characteristics. table 23.18 gives the allowable current output values. bus drive characteristics common listed in table 23.19. table 23.17 dc characteristics (3-v version) conditions: v cc = 3.0 v to 5.5 v, av cc = 3.0 v to 5.5 v *1 , v ss = av ss = 0 v, ta = ?0?c to +75?c (regular specifications), ta = ?0 c to +85 c (wide-range specifications) item symbol min typ max unit test conditions schmitt p6 7 to p6 0 * 4 , (1) v t v cc 0.15 v trigger input irq 2 to irq 0 * 5 , v t + v cc 0.7 voltage irq 7 to irq 3 v t + v t 0.2 input high voltage res , stby , md 1 , md 0 , extal, nmi (2) v ih v cc 0.9 v cc + 0.3 v scl, sda v cc 0.7 v cc + 0.3 p7 7 to p7 0 v cc 0.7 av cc + 0.3 all input pins other than (1) and (2) above v cc 0.7 v cc + 0.3 input low voltage * 4 res , stby , md 1 , md 0 (3) v il 0.3 v cc 0.1 v scl, sda 0.3 v cc 0.15 all input pins other than (1) and (3) above 0.3 v cc 0.15 output high all output pins * 6 v oh v cc 0.5 vi oh = 200 a voltage v cc 1.0 i oh = 1 ma output low all output pins * 6 v ol 0.4 v i ol = 0.8 ma voltage p1 7 to p1 0 , p2 7 to p2 0 0.4 i ol = 1.6 ma input res , stby | i in | 10.0 a vin = 0.5 v to leakage nmi , md 1 , md 0 1.0 v cc 0.5 v current p7 7 to p7 0 1.0 vin = 0.5 v to av cc 0.5 v 575 item symbol min typ max unit test conditions leakage current in three-state (off state) ports 1 to 6, 8, 9 | i tsi | 1.0 a vin = 0.5 v to v cc 0.5 v input pull-up ports 1 to 3 i p 3 120 a vin = 0 v, mos current ports 6 30 250 v cc = 3.0 v to 3.6 v input capacitance res , stby (4) c in 60 pf vin = 0 v, f = 1mhz, ta = 25 c nmi , md 1 50 f = 1 mhz, p9 7 , p8 6 20 ta = 25 c all input pins other than (4) above 15 current dissipation * 2 normal operation i cc 7 ma f = 6 mhz, 3.0 v to 3.6 v 12 22 f = 10 mhz, v cc = 3.0 v to 3.6 v 25 f = 10 mhz, v cc = 4.0 v to 5.5 v sleep mode 5 f = 6 mhz, 3.0 v to 3.6 v 9 16 f = 10 mhz, v cc = 3.0 v to 3.6 v 18 f = 10 mhz, v cc = 4.0 v to 5.5 v standby modes * 3 0.01 5.0 a ta 50 c 20.0 50 c < ta 576 item symbol min typ max unit test conditions analog supply during a/d conversion ai cc 2.0 5.0 ma current during a/d and d/a conversion 2.0 5.0 a/d and d/a conversion idle 0.01 5.0 aav cc = 2.0 v to 5.5 v analog supply voltage * 1 av cc 3.0 5.5 v during operation 2.0 5.5 while idle or when not in use ram standby voltage v ram 2.0 v notes: * 1 even when the a/d and d/a converters are not used, connect av cc to power supply v cc and keep the applied voltage between 2.0 v and 5.5 v. * 2 current dissipation values assume that v ih min = v cc 0.5 v, v il max = 0.5 v, all output pins are in the no-load state, and all input pull-up transistors are off. * 3 for these values it is assumed that v ram v cc < 3.0 v and v ih min = v cc 0.9, v il max = 0.3 v. * 4p6 7 to p6 0 include supporting module inputs multiplexed with them. * 5 irq 2 includes adtrg multiplexed with it. * 6 applies when iice = 0. the output low level is determined separately when the bus drive function is selected. 577 table 23.18 allowable output current values (3-v version) conditions: v cc = 3.0 to 5.5 v, av cc = 3.0 v to 5.5 v, v ss = av ss = 0 v, ta = ?0?c to +75?c (regular specifications), ta = ?0 c to +85 c (wide-range specifications) item symbol min typ max unit allowable output low current (per pin) scl, sda (bus drive selection) i ol 10 ma ports 1 and 2 2 other output pins 1 allowable output low ports 1 and 2, total i ol 40 ma current (total) total of all output 60 allowable output high current (per pin) all output pins i oh 2ma allowable output high current (total) total of all output i oh 30 ma h8/3337 series or h8/3397 series port 2 k ? darlington transistor figure 23.4 example of circuit for driving a darlington transistor (5-v version) 578 h8/3337 series or h8/3397 series ports 1 or 2 led 600 ? v cc figure 23.5 example of circuit for driving an led (5-v version) table 23.19 bus drive characteristics conditions: v cc = 3.0 v to 5.5 v, v ss = 0 v, ta = ?0?c to 75?c item symbol min typ max unit test condition output low voltage scl, sda (bus drive selection) v ol 0.5 v v cc = 5 v 10% i ol = 16 ma 0.5 v cc = 3.0 v to 5.5 v i ol = 8 ma 0.4 v cc = 3.0 v to 5.5 v i ol = 3 ma 23.4.2 ac characteristics the ac characteristics are listed in following tables. bus timing parameters are given in table 23.20, control signal timing parameters in table 23.21, timing parameters of the on-chip supporting modules in table 23.22, i 2 c bus timing parameters in table 23.23, and external clock output delay timing parameters in table 23.24. 579 table 23.20 bus timing conditions: v cc = 3.0 v to 5.5 v, v ss = 0 v, ?= 2.0 mhz to maximum operating frequency, ta = ?0?c to +75?c (regular specifications), ta = ?0 c to +85 c (wide-range specifications) condition 10 mhz item symbol min max unit test conditions clock cycle time t cyc 100 500 ns fig. 23.7 clock pulse width low t cl 30 ns clock pulse width high t ch 30 ns clock rise time t cr 20 ns clock fall time t cf 20 ns address delay time t ad 50 ns address hold time t ah 20 ns address strobe delay time t asd 50 ns write strobe delay time t wsd 50 ns strobe delay time t sd 50 ns write strobe pulse width * t wsw 110 ns address setup time 1 * t as1 15 ns address setup time 2 * t as2 65 ns read data setup time t rds 35 ns read data hold time * t rdh 0 ns read data access time * t acc 170 ns write data delay time t wdd 75 ns write data setup time t wds 5 ns write data hold time t wdh 20 ns wait setup time t wts 40 ns fig. 23.8 wait hold time t wth 10 ns note: * values at maximum operating frequency 580 table 23.21 control signal timing conditions: v cc = 3.0 v to 5.5 v, v ss = 0 v, ?= 2.0 mhz to maximum operating frequency, ta = ?0?c to +75?c (regular specifications), ta = ?0 c to +85 c (wide-range specifications) condition 10 mhz item symbol min max unit test conditions res setup time t ress 300 ns fig. 23.9 res pulse width t resw 10 t cyc nmi setup time ( nmi , irq 0 to irq 7 )t nmis 300 ns fig. 23.10 nmi hold time ( nmi , irq 0 to irq 7 )t nmih 10 ns interrupt pulse width for recovery from software standby mode ( nmi , irq 0 to irq 2 , irq 6 ) t nmiw 300 ns crystal oscillator settling time (reset) t osc1 20 ms fig. 23.11 crystal oscillator settling time (software standby) t osc2 8 ms fig. 23.12 measurement conditions for ac characteristics c r h 5 v r l lsi output pin c = input/output timing measurement levels low: 0.8 v high: 2.0 v r l = r h = 90 pf: ports 1 4, 6, 9 30 pf: ports 5, 8 2.4 k ? 12 k ? figure 23.6 output load circuit 581 table 23.22 timing conditions of on-chip supporting modules conditions: v cc = 3.0 v to 5.5 v, v ss = 0 v, ?= 2.0 mhz to maximum operating frequency, ta = ?0?c to +75?c (regular specifications), ta = ?0 c to +85 c (wide-range specifications) condition 10 mhz item symbol min max unit test conditions frt timer output delay time t ftod 150 ns fig. 23.13 timer input setup time t ftis 80 ns timer clock input setup time t ftcs 80 ns fig. 23.14 timer clock pulse width t ftcwh 1.5 t cyc t ftcwl tmr timer output delay time t tmod 150 ns fig. 23.15 timer reset input setup time t tmrs 80 ns fig. 23.17 timer clock input setup time t tmcs 80 ns fig. 23.16 timer clock pulse width (single edge) t tmcwh 1.5 t cyc timer clock pulse width (both edges) t tmcwl 2.5 t cyc pwm timer output delay time t pwod 150 ns fig. 23.18 sci input clock cycle (async) t scyc 4 t cyc fig. 23.19 (sync) 6 t cyc transmit data delay time (sync) t txd 200 ns receive data setup time (sync) t rxs 150 ns receive data hold time (sync) t rxh 150 ns input clock pulse width t sckw 0.4 0.6 t scyc fig. 23.20 ports output data delay time t pwd 150 ns fig. 23.21 input data setup time t prs 80 ns input data hold time t prh 80 ns hif read cs /ha 0 setup time t har 10 ns fig. 23.22 cycle cs /ha 0 hold time t hra 10 ns ior pulse width t hrpw 220 ns hdb delay time t hrd 200 ns hdb hold time t hrf 040ns hirq delay time t hirq 200 ns hif write cs /ha 0 setup time t haw 10 ns fig. 23.23 cycle cs /ha 0 hold time t hwa 10 ns iow pulse width t hwpw 100 ns high-speed gate a 20 not uesd t hdw 50 ns high-speed gate a 20 uesd 85 hdb hold time t hwd 25 ns ga 20 delay time t hga 180 ns 582 table 23.23 i 2 c bus timing conditions: v cc = 3.0 v to 5.5 v, v ss = 0 v, ta = ?0?c to +75?c (regular specifications), ta = ?0 c to +85 c (wide-range specifications), ?= 5.0 mhz to maximum operating frequency rating item symbol min typ max unit test condition note scl clock cycle time t scl 12t cyc ns figure 23.24 scl clock high pulse width t sclh 3t cyc ns scl clock low pulse width t scll 5t cyc ns scl, sda rise time t sr 1000 ns normal mode 100 kbit/s (max) 20 + 0.1c b 300 high-speed mode 400 kbit/s (max) scl, sda fall time t sf 300 ns normal mode 100 kbit/s (max) 20 + 0.1c b 300 high-speed mode 400 kbit/s (max) sda bus free time t buf 5t cyc ns scl start condition hold time t stah 3t cyc ns scl resend start condition hold time t stas 3t cyc ns sda stop condition setup time t stos 3t cyc ns sda data setup time t sdas 0.5t cyc ns sda data hold time t sdah 0 ns sda load capacitance c b 400 pf 583 23.4.3 a/d converter characteristics table 23.24 lists the characteristics of the on-chip a/d converter. table 23.24 a/d converter characteristics conditions: v cc = 3.0 v to 5.5 v, av cc = 3.0 v to 5.5 v, v ss = av ss = 0 v, ?= 2.0 mhz to maximum operating frequency, ta = ?0?c to +75?c (regular specifications), ta = ?0 c to +85 c (wide-range specifications) condition 10 mhz item min typ max unit resolution 10 10 10 bits conversion (single mode) * 13.4 s analog input capacitance 20 pf allowable signal source impedance 5k ? nonlinearity error 6.0 lsb offset error 4.0 lsb full-scale error 4.0 lsb quantizing error 0.5 lsb absolute accuracy 8.0 lsb note: * values at maximum operating frequency 584 23.4.4 d/a converter characteristics (h8/3337 series only) table 23.25 lists the characteristics of the on-chip d/a converter. table 23.25 d/a converter characteristics conditions: v cc = 3.0 v to 5.5 v, av cc = 3.0 v to 5.5 v, v ss = av ss = 0 v, ?= 2.0 mhz to maximum operating frequency, ta = ?0?c to +75?c (regular specifications), ta = ?0 c to +85 c (wide-range specifications) condition 10 mhz item min typ max unit test conditions resolution 8 8 8 bits conversion time (settling time) 10.0 s 30 pf load capacitance absolute accuracy 2.0 3.0 lsb 2 m ? load resistance 2.0 lsb 4 m ? load resistance 585 23.4.5 flash memory characteristics table 23.26 shows the flash memory characteristics. table 23.26 flash memory characteristics conditions: v cc = 3.0 v to 3.6 v, av cc = 3.0 v to 5.5 v, v ss = av ss = 0 v, t a = 0 to +75 c item symbol min typ max unit test condition programming time * 1 * 2 * 4 tp 10 200 ms/ 32 bytes erase time * 1 * 3 * 5 te 100 1200 ms/ block reprogramming count n wec 100 times programming wait time after swe-bit setting * 1 x10 s wait time after psu-bit setting * 1 y50 s wait time after p-bit setting * 1 * 4 z 150 500 s wait time after p-bit clear * 1 10 s wait time after psu-bit clear * 1 10 s wait time after pv-bit setting * 1 4 s wait time after dummy write * 1 2 s wait time after pv-bit clear * 1 4 s maximum programming count * 1 * 4 * 5 n 403 times 586 item symbol min typ max unit test condition erase wait time after swe-bit setting * 1 x10 s wait time after esu-bit setting * 1 y 200 s wait time after e-bit setting * 1 * 6 z5 10 ms wait time after e-bit clear * 1 10 s wait time after esu-bit clear * 1 10 s wait time after ev-bit setting * 1 20 s wait time after dummy write * 1 2 s wait time after ev-bit clear * 1 5 s maximum erase count * 1 * 6 * 7 n 120 times te = 10 ms notes: * 1 set the times according to the program/erase algorithms. * 2 programming time per 32 bytes (shows the total period for which the p-bit in flmcr1 is set. it does not include the programming verification time.) * 3 block erase time (shows the total period for which the e-bit in flmcr1 is set. it does not include the erase verification time.) * 4 maximum programming time (tp (max) = wait time after p-bit setting (z) maximum programming count (n)) set the wait time after p-bit setting (z) to the minimum value of 150 s when the write counter in the 32-byte write algorithm is between 1 and 4. * 5 number of times when the wait time after p-bit setting (z) = 150 s or 500 s. the number of writes should be set according to the actual set value of (z) to allow programming within the maximum programming time (tp). * 6 maximum erase time (te (max) = wait time after e-bit setting (z) maximum erase count (n)) * 7 number of times when the wait time after e-bit setting (z) = 10 ms. the number of erases should be set according to the actual set value of (z) to allow erasing within the maximum erase time (te). 587 23.5 mcu operational timing this section provides the following timing charts: 23.5.1 bus timing figures 23.7 and 23.8 23.5.2 control signal timing figures 23.9 to 23.12 23.5.3 16-bit free-running timer timing figures 23.13 and 23.14 23.5.4 8-bit timer timing figures 23.15 to 23.17 23.5.5 pwm timer timing figure 23.18 23.5.6 sci timing figures 23.19 and 23.20 23.5.7 i/o port timing figure 23.21 23.5.8 host interface timing (h8/3337 series only) figures 23.22 and 23.23 23.5.9 i 2 c bus timing (option) (h8/3337 series only) figure 23.24 23.5.10 external clock output timing figure 23.25 23.5.1 bus timing (1) basic bus cycle (without wait states) in expanded modes t 2 t 1 t cyc t 3 t ch t cl t ad t cr t asd t acc t rds t wsd t as2 t wdd t wds t wdh t ah t wsw t rdh t ah t sd a 15 to a 0 wr d 7 to d 0 (read) d 7 to d 0 (write) as , rd t cf t as1 t sd figure 23.7 basic bus cycle (without wait states) in expanded modes 588 (2) basic bus cycle (with 1 wait state) in expanded modes as , rd wr wait d 7 to d 0 (read) a 15 to a 0 d 7 to d 0 (write) t 1 t 2 t w t 3 t wts t wth t wts t wth figure 23.8 basic bus cycle (with 1 wait state) in expanded modes (modes 1 and 2) 23.5.2 control signal timing (1) reset input timing res t ress t ress t resw figure 23.9 reset input timing 589 (2) interrupt input timing irq l nmi irq i t nmis t nmih t nmis nmi irq e t nmiw note: i = 0 to 7; irq e : irq i when edge-sensed; irq l : irq i when level-sensed figure 23.10 interrupt input timing (3) clock settling timing v cc res stby t osc1 t osc1 figure 23.11 clock settling timing 590 (4) clock settling timing for recovery from software standby mode nmi irq i (i = 0, 1, 2, 6) t osc2 figure 23.12 clock settling timing for recovery from software standby mode 23.5.3 16-bit free-running timer timing (1) free-running timer input/output timing compare-match ftia, ftib, ftic, ftid ftoa , ftob free-running timer counter t ftod t ftis figure 23.13 free-running timer input/output timing 591 (2) external clock input timing for free-running timer ftci t ftcs t ftcwl t ftcwh figure 23.14 external clock input timing for free-running timer 23.5.4 8-bit timer timing (1) 8-bit timer output timing timer counter compare-match tmo 0 , tmo 1 t tmod figure 23.15 8-bit timer output timing (2) 8-bit timer clock input timing t tmcs t tmcs t tmcwl t tmcwh tmci 0 , tmci 1 figure 23.16 8-bit timer clock input timing 592 (3) 8-bit timer reset input timing n h'00 timer counter t tmrs tmri 0 , tmri 1 figure 23.17 8-bit timer reset input timing 23.5.5 pulse width modulation timer timing compare-match t pwod timer counter pw 0 , pw 1 figure 23.18 pwm timer output timing 593 23.5.6 serial communication interface timing (1) sci input/output timing t scyc t txd t rxs t rxh serial clock (sck 0 , sck 1 ) transmit data (txd 0 , txd 1 ) receive data (rxd 0 , rxd 1 ) figure 23.19 sci input/output timing (synchronous mode) (2) sci input clock timing t sckw t scyc sck 0 , sck 1 figure 23.20 sci input clock timing 594 23.5.7 i/o port timing note: * except p9 6 and p7 7 to p7 0 t prs t prh t pwd port 1 to port 9 (input) port 1 * to port 9 (output) t 1 t 2 t 3 figure 23.21 i/o port input/output timing 23.5.8 host interface timing (h8/3337 series only) (1) host interface read timing cs /ha 0 ha 0 ior hdb 7 to hdb 0 hirq i (i = 1, 11, 12) note: the risin g ed g e timin g is the same as port 4 output timin g . refer to fi g ure 23.21. t har t hrpw t hra t hrf t hrd t hirq effective data figure 23.22 host interface read timing 595 (2) host interface write timing cs /ha 0 ha 0 iow hdb 7 to hdb 0 ga 20 t haw t hwpw t hwa t hwd t hga t hdw figure 23.23 host interface write timing 23.5.9 i 2 c bus timing (option) (h8/3337 series only) sda v il v ih t buf p * s * t stah t sclh t sr t scll t scl t sf t sdah sr * t sdas t stas t sp t stos note: * s, p, and sr are defined as follows: s: p: sr: start condition stop condition retransmission start condition scl p * figure 23.24 i 2 c interface input/output timing 596 23.5.10 external clock output timing v cc stby v ih extal note: * t dext includes an res pulse width (t resw ) of 10 t cyc . res t dext * (internal or external) figure 23.25 external clock output delay timing 597 appendix a cpu instruction set a.1 instruction set list operation notation rd8/16 general register (destination) (8 or 16 bits) rs8/16 general register (source) (8 or 16 bits) rn8/16 general register (8 or 16 bits) ccr condition code register n n (negative) flag in ccr z z (zero) flag in ccr v v (overflow) flag in ccr c c (carry) flag in ccr pc program counter sp stack pointer #xx:3/8/16 immediate data (3, 8, or 16 bits) d:8/16 displacement (8 or 16 bits) @aa:8/16 absolute address (8 or 16 bits) + addition subtraction multiplication division logical and logical or exclusive logical or move not (logical complement) condition code notation modified according to the instruction result * undetermined (unpredictable) 0 always cleared to 0 not affected by the instruction result 598 table a.1 instruction set mnemonic operation addressing mode/ instruction length operand size #xx: 8/16 rn @rn @(d:16, rn) @?n/@rn+ @aa: 8/16 @(d:8, pc) @@aa implied no. of states ihnzvc condition code ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? mov.b #xx:8, rd mov.b rs, rd mov.b @rs, rd mov.b @(d:16, rs), rd mov.b @rs+, rd mov.b @aa:8, rd mov.b @aa:16, rd mov.b rs, @rd mov.b rs, @(d:16, rd) mov.b rs, @ rd mov.b rs, @aa:8 mov.b rs, @aa:16 mov.w #xx:16, rd mov.w rs, rd mov.w @rs, rd mov.w @(d:16, rs), rd mov.w @rs+, rd mov.w @aa:16, rd mov.w rs, @rd mov.w rs, @(d:16, rd) mov.w rs, @ rd mov.w rs, @aa:16 pop rd push rs #xx:8 rd8 rs8 rd8 @rs16 rd8 @(d:16, rs16) rd8 @rs16 rd8 rs16+1 rs16 @aa:8 rd8 @aa:16 rd8 rs8 @rd16 rs8 @(d:16, rd16) rd16 1 rd16 rs8 @rd16 rs8 @aa:8 rs8 @aa:16 #xx:16 rd rs16 rd16 @rs16 rd16 @(d:16, rs16) rd16 @rs16 rd16 rs16+2 rs16 @aa:16 rd16 rs16 @rd16 rs16 @(d:16, rd16) rd16 2 rd16 rs16 @rd16 rs16 @aa:16 @sp rd16 sp+2 sp sp 2 sp rs16 @sp b b b b b b b b b b b b w w w w w w w w w w w w 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 4 6 6 4 6 4 6 6 4 6 4 2 4 6 6 6 4 6 6 6 6 6 2 2 4 2 2 4 2 4 2 2 4 4 2 2 4 2 4 2 4 2 4 2 2 599 mnemonic operation addressing mode/ instruction length operand size #xx: 8/16 rn @rn @(d:16, rn) @ rn/@rn+ @aa: 8/16 @(d:8, pc) @@aa implied no. of states ihnzvc condition code movfpe @aa:16, rd movtpe rs, @aa:16 eepmov add.b #xx:8, rd add.b rs, rd add.w rs, rd addx.b #xx:8, rd addx.b rs, rd adds.w #1, rd adds.w #2, rd inc.b rd daa.b rd sub.b rs, rd sub.w rs, rd subx.b #xx:8, rd subx.b rs, rd subs.w #1, rd subs.w #2, rd dec.b rd das.b rd neg.b rd cmp.b #xx:8, rd cmp.b rs, rd cmp.w rs, rd mulxu.b rs, rd if r4l 0 then repeat @r5 @r6 r5+1 r5 r6+1 r6 r4l 1 r4l until r4l=0 else next rd8+#xx:8 rd8 rd8+rs8 rd8 rd16+rs16 rd16 rd8+#xx:8 +c rd8 rd8+rs8 +c rd8 rd16+1 rd16 rd16+2 rd16 rd8+1 rd8 rd8 decimal adjust rd8 rd8 rs8 rd8 rd16 rs16 rd16 rd8 #xx:8 c rd8 rd8 rs8 c rd8 rd16 1 rd16 rd16 2 rd16 rd8 1 rd8 rd8 decimal adjust rd8 0 rd rd rd8 #xx:8 rd8 rs8 rd16 rs16 rd8 rs8 rd16 b b w b b w w b b b w b b w w b b b b b w b b b not supported not supported (5) (5) (4) 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 14 4 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 ? ? ? ? ? ? ? ? ? ? (1) ? ? ? ? (2) ? ? ? (2) ? ? ? ? ? ? ** (3) ? ? ? ? ? ? ? (1) ? ? ? ? (2) ? ? ? ? (2) ? ? ? ? ? ? ? ** ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? (1) ? ? ? ? ? ? 600 mnemonic operation addressing mode/ instruction length operand size #xx: 8/16 rn @rn @(d:16, rn) @ rn/@rn+ @aa: 8/16 @(d:8, pc) @@aa implied no. of states ihnzvc condition code ? ? divxu.b rs, rd and.b #xx:8, rd and.b rs, rd or.b #xx:8, rd or.b rs, rd xor.b #xx:8, rd xor.b rs, rd not.b rd shal.b rd shar.b rd shll.b rd shlr.b rd rotxl.b rd rotxr.b rd rotl.b rd rotr.b rd rd16 rs8 rd16 (rdh: remainder, rdl: quotient) rd8 #xx:8 rd8 rd8 rs8 rd8 rd8 #xx:8 rd8 rd8 rs8 rd8 rd8 #xx:8 rd8 rd8 rs8 rd8 rd rd b b b b b b b b b b b b b b b b 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 (6) 0 (7) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? b 7 b 0 0 c b 7 b 0 0 c c b 7 b 0 b 7 b 0 0c c b 7 b 0 c b 7 b 0 c b 7 b 0 c b 7 b 0 601 mnemonic operation addressing mode/ instruction length operand size #xx: 8/16 rn @rn @(d:16, rn) @ rn/@rn+ @aa: 8/16 @(d:8, pc) @@aa implied no. of states ihnzvc condition code ? bset #xx:3, rd bset #xx:3, @rd bset #xx:3, @aa:8 bset rn, rd bset rn, @rd bset rn, @aa:8 bclr #xx:3, rd bclr #xx:3, @rd bclr #xx:3, @aa:8 bclr rn, rd bclr rn, @rd bclr rn, @aa:8 bnot #xx:3, rd bnot #xx:3, @rd bnot #xx:3, @aa:8 bnot rn, rd bnot rn, @rd bnot rn, @aa:8 btst #xx:3, rd btst #xx:3, @rd btst #xx:3, @aa:8 btst rn, rd btst rn, @rd btst rn, @aa:8 (#xx:3 of rd8) 1 (#xx:3 of @rd16) 1 (#xx:3 of @aa:8) 1 (rn8 of rd8) 1 (rn8 of @rd16) 1 (rn8 of @aa:8) 1 (#xx:3 of rd8) 0 (#xx:3 of @rd16) 0 (#xx:3 of @aa:8) 0 (rn8 of rd8) 0 (rn8 of @rd16) 0 (rn8 of @aa:8) 0 (#xx:3 of rd8) ( #xx:3 of rd8 ) (#xx:3 of @rd16) ( #xx:3 of @rd16 ) (#xx:3 of @aa:8) ( #xx:3 of @aa:8 ) (rn8 of rd8) ( rn8 of rd8 ) (rn8 of @rd16) ( rn8 of @rd16 ) (rn8 of @aa:8) ( rn8 of @aa:8 ) ( #xx:3 of rd8 ) z ( #xx:3 of @rd16 ) z ( #xx:3 of @aa:8 ) z ( rn8 of rd8 ) z ( rn8 of @rd16 ) z ( rn8 of @aa:8 ) z b b b b b b b b b b b b b b b b b b b b b b b b 2 2 2 2 2 2 2 2 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 2 8 8 2 8 8 2 8 8 2 8 8 2 8 8 2 8 8 2 6 6 2 6 6 ? ? ? ? ? 602 mnemonic operation addressing mode/ instruction length operand size #xx: 8/16 rn @rn @(d:16, rn) @ rn/@rn+ @aa: 8/16 @(d:8, pc) @@aa implied no. of states ihnzvc condition code ? bld #xx:3, rd bld #xx:3, @rd bld #xx:3, @aa:8 bild #xx:3, rd bild #xx:3, @rd bild #xx:3, @aa:8 bst #xx:3, rd bst #xx:3, @rd bst #xx:3, @aa:8 bist #xx:3, rd bist #xx:3, @rd bist #xx:3, @aa:8 band #xx:3, rd band #xx:3, @rd band #xx:3, @aa:8 biand #xx:3, rd biand #xx:3, @rd biand #xx:3, @aa:8 bor #xx:3, rd bor #xx:3, @rd bor #xx:3, @aa:8 bior #xx:3, rd bior #xx:3, @rd bior #xx:3, @aa:8 bxor #xx:3, rd bxor #xx:3, @rd bxor #xx:3, @aa:8 bixor #xx:3, rd (#xx:3 of rd8) c (#xx:3 of @rd16) c (#xx:3 of @aa:8) c ( #xx:3 of rd8 ) c ( #xx:3 of @rd16 ) c ( #xx:3 of @aa:8 ) c c (#xx:3 of rd8) c (#xx:3 of @rd16) c (#xx:3 of @aa:8) c (#xx:3 of rd8) c (#xx:3 of @rd16) c (#xx:3 of @aa:8) c (#xx:3 of rd8) c c (#xx:3 of @rd16) c c (#xx:3 of @aa:8) c c ( #xx:3 of rd8 ) c c ( #xx:3 of @rd16 ) c c ( #xx:3 of @aa:8 ) c c (#xx:3 of rd8) c c (#xx:3 of @rd16) c c (#xx:3 of @aa:8) c c ( #xx:3 of rd8 ) c c ( #xx:3 of @rd16 ) c c ( #xx:3 of @aa:8 ) c c (#xx:3 of rd8) c c (#xx:3 of @rd16) c c (#xx:3 of @aa:8) c c ( #xx:3 of rd8 ) c b b b b b b b b b b b b b b b b b b b b b b b b b b b b 2 2 2 2 2 2 2 2 2 2 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 2 6 6 2 6 6 2 8 8 2 8 8 2 6 6 2 6 6 2 6 6 2 6 6 2 6 6 2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 603 mnemonic operation addressing mode/ instruction length operand size #xx: 8/16 rn @rn @(d:16, rn) @ rn/@rn+ @aa: 8/16 @(d:8, pc) @@aa implied no. of states ihnzvc condition code ? bixor #xx:3, @rd bixor #xx:3, @aa:8 bra d:8 (bt d:8) brn d:8 (bf d:8) bhi d:8 bls d:8 bcc d:8 (bhs d:8) bcs d:8 (blo d:8) bne d:8 beq d:8 bvc d:8 bvs d:8 bpl d:8 bmi d:8 bge d:8 blt d:8 bgt d:8 ble d:8 jmp @rn jmp @aa:16 jmp @@aa:8 bsr d:8 jsr @rn jsr @aa:16 c ( #xx:3 of @rd16 ) c c ( #xx:3 of @aa:8 ) c pc pc+d:8 pc pc+2 if condition is true then pc pc+d:8 else next; b b 4 2 2 4 4 4 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 6 6 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 6 8 6 6 8 c z = 0 c z = 1 c = 0 c = 1 z = 0 z = 1 v = 0 v = 1 n = 0 n = 1 n v = 0 n v = 1 z (n v) = 0 z (n v) = 1 pc rn16 pc aa:16 pc @aa:8 sp 2 sp pc @sp pc pc+d:8 sp 2 sp pc @sp pc rn16 sp 2 sp pc @sp pc aa:16 ? branching condition 604 mnemonic operation addressing mode/ instruction length operand size #xx: 8/16 rn @rn @(d:16, rn) @ rn/@rn+ @aa: 8/16 @(d:8, pc) @@aa implied no. of states ihnzvc condition code jsr @@aa:8 rts rte sleep ldc #xx:8, ccr ldc rs, ccr stc ccr, rd andc #xx:8, ccr orc #xx:8, ccr xorc #xx:8, ccr nop sp 2 sp pc @sp pc @aa:8 pc @sp sp+2 sp ccr @sp sp+2 sp pc @sp sp+2 sp transition to power-down state. #xx:8 ccr rs8 ccr ccr rd8 ccr #xx:8 ccr ccr #xx:8 ccr ccr #xx:8 ccr pc pc+2 b b b b b b 2 8 8 10 2 2 2 2 2 2 2 2 2 ? ? 2 ? ? ? ? 2 ? ? 2 ? ? ? ? ? ? 2 ? ? ? ? 2 ? ? 2 ? ? ? ? ? ? 2 ? ? ? ? ? ? 2 ? ? ? ? 2 notes: the number of states is the number of states required for execution when the instruction and its operands are located in on-chip memory. (1) set to 1 when there is a carry or borrow from bit 11; otherwise cleared to 0. (2) if the result is zero, the previous value of the flag is retained; otherwise the flag is cleared to 0. (3) set to 1 if decimal adjustment produces a carry; otherwise retains its previous value. (4) the number of states required for execution is 4n+8 (n = value of r4l). (5) these instructions are not supported by the h8/3337 series and h8/3397 series. (6) set to 1 if the divisor is negative; otherwise cleared to 0. (7) set to 1 if the divisor is 0; otherwise cleared to 0. 605 a.2 operation code map table a.2 is a map of the operation codes contained in the first byte of the instruction code (bits 15 to 8 of the first instruction word). some pairs of instructions have identical first bytes. these instructions are differentiated by the first bit of the second byte (bit 7 of the first instruction word). instruction when first bit of byte 2 (bit 7 of first instruction word) is 0. instruction when first bit of byte 2 (bit 7 of first instruction word) is 1. 606 table a.2 operation code map high low 0123456789abcdef 0 1 2 3 4 5 6 7 8 9 a b c d e f nop bra * 2 mulxu bset shll shal sleep brn * 2 divxu bnot shlr shar stc bhi bclr rotxl rotl ldc bls bts rotxr rotr orc or bcc * 2 rts xorc xor bcs * 2 bsr bor bior bxor bixor band biand andc and bne rte ldc beq not neg bld bild bst bist add sub bvc bvs mov inc dec bpl jmp adds subs bmi eepmov mov cmp bge blt addx subx bgt jsr daa das ble mov add addx cmp subx or xor and mov mov * 1 notes: * 1 * 2 bit manipulation instructions the movfpe and movtpe instructions are identical to mov instructions in the first byte and first bit of the second byte (bits 1 5 to 7 of the instruction word). the push and pop instructions are identical in machine language to mov instructions. the bt, bf, bhs, and blo instructions are identical in machine language to bra, brn, bcc, and bcs, respectively. 607 a.3 number of states required for execution the tables below can be used to calculate the number of states required for instruction execution. table a.3 indicates the number of states required for each cycle (instruction fetch, branch address read, stack operation, byte data access, word data access, internal operation). table a.4 indicates the number of cycles of each type occurring in each instruction. the total number of states required for execution of an instruction can be calculated from these two tables as follows: execution states = i s i + j s j + k s k + l s l + m s m + n s n examples: mode 1 (on-chip rom disabled), stack located in external memory, 1 wait state inserted in external memory access. 1. bset #0, @ffc7 from table a.4: i = l = 2, j = k = m = n= 0 from table a.3: s i = 8, s l = 3 number of states required for execution: 2 8 + 2 3 = 22 2. jsr @@30 from table a.4: i = 2, j = k = 1, l = m = n = 0 from table a.3: s i = s j = s k = 8 number of states required for execution: 2 8 + 1 8 + 1 8 = 32 table a.3 number of states taken by each cycle in instruction execution access location execution status (instruction cycle) on-chip memory on-chip supporting module external device instruction fetch s i 2 6 6 + 2m branch address read s j stack operation s k byte data access s l 3 3 + m word data access s m 6 6 + 2m internal operation s n 11 1 note: m: number of wait states inserted in access to external device. 608 table a.4 number of cycles in each instruction instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n add add.b #xx:8, rd 1 add.b rs, rd 1 add.w rs, rd 1 adds adds.w #1/2, rd 1 addx addx.b #xx:8, rd 1 addx.b rs, rd 1 and and.b #xx:8, rd 1 and.b rs, rd 1 andc andc #xx:8, ccr 1 band band #xx:3, rd 1 band #xx:3, @rd 2 1 band #xx:3, @aa:8 2 1 bcc bra d:8 (bt d:8) 2 brn d:8 (bf d:8) 2 bhi d:8 2 bls d:8 2 bcc d:8 (bhs d:8) 2 bcs d:8 (blo d:8) 2 bne d:8 2 beq d:8 2 bvc d:8 2 bvs d:8 2 bpl d:8 2 bmi d:8 2 bge d:8 2 blt d:8 2 bgt d:8 2 ble d:8 2 bclr bclr #xx:3, rd 1 bclr #xx:3, @rd 2 2 bclr #xx:3, @aa:8 2 2 bclr rn, rd 1 bclr rn, @rd 2 2 bclr rn, @aa:8 2 2 609 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n biand biand #xx:3, rd 1 biand #xx:3, @rd 2 1 biand #xx:3, @aa:8 2 1 bild bild #xx:3, rd 1 bild #xx:3, @rd 2 1 bild #xx:3, @aa:8 2 1 bior bior #xx:3, rd 1 bior #xx:3, @rd 2 1 bior #xx:3, @aa:8 2 1 bist bist #xx:3, rd 1 bist #xx:3, @rd 2 2 bist #xx:3, @aa:8 2 2 bixor bixor #xx:3, rd 1 bixor #xx:3, @rd 2 1 bixor #xx:3, @aa:8 2 1 bld bld #xx:3, rd 1 bld #xx:3, @rd 2 1 bld #xx:3, @aa:8 2 1 bnot bnot #xx:3, rd 1 bnot #xx:3, @rd 2 2 bnot #xx:3, @aa:8 2 2 bnot rn, rd 1 bnot rn, @rd 2 2 bnot rn, @aa:8 2 2 bor bor #xx:3, rd 1 bor #xx:3, @rd 2 1 bor #xx:3, @aa:8 2 1 bset bset #xx:3, rd 1 bset #xx:3, @rd 2 2 bset #xx:3, @aa:8 2 2 bset rn, rd 1 bset rn, @rd 2 2 bset rn, @aa:8 2 2 610 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n bsr bsr d:8 2 1 bst bst #xx:3, rd 1 bst #xx:3, @rd 2 2 bst #xx:3, @aa:8 2 2 btst btst #xx:3, rd 1 btst #xx:3, @rd 2 1 btst #xx:3, @aa:8 2 1 btst rn, rd 1 btst rn, @rd 2 1 btst rn, @aa:8 2 1 bxor bxor #xx:3, rd 1 bxor #xx:3, @rd 2 1 bxor #xx:3, @aa:8 2 1 cmp cmp.b #xx:8, rd 1 cmp.b rs, rd 1 cmp.w rs, rd 1 daa daa.b rd 1 das das.b rd 1 dec dec.b rd 1 divxu divxu.b rs, rd 1 12 eepmov eepmov 2 2n+2 * 1 inc inc.b rd 1 jmp jmp @rn 2 jmp @aa:16 2 2 jmp @@aa:8 2 1 2 jsr jsr @rn 2 1 jsr @aa:16 2 1 2 jsr @@aa:8 2 1 1 ldc ldc #xx:8, ccr 1 ldc rs, ccr 1 611 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n mov mov.b #xx:8, rd 1 mov.b rs, rd 1 mov.b @rs, rd 1 1 mov.b @(d:16,rs), rd 21 mov.b @rs+, rd 1 1 2 mov.b @aa:8, rd 1 1 mov.b @aa:16, rd 2 1 mov.b rs, @rd 1 1 mov.b rs, @(d:16, rd) 21 mov.b rs, @ rd 1 1 2 mov.b rs, @aa:8 1 1 mov.b rs, @aa:16 2 1 mov.w #xx:16, rd 2 mov.w rs, rd 1 mov.w @rs, rd 1 1 mov.w @(d:16, rs), rd 21 mov.w @rs+, rd 1 1 2 mov.w @aa:16, rd 2 1 mov.w rs, @rd 1 1 mov.w rs, @(d:16, rd) 21 mov.w rs, @ rd 1 1 2 mov.w rs, @aa:16 2 1 movfpe movfpe @aa:16, rd not supported movtpe movtpe rs, @aa:16 not supported mulxu mulxu.b rs, rd 1 12 neg neg.b rd 1 nop nop 1 not not.b rd 1 612 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n or or.b #xx:8, rd 1 or.b rs, rd 1 orc orc #xx:8, ccr 1 pop pop rd 1 1 2 push push rd 1 1 2 rotl rotl.b rd 1 rotr rotr.b rd 1 rotxl rotxl.b rd 1 rotxr rotxr.b rd 1 rte rte 2 2 2 rts rts 2 1 2 shal shal.b rd 1 shar shar.b rd 1 shll shll.b rd 1 shlr shlr.b rd 1 sleep sleep 1 stc stc ccr, rd 1 sub sub.b rs, rd 1 sub.w rs, rd 1 subs subs.w #1/2, rd 1 subx subx.b #xx:8, rd 1 subx.b rs, rd 1 xor xor.b #xx:8, rd 1 xor.b rs, rd 1 xorc xorc #xx:8, ccr 1 note: all values left blank are zero. * n: initial value in r4l. source and destination are accessed n + 1 times each. 613 appendix b interrupt i/o register b.1 addresses b.1.1 addresses for h8/3337 series addr. (last register bit names byte) name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module h'80 flmcr * 1, * 2 v pp ?vpve p flash memory or external flmcr1 * 3 fwe swe ev pv e p addresses (in expanded h'81 flmcr2 * 3 fler ?supsu modes) h'82 * 4 ebr1 * 1 lb3lb2lb1lb0 ebr1 * 2 lb7 lb6 lb5 lb4 lb3 lb2 lb1 lb0 h'83 ebr2 * 1, * 2 sb7 sb6 sb5 sb4 sb3 sb2 sb1 sb0 ebr2 * 3 eb7 eb6 eb5 eb4 eb3 eb2 eb1 eb0 h'84 h'85 h'86 h'87 h'88 smr c/ a chr pe o/ e stop mp cks1 cks0 sci1 h'89 brr h'8a scr tie rie te re mpie teie cke1 cke0 h'8b tdr h'8c ssr tdre rdrf orer fer per tend mpb mpbt h'8d rdr h'8e h'8f h'90 tier iciae icibe icice icide ociae ocibe ovie frt h'91 tcsr icfa icfb icfc icfd ocfa ocfb ovf cclra h'92 frc (h) h'93 frc (l) h'94 ocra (h) ocrb (h) h'95 ocra (l) ocrb (l) 614 addr. (last register bit names byte) name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module h'96 tcr iedga iedgb iedgc iedgd bufea bufeb cks1 cks0 frt h'97 tocr ocrs oea oeb olvla olvlb h'98 icra (h) h'99 icra (l) h'9a icrb (h) h'9b icrb (l) h'9c icrc (h) h'9d icrc (l) h'9e icrd (h) h'9f icrd (l) h'a0 tcr oe os cks2 cks1 cks0 pwm0 h'a1 dtr h'a2 tcnt h'a3 h'a4 tcr oe os cks2 cks1 cks0 pwm1 h'a5 dtr h'a6 tcnt h'a7 h'a8 tcsr/ tcnt ovf wt/ it tme rst/ nmi cks2 cks1 cks0 wdt h'a9 tcnt h'aa h'ab h'ac p1pcr p1 7 pcr p1 6 pcr p1 5 pcr p1 4 pcr p1 3 pcr p1 2 pcr p1 1 pcr p1 0 pcr port 1 h'ad p2pcr p2 7 pcr p2 6 pcr p2 5 pcr p2 4 pcr p2 3 pcr p2 2 pcr p2 1 pcr p2 0 pcr port 2 h'ae p3pcr p3 7 pcr p3 6 pcr p3 5 pcr p3 4 pcr p3 3 pcr p3 2 pcr p3 1 pcr p3 0 pcr port 3 h'af h'b0 p1ddr p1 7 ddr p1 6 ddr p1 5 ddr p1 4 ddr p1 3 ddr p1 2 ddr p1 1 ddr p1 0 ddr port 1 h'b1 p2ddr p2 7 ddr p2 6 ddr p2 5 ddr p2 4 ddr p2 3 ddr p2 2 ddr p2 1 ddr p2 0 ddr port 2 h'b2 p1dr p1 7 p1 6 p1 5 p1 4 p1 3 p1 2 p1 1 p1 0 port 1 h'b3 p2dr p2 7 p2 6 p2 5 p2 4 p2 3 p2 2 p2 1 p2 0 port 2 h'b4 p3ddr p3 7 ddr p3 6 ddr p3 5 ddr p3 4 ddr p3 3 ddr p3 2 ddr p3 1 ddr p3 0 ddr port 3 h'b5 p4ddr p4 7 ddr p4 6 ddr p4 5 ddr p4 4 ddr p4 3 ddr p4 2 ddr p4 1 ddr p4 0 ddr port 4 h'b6 p3dr p3 7 p3 6 p3 5 p3 4 p3 3 p3 2 p3 1 p3 0 port 3 615 addr. (last register bit names byte) name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module h'b7 p4dr p4 7 p4 6 p4 5 p4 4 p4 3 p4 2 p4 1 p4 0 port 4 h'b8 p5ddr ?5 2 ddr p5 1 ddr p5 0 ddr port 5 h'b9 p6ddr p6 7 ddr p6 6 ddr p6 5 ddr p6 4 ddr p6 3 ddr p6 2 ddr p6 1 ddr p6 0 ddr port 6 h'ba p5dr ?5 2 p5 1 p5 0 port 5 h'bb p6dr p6 7 p6 6 p6 5 p6 4 p6 3 p6 2 p6 1 p6 0 port 6 h'bc h'bd p8ddr p8 6 ddr p8 5 ddr p8 4 ddr p8 3 ddr p8 2 ddr p8 1 ddr p8 0 ddr port 8 h'be p7pin p7 7 p7 6 p7 5 p7 4 p7 3 p7 2 p7 1 p7 0 port 7 h'bf p8dr p8 6 p8 5 p8 4 p8 3 p8 2 p8 1 p8 0 port 8 h'c0 p9ddr p9 7 ddr p9 6 ddr p9 5 ddr p9 4 ddr p9 3 ddr p9 2 ddr p9 1 ddr p9 0 ddr port 9 h'c1 p9dr p9 7 p9 6 p9 5 p9 4 p9 3 p9 2 p9 1 p9 0 h'c2 wscr rams * 2 ram0 * 2 ckdbl flshe * 3 wms1 wms0 wc1 wc0 h'c3 stcr iics iicd iicx iice stac mpe icks1 icks0 h'c4 syscr ssby sts2 sts1 sts0 xrst nmieg hie rame h'c5 mdcr expe * 3 mds1 mds0 h'c6 iscr irq7sc irq6sc irq5sc irq4sc irq3sc irq2sc irq1sc irq0sc h'c7 ier irq7e irq6e irq5e irq4e irq3e irq2e irq1e irq0e h'c8 tcr cmieb cmiea ovie cclr1 cclr0 cks2 cks1 cks0 tmr0 h'c9 tcsr cmfb cmfa ovf os3 os2 os1 os0 h'ca tcora h'cb tcorb h'cc tcnt h'cd h'ce h'cf h'd0 tcr cmieb cmiea ovie cclr1 cclr0 cks2 cks1 cks0 tmr1 h'd1 tcsr cmfb cmfa ovf os3 os2 os1 os0 h'd2 tcora h'd3 tcorb h'd4 tcnt h'd5 h'd6 h'd7 616 addr. (last register bit names byte) name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module h'd8 smr c/ a chr pe o/ e stop mp cks1 cks0 sci0 and i 2 c iccr ice ieic mst trs ack cks2 cks1 cks0 h'd9 brr icsr bbsy iric scp al aas adz ackb h'da scr tie rie te re mpie teie cke1 cke0 h'db tdr h'dc ssr tdre rdrf orer fer per tend mpb mpbt h'dd rdr h'de icdr icdr7 icdr6 icdr5 icdr4 icdr3 icdr2 icdr1 icdr0 h'df icmr/ sar mls/ sva6 wait/ sva5 ? sva4 ? sva3 ? sva2 bc2/ sva1 bc1/ sva0 bc0/ fs h'e0 addrah ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 a/d h'e1 addral ad1 ad0 h'e2 addrbh ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 h'e3 addrbl ad1 ad0 h'e4 addrch ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 h'e5 addrcl ad1 ad0 h'e6 addrdh ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 h'e7 addrdl ad1 ad0 h'e8 adcsr adf adie adst scan cks ch2 ch1 ch0 h'e9 adcr trge h'ea h'eb h'ec h'ed h'ee h'ef h'f0 hicr ibfie2 ibfie1 fga20e hif h'f1 kmimr kmimr7 kmimr6 kmimr5 kmimr4 kmimr3 kmimr2 kmimr1 kmimr0 h'f2 kmpcr km 7 pcr km 6 pcr km 5 pcr km 4 pcr km 3 pcr km 2 pcr km 1 pcr km 0 pcr port6 h'f3 617 addr. (last register bit names byte) name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module h'f4 idr1 idr7 idr6 idr5 idr4 idr3 idr2 idr1 idr0 hif1 h'f5 odr1 odr7 odr6 odr5 odr4 odr3 odr2 odr1 odr0 h'f6 str1 dbu dbu dbu dbu c/ d dbu ibf obf h'f7 h'f8 dadr0 d/a h'f9 dadr1 h'fa dacr daoe1 daoe0 dae h'fb h'fc idr2 idr7 idr6 idr5 idr4 idr3 idr2 idr1 idr0 hif2 h'fd odr2 odr7 odr6 odr5 odr4 odr3 odr2 odr1 odr0 h'fe str2 dbu dbu dbu dbu c/ d dbu ibf obf h'ff notes: * 1 applies to h8/3334yf only (32k on-chip dual-power-supply flash memory version). * 2 applies to h8/3337yf only (60k on-chip dual-power-supply flash memory version). * 3 applies to h8/3337sf only (60k on-chip single-power-supply flash memory version). * 4 do not use this address with single-power-supply flash memory. frt: 16-bit free-running timer sci1: serial communication interface 1 pwm0: pulse-width modulation timer channel 0 pwm1: pulse-width modulation timer channel 1 wdt: watchdog timer tmr0: 8-bit timer channel 0 tmr1: 8-bit timer channel 1 sci0: serial communication interface 0 i 2 c: i 2 c bus interface hif: host interface 618 b.1.2 addresses for h8/3397 series addr. (last register bit names byte) name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module h'80 external addresses (in h'81 expanded modes) h'82 h'83 h'84 h'85 h'86 h'87 h'88 smr c/ a chr pe o/ e stop mp cks1 cks0 sci1 h'89 brr h'8a scr tie rie te re mpie teie cke1 cke0 h'8b tdr h'8c ssr tdre rdrf orer fer per tend mpb mpbt h'8d rdr h'8e h'8f h'90 tier iciae icibe icice icide ociae ocibe ovie frt h'91 tcsr icfa icfb icfc icfd ocfa ocfb ovf cclra h'92 frc (h) h'93 frc (l) h'94 ocra (h) ocrb (h) h'95 ocra (l) ocrb (l) h'96 tcr iedga iedgb iedgc iedgd bufea bufeb cks1 cks0 h'97 tocr ocrs oea oeb olvla olvlb h'98 icra (h) h'99 icra (l) h'9a icrb (h) 619 addr. (last register bit names byte) name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module h'9b icrb (l) frt h'9c icrc (h) h'9d icrc (l) h'9e icrd (h) h'9f icrd (l) h'a0 tcr oe os cks2 cks1 cks0 pwm0 h'a1 dtr h'a2 tcnt h'a3 h'a4 tcr oe os cks2 cks1 cks0 pwm1 h'a5 dtr h'a6 tcnt h'a7 h'a8 tcsr/ tcnt ovf wt/ it tme rst/ nmi cks2 cks1 cks0 wdt h'a9 tcnt h'aa h'ab h'ac p1pcr p1 7 pcr p1 6 pcr p1 5 pcr p1 4 pcr p1 3 pcr p1 2 pcr p1 1 pcr p1 0 pcr port 1 h'ad p2pcr p2 7 pcr p2 6 pcr p2 5 pcr p2 4 pcr p2 3 pcr p2 2 pcr p2 1 pcr p2 0 pcr port 2 h'ae p3pcr p3 7 pcr p3 6 pcr p3 5 pcr p3 4 pcr p3 3 pcr p3 2 pcr p3 1 pcr p3 0 pcr port 3 h'af h'b0 p1ddr p1 7 ddr p1 6 ddr p1 5 ddr p1 4 ddr p1 3 ddr p1 2 ddr p1 1 ddr p1 0 ddr port 1 h'b1 p2ddr p2 7 ddr p2 6 ddr p2 5 ddr p2 4 ddr p2 3 ddr p2 2 ddr p2 1 ddr p2 0 ddr port 2 h'b2 p1dr p1 7 p1 6 p1 5 p1 4 p1 3 p1 2 p1 1 p1 0 port 1 h'b3 p2dr p2 7 p2 6 p2 5 p2 4 p2 3 p2 2 p2 1 p2 0 port 2 h'b4 p3ddr p3 7 ddr p3 6 ddr p3 5 ddr p3 4 ddr p3 3 ddr p3 2 ddr p3 1 ddr p3 0 ddr port 3 h'b5 p4ddr p4 7 ddr p4 6 ddr p4 5 ddr p4 4 ddr p4 3 ddr p4 2 ddr p4 1 ddr p4 0 ddr port 4 h'b6 p3dr p3 7 p3 6 p3 5 p3 4 p3 3 p3 2 p3 1 p3 0 port 3 h'b7 p4dr p4 7 p4 6 p4 5 p4 4 p4 3 p4 2 p4 1 p4 0 port 4 h'b8 p5ddr ?5 2 ddr p5 1 ddr p5 0 ddr port 5 h'b9 p6ddr p6 7 ddr p6 6 ddr p6 5 ddr p6 4 ddr p6 3 ddr p6 2 ddr p6 1 ddr p6 0 ddr port 6 620 addr. (last register bit names byte) name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module h'ba p5dr ?5 2 p5 1 p5 0 port 5 h'bb p6dr p6 7 p6 6 p6 5 p6 4 p6 3 p6 2 p6 1 p6 0 port 6 h'bc h'bd p8ddr p8 6 ddr p8 5 ddr p8 4 ddr p8 3 ddr p8 2 ddr p8 1 ddr p8 0 ddr port 8 h'be p7pin p7 7 p7 6 p7 5 p7 4 p7 3 p7 2 p7 1 p7 0 port 7 h'bf p8dr p8 6 p8 5 p8 4 p8 3 p8 2 p8 1 p8 0 port 8 h'c0 p9ddr p9 7 ddr p9 6 ddr p9 5 ddr p9 4 ddr p9 3 ddr p9 2 ddr p9 1 ddr p9 0 ddr port 9 h'c1 p9dr p9 7 p9 6 p9 5 p9 4 p9 3 p9 2 p9 1 p9 0 h'c2 wscr ckdbl wms1 wms0 wc1 wc0 h'c3 stcr ?pe icks1 icks0 h'c4 syscr ssby sts2 sts1 sts0 xrst nmieg rame h'c5 mdcr mds1 mds0 h'c6 iscr irq7sc irq6sc irq5sc irq4sc irq3sc irq2sc irq1sc irq0sc h'c7 ier irq7e irq6e irq5e irq4e irq3e irq2e irq1e irq0e h'c8 tcr cmieb cmiea ovie cclr1 cclr0 cks2 cks1 cks0 tmr0 h'c9 tcsr cmfb cmfa ovf os3 os2 os1 os0 h'ca tcora h'cb tcorb h'cc tcnt h'cd h'ce h'cf h'd0 tcr cmieb cmiea ovie cclr1 cclr0 cks2 cks1 cks0 tmr1 h'd1 tcsr cmfb cmfa ovf os3 os2 os1 os0 h'd2 tcora h'd3 tcorb h'd4 tcnt h'd5 h'd6 h'd7 621 addr. (last register bit names byte) name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module h'd8 smr c/ a chr pe o/ e stop mp cks1 cks0 sci0 h'd9 brr h'da scr tie rie te re mpie teie cke1 cke0 h'db tdr h'dc ssr tdre rdrf orer fer per tend mpb mpbt h'dd rdr h'de h'df h'e0 addrah ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 a/d h'e1 addral ad1 ad0 h'e2 addrbh ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 h'e3 addrbl ad1 ad0 h'e4 addrch ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 h'e5 addrcl ad1 ad0 h'e6 addrdh ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 h'e7 addrdl ad1 ad0 h'e8 adcsr adf adie adst scan cks ch2 ch1 ch0 h'e9 adcr trge h'ea h'eb h'ec h'ed h'ee h'ef h'f0 h'f1 kmimr kmimr7 kmimr6 kmimr5 kmimr4 kmimr3 kmimr2 kmimr1 kmimr0 622 addr. (last register bit names byte) name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module h'f2 kmpcr km 7 pcr km 6 pcr km 5 pcr km 4 pcr km 3 pcr km 2 pcr km 1 pcr km 0 pcr h'f3 h'f4 h'f5 h'f6 h'f7 h'f8 h'f9 h'fa h'fb h'fc h'fd h'fe h'ff note: frt: 16-bit free-running timer sci1: serial communication interface 1 pwm0: pulse-width modulation timer channel 0 pwm1: pulse-width modulation timer channel 1 wdt: watchdog timer tmr0: 8-bit timer channel 0 tmr1: 8-bit timer channel 1 sci0: serial communication interface 0 623 b.2 function tier?imer interrupt enable register h'ff90 frt bit no. initial value type of access permitted r w r/w abbreviation of register name register name address onto which register is mapped name of on-chip supporting module bit names (abbreviations). bits marked are reserved. full name of bit description of bit function read only write only read or write bit initial value read/write 7 iciae 0 r/w 6 icibe 0 r/w 5 icice 0 r/w 4 icide 0 r/w 3 ociae 0 r/w 0 1 2 ocibe 0 r/w 1 ovie 0 r/w overflow interrupt enable 0 1 overflow interrupt request is disabled. overflow interrupt request is enabled. output compare interrupt b enable 0 1 output compare interrupt request b is disabled. output compare interrupt request b is enabled. output compare interrupt a enable 0 1 output compare interrupt request a is disabled. output compare interrupt request a is enabled. input capture interrupt d enable 0 1 input capture interrupt request d is disabled. input capture interrupt request d is enabled. 624 (dual-power-supply flash memory only) flmcr?lash memory control register h'80 flash memory ? h8/3334yf, h8/3337yf bit initial value read/write 7 v pp 0 r 6 0 5 0 4 0 3 ev 0 r/w 0 p 0 r/w 2 pv 0 r/w 1 e 0 r/w program mode 0 1 exit from program mode (initial value) transition to program mode erase mode 0 1 exit from erase mode (initial value) transition to erase mode programming power 0 1 12 v is not applied to fv pp (initial value) 12 v is applied to fv pp program-verify mode 0 1 exit from program-verify mode (initial value) transition to program-verify mode erase-verify mode 0 1 exit from erase-verify mode (initial value) transition to erase-verify mode 625 (single-power-supply flash memory only) flmcr1?lash memory control register 1 h'80 flash memory ? h8/3337sf bit initial value read/write 7 fwe 1 r 6 swe 0 r/w 5 0 4 0 3 ev 0 r/w 0 p 0 r/w 2 pv 0 r/w 1 e 0 r/w program mode 0 1 exit from program mode (initial value) transition to program mode [setting condition] when swe = 1 erase mode 0 1 exit from erase mode (initial value) transition to erase mode [setting condition] when swe = 1 program-verify mode 0 1 exit from program-verify mode (initial value) transition to program-verify mode [setting condition] when swe = 1 erase-verify mode 0 1 exit from erase-verify mode (initial value) transition to erase-verify mode [setting condition] when swe = 1 flash write enable (controls programming and erasing of flash memory. in the h8/3337sf, this bit is always read as 1.) software write enable 0 1 writes to flash memory disabled (initial value) writes to flash memory enabled note: the flshe bit in wscr must be set to 1 in order for this register to be accessed. 626 (single-power-supply flash memory only) flmcr2?lash memory control register 2 h'81 flash memory ? h8/3337sf bit initial value read/write 7 fler 0 r 6 0 5 0 4 0 3 0 0 psu 0 r/w 2 0 1 esu 0 r/w program setup 0 1 program setup cleared (initial value) program setup [setting condition] when swe = 1 erase setup 0 1 erase setup cleared (initial value) erase setup [setting condition] when swe = 1 flash memory error 0 1 flash memory is operating normally (initial value) an error occurred during flash memory programming/erasing note: the flshe bit in wscr must be set to 1 in order for this register to be accessed. 627 (dual-power-supply flash memory only) ebr1?rase block register 1 h'82 flash memory ? h8/3334yf bit initial value read/write 7 1 6 1 5 1 4 1 3 lb3 0 r/w 0 lb0 0 r/w 2 lb2 0 r/w 1 lb1 0 r/w large block 3 to 0 0 1 block (lb3 to lb0) is not selected (initial value) block (lb3 to lb0) is selected ? h8/3337yf bit initial value read/write 7 lb7 0 r/w 6 lb6 0 r/w 5 lb5 0 r/w 4 lb4 0 r/w 3 lb3 0 r/w 0 lb0 0 r/w 2 lb2 0 r/w 1 lb1 0 r/w large block 7 to 0 0 1 block (lb7 to lb0) is not selected (initial value) block (lb7 to lb0) is selected 628 ebr2?rase block register 2 h'83 flash memory ? h8/3334yf, h8/3337yf bit initial value read/write 7 sb7 0 r/w 6 sb6 0 r/w 5 sb5 0 r/w 4 sb4 0 r/w 3 sb3 0 r/w 0 sb0 0 r/w 2 sb2 0 r/w 1 sb1 0 r/w small block 7 to 0 0 1 block (sb7 to sb0) is not selected (initial value) block (sb7 to sb0) is selected ? h8/3337sf bit initial value read/write 7 eb7 0 r/w 6 eb6 0 r/w 5 eb5 0 r/w 4 eb4 0 r/w 3 eb3 0 r/w 0 eb0 0 r/w 2 eb2 0 r/w 1 eb1 0 r/w erase block 7 to 0 0 1 corresponding block (eb7 to eb0) is not selected (initial value) corresponding block (eb7 to eb0) is selected 629 smr?erial mode register h'88 sci1 bit initial value read/write 7 c/a 0 r/w 6 chr 0 r/w 5 pe 0 r/w 4 o/e 0 r/w 3 stop 0 r/w 0 cks0 0 r/w 2 mp 0 r/w 1 cks1 0 r/w clock select 0 0 1 1 0 1 0 1 clock p /4 clock p /16 clock p /64 clock multiprocessor mode 0 1 multiprocessor function disabled multiprocessor format selected stop bit length 0 1 one stop bit two stop bits parity mode 0 1 even parity odd parity parity enable 0 transmit: receive: character length 0 1 8-bit data length 7-bit data length communication mode 0 1 asynchronous synchronous transmit: receive: 1 no parity bit added. parity bit not checked. parity bit added. parity bit checked. 630 brr?it rate register h'89 sci1 bit initial value read/write 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w constant that determines the bit rate 631 scr?erial control register h'8a sci1 bit initial value read/write 7 tie 0 r/w 6 rie 0 r/w 5 te 0 r/w 4 re 0 r/w 3 mpie 0 r/w 0 cke0 0 r/w 2 teie 0 r/w 1 cke1 0 r/w clock enable 0 0 1 sck pin not used sck pin uesd for serial clock output. clock enable 1 0 1 internal clock external clock transmit end interrupt enable 0 1 tsr-empty interrupt request is disabled. tsr-empty interrupt request is enabled. multiprocessor interrupt enable 0 1 multiprocessor receive interrupt function is disabled. multiprocessor receive interrupt function is enabled. receive enable 0 1 receive disabled receive enabled transmit enable 0 1 transmit disabled transmit enabled receive interrupt enable 0 1 receive end interrupt and receive error requests are disabled. receive end interrupt and receive error requests are enabled. transmit interrupt enable 0 1 tdr-empty interrupt request is disabled. tdr-empty interrupt request is enabled. 632 tdr?ransmit data register h'8b sci1 bit initial value read/write 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w transmit data 633 ssr?erial status register h'8c sci1 bit initial value read/write 7 tdre 1 r/(w) 6 rdrf 0 r/(w) 5 orer 0 r/(w) 4 fer 0 r/(w) 3 per 0 r/(w) 0 mpbt 0 r/w 2 tend 1 r 1 mpb 0 r multiprocessor bit transfer 0 1 multiprocessor bit = 0 in transmit data. (initial value) multiprocessor bit = 1 in transmit data. multiprocessor bit transmit end 0 1 cleared by reading tdre = 1, then writing 0 in tdre. set to 1 when te = 0, or when tdre = 1 at the end of character transmission. (initial value) parity error 0 1 cleared by reading per = 1, then writing 0 in per. (initial value) set when a parity error occurs (parity of receive data does not match parity selected by o/e bit in smr). framing error 0 1 cleared by reading fer = 1, then writing 0 in fer. (initial value) set when a framing error occurs (stop bit is 0). overrun error 0 1 cleared by reading orer = 1, then writing 0 in orer. (initial value) set when an overrun error occurs (next data is completely received while rdrf bit is set to 1). receive data register full 0 1 cleared by reading rdrf = 1, then writing 0 in rdrf. (initial value) set when one character is received normally and transferred from rsr to rdr. transmit data register empty 0 1 cleared by reading tdre = 1, then writing 0 in tdre. set when: (initial value) 1. data is transferred from tdr to tsr. 2. te is cleared while tdre = 0. ***** note: * software can write a 0 in bits 7 to 3 to clear the fla g s, but cannot write a 1 in these bits. 0 1 multiprocessor bit = 0 in receive data. (initial value) multiprocessor bit = 1 in receive data. 634 rdr?eceive data register h'8d sci1 bit initial value read/write 7 0 r 6 0 r 5 0 r 4 0 r 3 0 r 0 0 r 2 0 r 1 0 r receive data 635 tier?imer interrupt enable register h'90 frt bit initial value read/write 7 iciae 0 r/w 6 icibe 0 r/w 5 icice 0 r/w 4 icide 0 r/w 3 ociae 0 r/w 0 1 2 ocibe 0 r/w 1 ovie 0 r/w timer overflow interrupt enable 0 1 timer overflow interrupt request is disabled. timer overflow interrupt request is enabled. output compare interrupt b enable 0 1 output compare interrupt request b is disabled. output compare interrupt request b is enabled. output compare interrupt a enable 0 1 output compare interrupt request a is disabled. output compare interrupt request a is enabled. input capture interrupt d enable 0 1 input capture interrupt request d is disabled. input capture interrupt request d is enabled. input capture interrupt c enable 0 1 input capture interrupt request c is disabled. input capture interrupt request c is enabled. input capture interrupt b enable 0 1 input capture interrupt request b is disabled. input capture interrupt request b is enabled. input capture interrupt a enable 0 1 input capture interrupt request a is disabled. input capture interrupt request a is enabled. 636 tcsr?imer control/status register h'91 frt bit initial value read/write 7 icfa 0 r/(w) 6 icfb 0 r/(w) 5 icfc 0 r/(w) 4 icfd 0 r/(w) 3 ocfa 0 r/(w) 0 cclra 0 r/w 2 ocfb 0 r/(w) 1 ovf 0 r/(w) counter clear a 0 1 frc count is not cleared. frc count is cleared by compare-match a. timer overflow flag output compare flag b 0 1 cleared by reading ocfb = 1, then writing 0 in ocfb. set when frc = ocrb. output compare flag a 0 1 cleared by reading ocfa = 1, then writing 0 in ocfa. set when frc = ocra. input capture flag d 0 1 cleared by reading icfd = 1, then writing 0 in icfd. set when an input capture signal is received. input capture flag c 0 1 cleared by reading icfc = 1, then writing 0 in icfc. set when an input capture signal is received. input capture flag b 0 1 cleared by reading icfb = 1, then writing 0 in icfb. set when ftib input causes frc to be copied to icrb. input capture flag a 0 1 cleared by reading icfa = 1, then writing 0 in icfa. set when ftia input causes frc to be copied to icra. ***** note: * software can write a 0 in bits 7 to 1 to clear the flags, but cannot write a 1 in these bits. 0 1 cleared by reading ovf = 1, then writing 0 in ovf. set when frc changes from h'ffff to h'0000. * * 637 frc (h and l)?ree-running counter h'92, h'93 frt bit initial value read/write 15 0 r/w 14 0 r/w 13 0 r/w 12 0 r/w 11 0 r/w 10 0 r/w 9 0 r/w 8 0 r/w 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 2 0 r/w 1 0 r/w 0 0 r/w count value ocra (h and l)?utput compare register a h'94, h'95 frt continually compared with frc. ocfa is set to 1 when ocra = frc. bit initial value read/write 15 1 r/w 14 1 r/w 13 1 r/w 12 1 r/w 11 1 r/w 10 1 r/w 9 1 r/w 8 1 r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 1 r/w ocrb (h and l)?utput compare register b h'94, h'95 frt continually compared with frc. ocfb is set to 1 when ocrb = frc. bit initial value read/write 15 1 r/w 14 1 r/w 13 1 r/w 12 1 r/w 11 1 r/w 10 1 r/w 9 1 r/w 8 1 r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 1 r/w 638 tcr?imer control register h'96 frt bit initial value read/write 7 iedga 0 r/w 6 iedgb 0 r/w 5 iedgc 0 r/w 4 iedgd 0 r/w 3 bufea 0 r/w 0 cks0 0 r/w 2 bufeb 0 r/w 1 cks1 0 r/w clock select 0 0 1 1 0 1 0 1 internal clock source: p /2 internal clock source: p /8 internal clock source: p /32 external clock source: counted on rising edge buffer enable b 0 1 icrd is used for input capture d. icrd is buffer register for input capture b. buffer enable a 0 1 icrc is used for input capture c. icrc is buffer register for input capture a. input edge select d 0 1 falling edge of ftid is valid. rising edge of ftid is valid. input edge select c input edge select b 0 1 falling edge of ftib is valid. rising edge of ftib is valid. input edge select a 0 1 falling edge of ftia is valid. rising edge of ftia is valid. 0 1 falling edge of ftic is valid. rising edge of ftic is valid. 639 tocr?imer output compare control register h'97 frt bit initial value read/write 7 1 6 1 5 1 4 ocrs 0 r/w 3 oea 0 r/w 0 olvlb 0 r/w 2 oeb 0 r/w 1 olvla 0 r/w output level b 0 1 compare-match b causes 0 output. compare-match b causes 1 output. output level a 0 1 compare-match a causes 0 output. compare-match a causes 1 output. output enable b 0 1 output compare b output is disabled. output compare b output is enabled. output enable a output compare register select 0 1 ocra is selected. ocrb is selected. 0 1 output compare a output is disabled. output compare a output is enabled. icra (h and l)?nput capture register a h'98, h'99 frt bit initial value read/write 14 0 r 12 0 r 10 0 r 8 0 r 6 0 r 0 0 r 4 0 r 2 0 r contains frc count captured on ftia input. 13 0 r 11 0 r 9 0 r 7 0 r 5 0 r 3 0 r 1 0 r 15 0 r 640 icrb (h and l)?nput capture register b h'9a, h'9b frt bit initial value read/write 14 0 r 12 0 r 10 0 r 8 0 r 6 0 r 0 0 r 4 0 r 2 0 r contains frc count captured on ftib input. 13 0 r 11 0 r 9 0 r 7 0 r 5 0 r 3 0 r 1 0 r 15 0 r icrc (h and l)?nput capture register c h'9c, h'9d frt bit initial value read/write 14 0 r 12 0 r 10 0 r 8 0 r 6 0 r 0 0 r 4 0 r 2 0 r contains frc count captured on ftic input, or old icra value in buffer mode. 13 0 r 11 0 r 9 0 r 7 0 r 5 0 r 3 0 r 1 0 r 15 0 r icrd (h and l)?nput capture register d h'9e, h'9f frt bit initial value read/write 14 0 r 12 0 r 10 0 r 8 0 r 6 0 r 0 0 r 4 0 r 2 0 r contains frc count captured on ftid input, or old icrb value in buffer mode. 13 0 r 11 0 r 9 0 r 7 0 r 5 0 r 3 0 r 1 0 r 15 0 r 641 tcr?imer control register h'a0 pwm0 bit initial value read/write 7 oe 0 r/w 6 os 0 r/w 5 1 4 1 3 1 0 cks0 0 r/w 2 cks2 0 r/w 1 cks1 0 r/w clock select (values when p = 10 mhz) 0 1 p /2 p /8 p /32 p /128 p /256 p /1024 p /2048 p /4096 output enable 0 1 pwm output disabled; tcnt cleared to h'00 and stops. pwm output enabled; tcnt runs. 0 1 0 1 0 1 0 1 0 1 0 1 resolution internal clock freq. pwm period pwm frequency 200 ns 800 ns 3.2 s 12.8 s 25.6 s 102.4 s 204.8 s 409.6 s 50 s 200 s 800 s 3.2 ms 6.4 ms 25.6 ms 51.2 ms 102.4 ms 20 khz 5 khz 1.25 khz 312.5 hz 156.3 hz 39.1 hz 19.5 hz 9.8 hz output select 0 1 pwm direct output pwm inverse output dtr?uty register h'a1 pwm0 bit initial value read/write 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w pulse duty cycle 642 tcnt?imer counter h'a2 pwm0 bit initial value read/write 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w count value (runs from h'00 to h'f9, then repeats from h'00) tcr?imer control register h'a4 pwm1 bit initial value read/write 7 oe 0 r/w 6 os 0 r/w 5 1 4 1 3 1 0 cks0 0 r/w 2 cks2 0 r/w 1 cks1 0 r/w note: bit functions are the same as for pwm0. dtr?uty register h'a5 pwm1 bit initial value read/write 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w note: bit functions are the same as for pwm0. tcnt?imer counter h'a6 pwm1 bit initial value read/write 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w note: bit functions are the same as for pwm0. 643 tcsr?imer control/status register h'a8 wdt bit initial value read/write 7 ovf 0 r/(w) * 6 wt/it 0 r/w 5 tme 0 r/w 4 1 3 rst/nmi 0 r/w 0 cks0 0 r/w 2 cks2 0 r/w 1 cks1 0 r/w clock select 2 to 0 0 1 timer enable 0 1 timer disabled: tcnt is initialized to h 00 and stopped timer enabled: tcnt runs; cpu interrupts can be requested timer mode select 0 1 interval timer mode (ovf interrupt request) (initial value) watchdog timer mode (generates reset or nmi signal) overflow flag 0 1 cleared by reading ovf = 1, then writing 0 in ovf (initial value) set when tcnt changes from h'ff to h'00 note: * only 0 can be written, to clear the flag. 0 1 0 1 p /2 p /32 p /64 p /128 p /256 p /512 p /2048 p /4096 0 1 0 1 0 1 0 1 reset or nmi 0 1 functions as nmi (initial value) functions as reset (initial value) 644 tcnt?imer counter h'a9 (read), h'a8 (write) wdt bit initial value read/write 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w count value p1pcr?ort 1 input pull-up control register h'ac port 1 bit initial value read/write 7 p1 7 pcr 0 r/w 6 p1 6 pcr 0 r/w 5 p1 5 pcr 0 r/w 4 p1 4 pcr 0 r/w 3 p1 3 pcr 0 r/w 0 p1 0 pcr 0 r/w 2 p1 2 pcr 0 r/w 1 p1 1 pcr 0 r/w port 1 input pull-up control 0 1 input pull-up transistor is off. input pull-up transistor is on. p2pcr?ort 2 input pull-up control register h'ad port 2 bit initial value read/write 7 p2 7 pcr 0 r/w 6 p2 6 pcr 0 r/w 5 p2 5 pcr 0 r/w 4 p2 4 pcr 0 r/w 3 p2 3 pcr 0 r/w 0 p2 0 pcr 0 r/w 2 p2 2 pcr 0 r/w 1 p2 1 pcr 0 r/w port 2 input pull-up control 0 1 input pull-up transistor is off. input pull-up transistor is on. 645 p3pcr?ort 3 input pull-up control register h'ae port 3 bit initial value read/write 7 p3 7 pcr 0 r/w 6 p3 6 pcr 0 r/w 5 p3 5 pcr 0 r/w 4 p3 4 pcr 0 r/w 3 p3 3 pcr 0 r/w 0 p3 0 pcr 0 r/w 2 p3 2 pcr 0 r/w 1 p3 1 pcr 0 r/w port 3 input pull-up control 0 1 input pull-up transistor is off. input pull-up transistor is on. p1ddr?ort 1 data direction register h'b0 port 1 bit mode 1 initial value read/write modes 2 and 3 initial value read/write 7 p1 7 ddr 1 0 w 6 p1 6 ddr 1 0 w 5 p1 5 ddr 1 0 w 4 p1 4 ddr 1 0 w 3 p1 3 ddr 1 0 w 0 p1 0 ddr 1 0 w 2 p1 2 ddr 1 0 w 1 p1 1 ddr 1 0 w port 1 input/output control 0 1 input port output port p1dr?ort 1 data register h'b2 port 1 bit initial value read/write 7 p1 7 0 r/w 6 p1 6 0 r/w 5 p1 5 0 r/w 4 p1 4 0 r/w 3 p1 3 0 r/w 0 p1 0 0 r/w 2 p1 2 0 r/w 1 p1 1 0 r/w 646 p2ddr?ort 2 data direction register h'b1 port 2 bit mode 1 initial value read/write modes 2 and 3 initial value read/write 7 p2 7 ddr 1 0 w 6 p2 6 ddr 1 0 w 5 p2 5 ddr 1 0 w 4 p2 4 ddr 1 0 w 3 p2 3 ddr 1 0 w 0 p2 0 ddr 1 0 w 2 p2 2 ddr 1 0 w 1 p2 1 ddr 1 0 w port 2 input/output control 0 1 input port output port p2dr?ort 2 data register h'b3 port 2 bit initial value read/write 7 p2 7 0 r/w 6 p2 6 0 r/w 5 p2 5 0 r/w 4 p2 4 0 r/w 3 p2 3 0 r/w 0 p2 0 0 r/w 2 p2 2 0 r/w 1 p2 1 0 r/w p3ddr?ort 3 data direction register h'b4 port 3 bit initial value read/write 7 p3 7 ddr 0 w 6 p3 6 ddr 0 w 5 p3 5 ddr 0 w 4 p3 4 ddr 0 w 3 p3 3 ddr 0 w 0 p3 0 ddr 0 w 2 p3 2 ddr 0 w 1 p3 1 ddr 0 w port 3 input/output control 0 1 input port output port 647 p3dr?ort 3 data register h'b6 port 3 bit initial value read/write 7 p3 7 0 r/w 6 p3 6 0 r/w 5 p3 5 0 r/w 4 p3 4 0 r/w 3 p3 3 0 r/w 0 p3 0 0 r/w 2 p3 2 0 r/w 1 p3 1 0 r/w p4ddr?ort 4 data direction register h'b5 port 4 bit initial value read/write 7 p4 7 ddr 0 w 6 p4 6 ddr 0 w 5 p4 5 ddr 0 w 4 p4 4 ddr 0 w 3 p4 3 ddr 0 w 0 p4 0 ddr 0 w 2 p4 2 ddr 0 w 1 p4 1 ddr 0 w port 4 input/output control 0 1 input port output port p4dr?ort 4 data register h'b7 port 4 bit initial value read/write 7 p4 7 0 r/w 6 p4 6 0 r/w 5 p4 5 0 r/w 4 p4 4 0 r/w 3 p4 3 0 r/w 0 p4 0 0 r/w 2 p4 2 0 r/w 1 p4 1 0 r/w p5ddr?ort 5 data direction register h'b8 port 5 bit initial value read/write 7 1 6 1 5 1 4 1 3 1 0 p5 0 ddr 0 w 2 p5 2 ddr 0 w 1 p5 1 ddr 0 w port 5 input/output control 0 1 input port output port 648 p5dr?ort 5 data register h'ba port 5 bit initial value read/write 7 1 6 1 5 1 4 1 3 1 0 p5 0 0 r/w 2 p5 2 0 r/w 1 p5 1 0 r/w p6ddr?ort 6 data direction register h'b9 port 6 bit initial value read/write 7 p6 7 ddr 0 w 6 p6 6 ddr 0 w 5 p6 5 ddr 0 w 4 p6 4 ddr 0 w 3 p6 3 ddr 0 w 0 p6 0 ddr 0 w 2 p6 2 ddr 0 w 1 p6 1 ddr 0 w port 6 input/output control 0 1 input port output port p6dr?ort 6 data register h'bb port 6 bit initial value read/write 7 p6 7 0 r/w 6 p6 6 0 r/w 5 p6 5 0 r/w 4 p6 4 0 r/w 3 p6 3 0 r/w 0 p6 0 0 r/w 2 p6 2 0 r/w 1 p6 1 0 r/w p7pin?ort 7 input data register h'be port 7 bit initial value read/write 7 p7 7 ? r 6 p7 6 ? r 5 p7 5 ? r 4 p7 4 ? r 3 p7 3 ? r 0 p7 0 ? r 2 p7 2 ? r 1 p7 1 ? r note: depends on the levels of pins p7 7 to p7 0 . * 649 p8ddr?ort 8 data direction register h'bd port 8 bit initial value read/write 7 1 6 p8 6 ddr 0 w 5 p8 5 ddr 0 w 4 p8 4 ddr 0 w 3 p8 3 ddr 0 w 0 p8 0 ddr 0 w 2 p8 2 ddr 0 w 1 p8 1 ddr 0 w port 8 input/output control 0 1 input port output port p8dr?ort 8 data register h'bf port 8 bit initial value read/write 7 1 6 p8 6 0 r/w 5 p8 5 0 r/w 4 p8 4 0 r/w 3 p8 3 0 r/w 0 p8 0 0 r/w 2 p8 2 0 r/w 1 p8 1 0 r/w p9ddr?ort 9 data direction register h'c0 port 9 bit modes 1 and 2 initial value read/write mode 3 initial value read/write 7 p9 7 ddr 0 w 0 w 6 p9 6 ddr 1 0 w 5 p9 5 ddr 0 w 0 w 4 p9 4 ddr 0 w 0 w 3 p9 3 ddr 0 w 0 w 0 p9 0 ddr 0 w 0 w 2 p9 2 ddr 0 w 0 w 1 p9 1 ddr 0 w 0 w port 9 input/output control 0 1 input port output port 650 p9dr?ort 9 data register h'c1 port 9 bit initial value read/write 7 p9 7 0 r/w 6 p9 6 * r 5 p9 5 0 r/w 4 p9 4 0 r/w 3 p9 3 0 r/w 0 p9 0 0 r/w 2 p9 2 0 r/w 1 p9 1 0 r/w note: depends on the level of pin p9 6 . * 651 wscr?ait-state control register h'c2 system control bit initial value read/write 7 rams 0 r/w 6 ram0 0 r/w 5 ckdbl 0 r/w 4 flshe 0 r/w 3 wms1 1 r/w 0 wc0 0 r/w 2 wms0 0 r/w 1 wc1 0 r/w wait count 0 0 1 1 0 1 0 1 no wait states inserted by wait-state controller (initial value) 1 state inserted 2 states inserted 3 states inserted wait mode select clock double ram select and ram 0 h8/3334yf (dual-power-supply flash memory only) 0 1 supporting module clock frequency is not divided ( p = ) (initial value) supporting module clock frequency is divided by two ( p = /2) note: in the h8/3397 series, do not write 1 to bits rams and ram0. flash memory control register enable h8/3337sf (single-power-supply flash memory only) 0 1 flash memory control registers are in unselected state (initial value) flash memory control registers are in selected state 0 0 1 1 0 1 0 1 programmable wait mode no wait states inserted by wait-state controller pin wait mode pin auto-wait mode none h'fc80 to h'fcff h'fc80 to h'fd7f h'fc00 to h'fc7f ram area rom area rams, ram0 h'0080 to h'00ff h'0080 to h'017f h'0000 to h'007f 0 0 1 1 0 1 0 1 (initial value) ram select and ram 0 h8/3337yf none h'f880 to h'f8ff h'f880 to h'f97f h'f800 to h'f87f ram area rom area rams, ram0 h'0080 to h'00ff h'0080 to h'017f h'0000 to h'007f 0 0 1 1 0 1 0 1 652 stcr?erial/timer control register h'c3 system control bit initial value read/write 7 iics 0 r/w 6 iicd 0 r/w 5 iicx 0 r/w 4 iice 0 r/w 3 stac 0 r/w 0 icks0 0 r/w 2 mpe 0 r/w 1 icks1 0 r/w internal clock source select see tcr under tmr0 and tmr1. multiprocessor enable 0 1 multiprocessor communication function is disabled. multiprocessor communication function is enabled. slave mode control input switch 0 1 cs 2 and iow are enabled ecs 2 and eiow are enabled i 2 c master enable 0 1 i 2 c bus interface data registers and control registers are disabled (initial value) i 2 c bus interface data registers and control registers are enabled i 2 c transfer rate select i 2 c extra buffer reserve i 2 c extra buffer select 0 1 pa 7 to pa 4 are normal input/output pins pa 7 to pa 4 are selected for bus drive iicx cks2 * 2 cks1 * 2 cks0 * 2 clock transfer rate * 1 notes: * 1 p = . * 2 cks2 to cks0 are bits 2 to 0 of the i 2 c bus control register in the i 2 c bus interface. 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 p /28 p /40 p /48 p /64 p /80 p /100 p /112 p /128 p /56 p /80 p /96 p /128 p /160 p /200 p /224 p /256 143 khz 100 khz 83.3 khz 62.5 khz 50.0 khz 40.0 khz 35.7 khz 31.3 khz 71.4 khz 50.0 khz 41.7 khz 31.3 khz 25.0 khz 20.0 khz 17.9 khz 15.6 khz p = 4 mhz p = 5 mhz p = 8 mhz p = 10 mhz p = 16 mhz 179 khz 125 khz 104 khz 78.1 khz 62.5 khz 50.0 khz 44.6 khz 39.1 khz 89.3 khz 62.5 khz 52.1 khz 39.1 khz 31.3 khz 25.0 khz 22.3 khz 19.5 khz 286 khz 200 khz 167 khz 125 khz 100 khz 80.0 khz 71.4 khz 62.5 khz 143 khz 100 khz 83.3 khz 62.5 khz 50.0 khz 40.0 khz 35.7 khz 31.3 khz 357 khz 250 khz 208 khz 156 khz 125 khz 100 khz 89.3 khz 78.1 khz 179 khz 125 khz 104 khz 78.1 khz 62.5 khz 50.0 khz 44.6 khz 39.1 khz 571 khz 400 khz 333 khz 250 khz 200 khz 160 khz 143 khz 125 khz 286 khz 200 khz 167 khz 125 khz 100 khz 80.0 khz 71.4 khz 62.5 khz 653 syscr?ystem control register h'c4 system control bit initial value read/write 7 ssby 0 r/w 6 sts2 0 r/w 5 sts1 0 r/w 4 sts0 0 r/w 3 xrst 1 r 0 rame 1 r/w 2 nmieg 0 r/w 1 hie 0 r/w ram enable 0 1 on-chip ram is disabled. on-chip ram is enabled. (initial value) standby timer select 2 to 0 (ztat and mask rom versions) 0 0 0 0 1 1 clock settling time = 8,192 states (initial value) clock settling time = 16,384 states clock settling time = 32,768 states clock settling time = 65,536 states clock settling time = 131,072 states unused software standby 0 1 sleep instruction causes transition to sleep mode. (initial value) sleep instruction causes transition to software standby mode. 0 0 1 1 0 1 0 1 0 1 host interface enable 0 1 host interface is prohibited (initial value) host interface is allowed (slave mode) nmi edge 0 1 falling edge of nmi is detected. rising edge of nmi is detected. external reset 0 1 reset was caused by watchdog timer overflow reset was caused by external reset signal (initial value) standby timer select 2 to 0 (f-ztat version) 0 0 0 0 1 1 1 settling time = 8,192 states (initial value) settling time = 16,384 states settling time = 32,768 states settling time = 65,536 states settling time = 131,072 states settling time = 1,024 states unused 0 0 1 1 0 0 1 0 1 0 1 0 1 654 mdcr?ode control register h'c5 system control ? except h8/3337sf bit initial value read/write 7 1 6 1 5 1 4 0 3 0 0 mds0 * r 2 1 1 mds1 * r mode select bits value at mode pins. note: determined by inputs at pins md 1 and md 0 . * ? h8/3337sf bit initial value read/write 7 expe * r/w * 6 1 5 1 4 0 3 0 0 mds0 * r 2 1 1 mds1 * r mode select bits value at mode pins. expanded mode enable 0 1 single-chip mode is selected. expanded mode is selected (writable in boot mode only). note: determined by inputs at pins md 1 and md 0 . * 655 iscr?rq sense control register h'c6 system control bit initial value read/write 7 irq7sc 0 r/w 6 irq6sc 0 r/w 5 irq5sc 0 r/w 4 irq4sc 0 r/w 3 irq3sc 0 r/w 0 irq0sc 0 r/w 2 irq2sc 0 r/w 1 irq1sc 0 r/w irq 0 to irq 7 sense control 0 1 irq 0 to irq 7 are level-sensed (active low). irq 0 to irq 7 are edge-sensed (falling edge). ier?rq enable register h'c7 system control bit initial value read/write 7 irq7e 0 r/w 6 irq6e 0 r/w 5 irq5e 0 r/w 4 irq4e 0 r/w 3 irq3e 0 r/w 0 irq0e 0 r/w 2 irq2e 0 r/w 1 irq1e 0 r/w irq0 to irq7 enable 0 1 irq 0 to irq 7 are disabled. irq 0 to irq 7 are enabled. 656 tcr?imer control register h'c8 tmr0 bit initial value read/write 7 cmieb 0 r/w 6 cmiea 0 r/w 5 ovie 0 r/w 4 cclr1 0 r/w 3 cclr0 0 r/w 0 cks0 0 r/w 2 cks2 0 r/w 1 cks1 0 r/w clock select cks2 0 0 0 0 0 0 0 1 1 1 1 timer stopped (initial value) p /8 internal clock, falling edge p /2 internal clock, falling edge p /64 internal clock, falling edge p /32 internal clock, falling edge p /1024 internal clock, falling edge p /256 internal clock, falling edge timer stopped external clock, rising edge external clock, falling edge external clock, rising and falling edges counter clear 0 0 1 1 counter is not cleared. cleared by compare-match a. cleared by compare-match b. cleared on rising edge of external reset input. timer overflow interrupt enable compare-match interrupt enable a 0 1 compare-match a interrupt request is disabled. compare-match a interrupt request is enabled. compare-match interrupt enable b 0 1 compare-match b interrupt request is disabled. compare-match b interrupt request is enabled. 0 1 timer overflow interrupt request is disabled. timer overflow interrupt request is enabled. 0 1 0 1 cks1 0 0 0 1 1 1 1 0 0 1 1 cks0 0 1 1 0 0 1 1 0 1 0 1 icks1 icks0 0 1 0 1 0 1 tcr stcr description bit 2 bit 1 bit 0 bit 1 bit 0 657 tcsr?imer control/status register h'c9 tmr0 bit initial value read/write 7 cmfb 0 r/(w) 6 cmfa 0 r/(w) 5 ovf 0 r/(w) 4 1 3 os3 0 r/w 0 os0 0 r/w 2 os2 0 r/w 1 os1 0 r/w output select 0 0 1 1 no change on compare-match a. output 0 on compare-match a. output 1 on compare-match a. invert (toggle) output on compare-match a. output select 0 0 1 1 no change on compare-match b. output 0 on compare-match b. output 1 on compare-match b. invert (toggle) output on compare-match b. timer overflow flag 0 1 cleared by reading ovf = 1, then writing 0 in ovf. set when tcnt changes from h'ff to h'00. compare-match flag a 0 1 cleared by reading cmfa = 1, then writing 0 in cmfa. set when tcnt = tcora. compare-match flag b 0 1 cleared by reading cmfb = 1, then writing 0 in cmfb. set when tcnt = tcorb. when all four bits (os3 to os0) are cleared to 0, output is disabled. software can write a 0 in bits 7 to 5 to clear the fla g s, but cannot write a 1 in these bits. notes: * 1 * 2 * 2 * 2 * 2 * 1 * 1 * 1 * 1 0 1 0 1 0 1 0 1 658 tcora?ime constant register a h'ca tmr0 bit initial value read/write 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w the cmfa bit is set to 1 when tcora = tcnt. tcorb?ime constant register b h'cb tmr0 bit initial value read/write 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w the cmfb bit is set to 1 when tcorb = tcnt. tcnt?imer counter h'cc tmr0 bit initial value read/write 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w count value 659 tcr?imer control register h'd0 tmr1 bit initial value read/write 7 cmieb 0 r/w 6 cmiea 0 r/w 5 ovie 0 r/w 4 cclr1 0 r/w 3 cclr0 0 r/w 0 cks0 0 r/w 2 cks2 0 r/w 1 cks1 0 r/w clock select cks2 0 0 0 0 0 0 0 1 1 1 1 timer stopped p /8 internal clock, falling edge p /2 internal clock, falling edge p /64 internal clock, falling edge p /128 internal clock, falling edge p /1024 internal clock, falling edge p /2048 internal clock, falling edge timer stopped external clock, rising edge external clock, falling edge external clock, rising and falling edges counter clear 0 0 1 1 counter is not cleared. cleared by compare-match a. cleared by compare-match b. cleared on rising edge of external reset input. timer overflow interrupt enable compare-match interrupt enable a 0 1 compare-match a interrupt request is disabled. compare-match a interrupt request is enabled. compare-match interrupt enable b 0 1 compare-match b interrupt request is disabled. compare-match b interrupt request is enabled. 0 1 timer overflow interrupt request is disabled. timer overflow interrupt request is enabled. 0 1 0 1 cks1 0 0 0 1 1 1 1 0 0 1 1 cks0 0 1 1 0 0 1 1 0 1 0 1 icks1 0 1 0 1 0 1 icks0 tcr stcr description bit 2 bit 1 bit 0 bit 1 bit 0 660 tcsr?imer control/status register h'd1 tmr1 bit initial value read/write 7 cmfb 0 r/(w) 6 cmfa 0 r/(w) 5 ovf 0 r/(w) 4 1 3 os3 0 r/w 0 os0 0 r/w 2 os2 0 r/w 1 os1 0 r/w * 2 * 2 * 2 * 1 * 1 * 1 * 1 bit functions are the same as for tmr0. * 1 when all four bits (os3 to os0) are cleared to 0, output is disabled. * 2 software can write a 0 in bits 7 to 5 to clear the flags, but cannot write a 1 in these bits. notes: tcora?ime constant register a h'd2 tmr1 bit initial value read/write note: bit functions are the same as for tmr0. 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w tcorb?ime constant register b h'd3 tmr1 bit initial value read/write note: bit functions are the same as for tmr0. 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w tcnt?imer counter h'd4 tmr1 bit initial value read/write note: bit functions are the same as for tmr0. 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w 661 iccr? 2 c bus control register h'd8 i 2 c bit initial value read/write 7 ice 0 r/w 6 ieic 0 r/w 5 mst 0 r/w 4 trs 0 r/w 3 ack 0 r/w 0 cks0 0 r/w 2 cks2 0 r/w 1 cks1 0 r/w transfer clock select acknowledgement mode select 0 1 acknowledgement mode serial mode master/slave select and transmit/receive select 0 1 slave receive mode slave transmit mode master receive mode master transmit mode 0 1 0 1 i 2 c bus interface interrupt enable 0 1 interrupts disabled interrupts enabled i 2 c bus interface enable 0 1 interface module disabled, with pins scl and sda operating as ports interface module enabled for transfer operations, with pins scl and sda capable of bus drive iicx * cks2 cks1 cks0 clock transfer rate note: the shaded setting exceeds the maximum transfer rate in the standard i 2 c bus specifications. p = . * iicx is bit 5 of the serial timer control register (stcr). 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 p /28 p /40 p /48 p /64 p /80 p /100 p /112 p /128 p /56 p /80 p /96 p /128 p /160 p /200 p /224 p /256 143 khz 100 khz 83.3 khz 62.5 khz 50.0 khz 40.0 khz 35.7 khz 31.3 khz 71.4 khz 50.0 khz 41.7 khz 31.3 khz 25.0 khz 20.0 khz 17.9 khz 15.6 khz p = 4 mhz p = 5 mhz p = 8 mhz p = 10 mhz p = 16 mhz 179 khz 125 khz 104 khz 78.1 khz 62.5 khz 50.0 khz 44.6 khz 39.1 khz 89.3 khz 62.5 khz 52.1 khz 39.1 khz 31.3 khz 25.0 khz 22.3 khz 19.5 khz 286 khz 200 khz 167 khz 125 khz 100 khz 80.0 khz 71.4 khz 62.5 khz 143 khz 100 khz 83.3 khz 62.5 khz 50.0 khz 40.0 khz 35.7 khz 31.3 khz 357 khz 250 khz 208 khz 156 khz 125 khz 100 khz 89.3 khz 78.1 khz 179 khz 125 khz 104 khz 78.1 khz 62.5 khz 50.0 khz 44.6 khz 39.1 khz 571 khz 400 khz 333 khz 250 khz 200 khz 160 khz 143 khz 125 khz 286 khz 200 khz 167 khz 125 khz 100 khz 80.0 khz 71.4 khz 62.5 khz 662 icsr? 2 c bus status register h'd9 i 2 c bit initial value read/write 7 bbsy 0 r/w 6 iric 0 r/(w) * 5 scp 1 w 4 1 3 al 0 r/(w) * 0 ackb 0 r/w 2 aas 0 r/(w) * 1 adz 0 r/(w) * acknowledge bit 0 1 receive mode: 0 is output at acknowledge output timing transmit mode: indicates that the receiving device has acknowledged the data receive mode: 1 is output at acknowledge output timing transmit mode: indicates that the receiving device has not acknowledged the data general call address recognition flag 0 1 general call address not recognized cleared when icdr data is written (transmit mode) or read (receive mode) cleared by reading adz = 1, then writing 0 general call address recognized set when the general call address is detected in slave receive mode slave address recognition flag 0 1 slave address or general call address not recognized (initial value) cleared when icdr data is written (transmit mode) or read (receive mode) cleared by reading aas = 1, then writing 0 slave address or general call address recognized set when the slave address or general call address is detected in slave receive mode arbitration lost flag 0 1 bus arbitration won cleared when icdr data is written (transmit mode) or read (receive mode) cleared by reading al = 1, then writing 0 arbitration lost set if the internal sda and bus line disagree at the rise of scl in master transmit mode set if the internal scl is high at the fall of scl in master transmit mode start condition/stop condition prohibit 0 1 writing 0 issues a start or stop condition, in combination with bbsy reading always results in 1 writing is ignored i 2 c bus interface interrupt request flag 0 1 waiting for transfer, or transfer in progress cleared by reading iric = 1, then writing 0 interrupt requested set to 1 at the following times: master mode end of data transfer bus arbitration lost slave mode (when fs = 0) when the slave address is matched, and whenever a data transfer ends after that, until a retransmit start condition or a stop condition is detected when a general call address is detected, and whenever a data transfer ends after that, until a retransmit start condition or a stop condition is detected slave mode (when fs = 1) end of data transfer bus busy 0 1 bus is free cleared by detection of a stop condition bus is busy set by detection of a start condition note: * only 0 can be written, to clear the flag. 663 smr?erial mode register h'd8 sci0 bit initial value read/write 7 c/a 0 r/w 6 chr 0 r/w 5 pe 0 r/w 4 o/e 0 r/w 3 stop 0 r/w 0 cks0 0 r/w 2 mp 0 r/w 1 cks1 0 r/w clock select 0 0 1 1 0 1 0 1 clock p /4 clock p /16 clock p /64 clock multiprocessor mode 0 1 multiprocessor function disabled multiprocessor format selected stop bit length 0 1 one stop bit two stop bits parity mode 0 1 even parity odd parity parity enable 0 transmit: receive: character length 0 1 8-bit data length 7-bit data length communication mode 0 1 asynchronous synchronous transmit: receive: 1 no parity bit added. parity bit not checked. parity bit added. parity bit checked. note: bit functions are the same as for sci1. 664 brr?it rate register h'd9 sci0 bit initial value read/write 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w note: bit functions are the same as for sci1. 665 scr?erial control register h'da sci0 bit initial value read/write 7 tie 0 r/w 6 rie 0 r/w 5 te 0 r/w 4 re 0 r/w 3 mpie 0 r/w 0 cke0 0 r/w 2 teie 0 r/w 1 cke1 0 r/w clock enable 0 0 1 sck pin not used sck pin used for serial clock output. clock enable 1 0 1 internal clock external clock transmit end interrupt enable 0 1 tsr-empty interrupt request is disabled. tsr-empty interrupt request is enabled. multiprocessor interrupt enable 0 1 multiprocessor receive interrupt function is disabled. multiprocessor receive interrupt function is enabled. receive enable 0 1 receive disabled receive enabled transmit enable 0 1 transmit disabled transmit enabled receive interrupt enable 0 1 receive end interrupt and receive error requests are disabled. receive end interrupt and receive error requests are enabled. transmit interrupt enable 0 1 tdr-empty interrupt request is disabled. tdr-empty interrupt request is enabled. note: bit functions are the same as for sci1. 666 tdr?ransmit data register h'db sci0 bit initial value read/write 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w note: bit functions are the same as for sci1. 667 ssr?erial status register h'dc sci0 bit initial value read/write 7 tdre 1 r/(w) 6 rdrf 0 r/(w) 5 orer 0 r/(w) 4 fer 0 r/(w) 3 per 0 r/(w) 0 mpbt 0 r/w 2 tend 1 r 1 mpb 0 r multiprocessor bit transfer 0 1 multiprocessor bit = 0 in transmit data. (initial value) multiprocessor bit = 1 in transmit data. multiprocessor bit transmit end 0 1 cleared by reading tdre = 1, then writing 0 in tdre. set to 1 when te = 0, or when tdre = 1 at the end of character transmission. (initial value) parity error 0 1 cleared by reading per = 1, then writing 0 in per. (initial value) set when a parity error occurs (parity of receive data does not match parity selected by o/e bit in smr). framing error 0 1 cleared by reading fer = 1, then writing 0 in fer. (initial value) set when a framing error occurs (stop bit is 0). overrun error 0 1 cleared by reading orer = 1, then writing 0 in orer. (initial value) set when an overrun error occurs (next data is completely received while rdrf bit is set to 1). receive data register full 0 1 cleared by reading rdrf = 1, then writing 0 in rdrf. (initial value) set when one character is received normally and transferred from rsr to rdr. transmit data register empty 0 1 cleared by reading tdre = 1, then writing 0 in tdre. set when: (initial value) 1. data is transferred from tdr to tsr. 2. te is cleared to 0 while tdre = 0. ***** 0 1 multiprocessor bit = 0 in receive data. (initial value) multiprocessor bit = 1 in receive data. software can write a 0 in bits 7 to 3 to clear the flags, but cannot write a 1 in these bits. bit functions are the same as for sci1. note: * 668 rdr?eceive data register h'dd sci0 bit initial value read/write note: bit functions are the same as for sci1. 7 0 r 6 0 r 5 0 r 4 0 r 3 0 r 0 0 r 2 0 r 1 0 r receive data icdr? 2 c bus data register h'de i 2 c bit initial value read/write 7 icdr7 r/w 6 icdr6 r/w 5 icdr5 r/w 4 icdr4 r/w 3 icdr3 r/w 0 icdr0 r/w 2 icdr2 r/w 1 icdr1 r/w transmit/receive data sar?lave address register h'df i 2 c bit initial value read/write 7 sva6 0 r/w 6 sva5 0 r/w 5 sva4 0 r/w 4 sva3 0 r/w 3 sva2 0 r/w 0 fs 0 r/w 2 sva1 0 r/w 1 sva0 0 r/w slave address format select 0 1 addressing format, slave address recognized non-addressing format 669 icmr? 2 c bus mode register h'df i 2 c bit initial value read/write 7 mls 0 r/w 6 wait 0 r/w 5 1 4 1 3 1 0 bc0 0 r/w 2 bc2 0 r/w 1 bc1 0 r/w bit counter bc0 serial mode 8 1 2 3 4 5 6 7 wait insertion bit 0 1 data and acknowledge transferred consecutively wait inserted between data and acknowledge bc1 bc2 0 1 0 1 0 1 bits/frame 0 1 0 1 0 1 0 1 acknowledgement mode 9 2 3 4 5 6 7 8 msb-first/lsb-first 0 1 msb-first lsb-first 670 addra (h and l)?/d data register a h'e0, h'e1 a/d bit initial value read/write 14 ad8 0 r 12 ad6 0 r 10 ad4 0 r 8 ad2 0 r 6 ad0 0 r 0 0 r 4 0 r 2 0 r a/d conversion data 10-bit data giving an a/d conversion result 15 ad9 0 r 13 ad7 0 r 11 ad5 0 r 9 ad3 0 r 7 ad1 0 r 1 0 r 5 0 r 3 0 r addra h addra l reserved bits addrb (h and l)?/d data register b h'e2, h'e3 a/d bit initial value read/write 14 ad8 0 r 12 ad6 0 r 10 ad4 0 r 8 ad2 0 r 6 ad0 0 r 0 0 r 4 0 r 2 0 r a/d conversion data 10-bit data giving an a/d conversion result 15 ad9 0 r 13 ad7 0 r 11 ad5 0 r 9 ad3 0 r 7 ad1 0 r 1 0 r 5 0 r 3 0 r addrb h addrb l reserved bits 671 addrc (h and l)?/d data register c h'e4, h'e5 a/d bit initial value read/write 14 ad8 0 r 12 ad6 0 r 10 ad4 0 r 8 ad2 0 r 6 ad0 0 r 0 0 r 4 0 r 2 0 r a/d conversion data 10-bit data giving an a/d conversion result 15 ad9 0 r 13 ad7 0 r 11 ad5 0 r 9 ad3 0 r 7 ad1 0 r 1 0 r 5 0 r 3 0 r addrc h addrc l reserved bits addrd (h and l)?/d data register d h'e6, h'e7 a/d bit initial value read/write 14 ad8 0 r 12 ad6 0 r 10 ad4 0 r 8 ad2 0 r 6 ad0 0 r 0 0 r 4 0 r 2 0 r a/d conversion data 10-bit data giving an a/d conversion result 15 ad9 0 r 13 ad7 0 r 11 ad5 0 r 9 ad3 0 r 7 ad1 0 r 1 0 r 5 0 r 3 0 r addrd h addrd l reserved bits 672 adcsr?/d control/status register h'e8 a/d bit initial value read/write 7 adf 0 r/(w) 6 adie 0 r/w 5 adst 0 r/w 4 scan 0 r/w 3 cks 0 r/w 0 ch0 0 r/w 2 ch2 0 r/w 1 ch1 0 r/w channel select clock select 0 1 conversion time = 266 states (max) conversion time = 134 states (max) * note: * onl y 0 can be written, to clear the fla g . ch2 0 1 ch1 0 1 0 1 ch0 0 1 0 1 0 1 0 1 single mode an 0 an 1 an 2 an 3 an 4 an 5 an 6 an 7 scan mode an 0 an 0 , an 1 an 0 to an 2 an 0 to an 3 an 4 an 4 , an 5 an 4 to an 6 an 4 to an 7 scan mode 0 1 single mode scan mode a/d start 0 1 a/d conversion is halted. a/d interrupt enable 0 1 the a/d interrupt request (adi) is disabled. the a/d interrupt request (adi) is enabled. a/d end flag 0 1 cleared from 1 to 0 when cpu reads adf = 1, then writes 0 in adf. set to 1 at the following times: single mode: at the completion of a/d conversion scan mode: when all selected channels have been converted. single mode: one a/d conversion is performed, then this bit is automatically cleared to 0. scan mode: a/c conversion starts and continues cyclically on all selected channels until 0 is written in this bit. note: p = group selection channel selection description 673 adcr?/d control register h'e9 a/d trigger enable 0 1 adtrg is disabled. adtrg is enabled. a/d conversion can be started by external trigger, or by software. bit initial value read/write 7 trge 0 r/w 6 1 5 1 4 1 3 1 0 1 2 1 1 1 hicr?ost interface control register h'f0 hif bit initial value host read/write slave read/write 7 1 6 1 5 1 4 1 3 1 0 fga20e 0 r/w 2 ibfie2 0 r/w 1 ibfie1 0 r/w fast gate a20 enable 0 1 fast a20 gate function disabled fast a20 gate function enabled input buffer full interrupt enable 1 0 1 idr1 input buffer full interrupt disabled idr1 input buffer full interrupt enabled input buffer full interrupt enable 2 0 1 idr2 input buffer full interrupt disabled idr2 input buffer full interrupt enabled 674 kmimr?eyboard matrix interrupt mask register h'f1 system control bit initial value read/write 7 kmimr7 1 r/w 6 kmimr6 0 r/w 5 kmimr5 1 r/w 4 kmimr4 1 r/w 3 kmimr3 1 r/w 0 kmimr0 1 r/w 2 kmimr2 1 r/w 1 kmimr1 1 r/w keyboard matrix interrupt mask 0 1 key-sense input interrupt request enabled key-sense input interrupt request disabled (initial value) * note: * initial value of kmimr6 is 0. kmpcr?ort 6 input pull-up control register h'f2 port 6 bit initial value read/write 7 km 7 pcr 0 r/w 6 km 6 pcr 0 r/w 5 km 5 pcr 0 r/w 4 km 4 pcr 0 r/w 3 km 3 pcr 0 r/w 0 km 0 pcr 0 r/w 2 km 2 pcr 0 r/w 1 km 1 pcr 0 r/w port 6 input pull-up control 0 1 input pull-up transistor is off. (initial value) input pull-up transistor is on. idr1?nput data register 1 h'f4 hif bit initial value host read/write slave read/write 7 idr7 w r 6 idr6 w r 5 idr5 w r 4 idr4 w r 3 idr3 w r 0 idr0 w r 2 idr2 w r 1 idr1 w r input data (command or data input from host processor) 675 odr1?utput data register 1 h'f5 hif bit initial value host read/write slave read/write 7 odr7 r r/w 6 odr6 r r/w 5 odr5 r r/w 4 odr4 r r/w 3 odr3 r r/w 0 odr0 r r/w 2 odr2 r r/w 1 odr1 r r/w output data ( data output to host processor ) str1?tatus register 1 h'f6 hif bit initial value host read/write slave read/write 7 dbu 0 r r/w 6 dbu 0 r r/w 5 dbu 0 r r/w 4 dbu 0 r r/w 3 c/d 0 r r 0 obf 0 r r 2 dbu 0 r r/w 1 ibf 0 r r output buffer full 0 1 host has read odr1 slave has written to odr1 input buffer full 0 1 slave has read idr1 host has written to idr1 defined by user command/data 0 1 idr1 contains data idr1 contains a command defined by user 676 dadr0?/a data register 0 h'f8 d/a bit initial value read/write 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w data to be converted dadr1?/a data register 1 h'f9 d/a bit initial value read/write 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w data to be converted 677 dacr?/a control register h'fa d/a bit initial value read/write 7 daoe1 0 r/w 6 daoe0 0 r/w 5 dae 0 r/w 4 1 3 1 0 1 2 1 1 1 d/a enable daoe1 d/a output enable 0 0 1 analog output at da0 disabled analog conversion in channel 0 and output at da0 enabled description 0 1 daoe0 dae bit 7 bit 6 bit 5 channels 0 and 1 disabled channel 0 enabled, channel 1 disabled channels 0 and 1 enabled channel 0 disabled, channel 1 enabled channels 0 and 1 enabled channels 0 and 1 enabled 0 1 0 1 0 1 0 1 d/a output enable 1 0 1 analog output at da1 disabled analog conversion in channel 1 and output at da1 enabled 678 idr2?nput data register 2 h'fc hif bit initial value host read/write slave read/write 7 idr7 w r 6 idr6 w r 5 idr5 w r 4 idr4 w r 3 idr3 w r 0 idr0 w r 2 idr2 w r 1 idr1 w r input data ( command or data input from host processor ) odr2?utput data register 2 h'fd hif bit initial value host read/write slave read/write 7 odr7 r r/w 6 odr6 r r/w 5 odr5 r r/w 4 odr4 r r/w 3 odr3 r r/w 0 odr0 r r/w 2 odr2 r r/w 1 odr1 r r/w output data (data output to host processor) 679 str2?tatus register 2 h'fe hif bit initial value host read/write slave read/write 7 dbu 0 r r/w 6 dbu 0 r r/w 5 dbu 0 r r/w 4 dbu 0 r r/w 3 c/d 0 r r 0 obf 0 r r 2 dbu 0 r r/w 1 ibf 0 r r output buffer full 0 1 host has read odr2 slave has written to odr2 input buffer full 0 1 slave has read idr2 host has written to idr2 defined by user command/data 0 1 idr2 contains data idr2 contains a command defined by user 680 appendix c i/o port block diagrams note: ?eset?here means ?eset + hardware standby. c.1 port 1 block diagram wp1p: wp1d: wp1: rp1p: rp1: n = 0 to 7 note: * set priorit y write to p1pcr write to p1ddr write to port 1 read p1pcr read port 1 reset r qd c p1 n pcr wp1p reset mode 1 r s qd c p1 n ddr p1 n wp1d reset r qd c p1 n dr wp1 rp1 * rp1p hardware standby mode 3 mode 1 or 2 internal data bus internal lower address bus figure c.1 port 1 block diagram 681 c.2 port 2 block diagram wp2p: wp2d: wp2: rp2p: rp2: n = 0 to 7 note: * set priorit y write to p2pcr write to p2ddr write to port 2 read p2pcr read port 2 reset r q d c p2 n pcr wp2p reset mode 1 r s qd c p2 n ddr p2 n wp2d reset r qd c p2 n dr wp2 rp2 * rp2p hardware standby mode 3 mode 1 or 2 internal data bus internal lower address bus figure c.2 port 2 block diagram 682 c.3 port 3 block diagram wp3p: wp3d: wp3: rp3p: rp3: n = 0 to 7 write to p3pcr write to p3ddr write to port 3 read p3pcr read port 3 reset reset r qd c p3 n pcr wp3p p3 n external address write rp3p modes 1 or 2 r qd c p3 n ddr wp3d r d c p3 n dr reset wp3 hie mode 3 q internal data bus host interface data bus external address read rp3 cs iow cs ior figure c.3 port 3 block diagram 683 c.4 port 4 block diagrams wp4d: wp4: rp4: n = 0, 2 write to p4ddr write to port 4 read port 4 reset r q d c p4 n ddr wp4d reset r q d c p4 n dr wp4 p4 n rp4 8-bit timer counter clock input counter reset input internal data bus figure c.4 (a) port 4 block diagram (pins p4 0 , p4 2 ) 684 wp4d: wp4: rp4: n = 1, 6, 7 reset 8-bit timer output write to p4ddr write to port 4 read port 4 output enable 8-bit timer, pwm timer r q d c p4 n dr wp4 reset r qd c p4 n ddr wp4d p4 n rp4 internal data bus pwm timer output figure c.4 (b) port 4 block diagram (pins p4 1 , p4 6 , p4 7 ) 685 wp4d: wp4: rp4: n = 3, 5 write to p4ddr write to port 4 * read port 4 reset r q d c p4 n ddr wp4d r q d c p4 n dr wp4 p4 n rp4 8-bit timer counter clock input counter reset input internal data bus reset resobf2, resobf1 (reset hirq 11 and hirq 12 , respectively) hif note: * refer to table 14-9, host interrupt set/clear conditions. figure c.4 (c) port 4 block diagram (pins p4 3 , p4 5 ) 686 wp4d: wp4: rp4: write to p4ddr write to port 4 * read port 4 output enable 8-bit timer output 8-bit timer r q d c p4 4 dr wp4 reset r qd c p4 4 ddr wp4d p4 n rp4 internal data bus reset hif resobf1 (reset hirq 1 ) note: * refer to table 14-9, host interrupt set/clear conditions. figure c.4 (d) port 4 block diagram (pin p4 4 ) 687 c.5 port 5 block diagrams wp5d: wp5: rp5: reset serial transmit data write to p5ddr write to port 5 read port 5 output enable sci r qd c p5 0 dr wp5 reset r qd c p5 0 ddr wp5d p5 0 rp5 internal data bus figure c.5 (a) port 5 block diagram (pin p5 0 ) 688 wp5d: wp5: rp5: reset serial receive data write to p5ddr write to port 5 read port 5 input enable sci r q d c p5 1 dr wp5 reset r qd c p5 1 ddr wp5d p5 1 rp5 internal data bus figure c.5 (b) port 5 block diagram (pin p5 1 ) 689 wp5d: wp5: rp5: reset clock output write to p5ddr write to port 5 read port 5 clock output enable sci r qd c p5 2 dr wp5 reset r qd c p5 2 ddr wp5d p5 2 rp5 clock input clock input enable internal data bus figure c.5 (c) port 5 block diagram (pin p5 2 ) 690 c.6 port 6 block diagrams wp6d: wp6: rp6: rp6p: wp6p: n = 0, 2, 3, 4, 5 write to p6ddr write to port 6 read port 6 read kmpcr write to kmpcr reset r q d c p6 n ddr wp6d reset r q d c p6 n dr wp6 p6 n rp6 free-running timer input capture input counter clock input internal data bus reset wp6p rp6p hardware standby r qd c km n pcr key-sense interrupt input kmimr n figure c.6 (a) port 6 block diagram (pins p6 0 , p6 2 , p6 3 , p6 4 , p6 5 ) 691 wp6d: wp6: rp6: rp6p: wp6p: reset output compare output write to p6ddr write to port 6 read port 6 read kmpcr write to kmpcr output enable free-running timer r q d c p6 1 dr wp6 reset r qd c p6 1 ddr wp6d p6 1 rp6 internal data bus key-sense interrupt input kmimr 1 reset wp6p rp6p hardware standby r qd c km 1 pcr figure c.6 (b) port 6 block diagram (pin p6 1 ) 692 reset wp6p rp6p hardware standby r qd c km 6 pcr wp6d: wp6: rp6: rp6p: wp6p: reset output compare output write to p6ddr write to port 6 read port 6 read kmpcr write to kmpcr output enable free-running timer irq enable register r qd c p6 6 dr wp6 reset r qd c p6 6 ddr wp6d p6 6 rp6 irq6 enable irq 6 input internal data bus kmimr 6 other key-sense interrupt inputs figure c.6 (c) port 6 block diagram (pin p6 6 ) 693 reset wp6p rp6p hardware standby r qd c km 7 pcr reset r q d c p6 7 ddr wp6d reset r q d c p6 7 dr wp6 p6 7 rp6 wp6d: wp6: rp6: rp6p: wp6p: write to p6ddr write to port 6 read port 6 read kmpcr write to kmpcr irq enable register irq7 enable irq 7 input internal data bus kmimr 7 key-sense interrupt input figure c.6 (d) port 6 block diagram (pin p6 7 ) 694 c.7 port 7 block diagrams p7 n rp7: n = 0 to 5 read port 7 a/d converter analog input internal data bus rp7 figure c.7 (a) port 7 block diagram (pins p7 0 to p7 5 ) p7 n rp7: n = 6, 7 read port 7 a/d converter d/a converter analog input output enable internal data bus rp7 analog output figure c.7 (b) port 7 block diagram (pins p7 6 and p7 7 ) 695 c.8 port 8 block diagrams wp8d: wp8: rp8: write to p8ddr write to port 8 read port 8 reset r q d c p8 0 ddr wp8d reset r q d c p8 0 dr wp8 p8 0 rp8 internal data bus hif ha 0 hie figure c.8 (a) port 8 block diagram (pin p8 0 ) 696 wp8d: wp8: rp8: reset fga 20 write to p8ddr write to port 8 read port 8 fga 20 e hif r qd c p8 1 dr wp8 reset r qd c p8 1 ddr wp8d p8 1 rp8 internal data bus figure c.8 (b) port 8 block diagram (pin p8 1 ) 697 wp8d: wp8: rp8: n = 2, 3 reset write to p8ddr write to port 8 read port 8 r q d c p8 n dr wp8 reset r q d c p8 n ddr wp8d p8 n rp8 hie hif input ( cs 1 , ior ) internal data bus figure c.8 (c) port 8 block diagram (pins p8 2 , p8 3 ) 698 wp8d: wp8: rp8: reset write to p8ddr write to port 8 read port 8 r q d c p8 4 dr wp8 reset r q d c p8 4 ddr wp8d p8 4 rp8 internal data bus irq enable register irq3 enable hif iow irq 3 input hie stac sci output enable serial transmit data figure c.8 (d) port 8 block diagram (pin p8 4 ) 699 p8 5 reset wp8d: wp8: rp8: write to p9ddr write to port 8 read port 8 r q d c p8 5 ddr wp8d reset r qd c p8 5 dr wp8 rp8 hif hie stac cs 2 input irq 4 input irq enable register irq4 enable internal data bus sci input enable serial receive data figure c.8 (e) port 8 block diagram (pin p8 5 ) 700 reset wp8 reset r q d c p8 6 ddr wp8d p8 6 rp8 internal data bus irq enable register irq5 enable irq 5 input sci clock output enable clock output clock input enable clock input r q d c p8 6 dr wp8d: wp8: rp8: write to p8ddr write to port 8 read port 8 note: for a block diagram when the scl pin function is selected, see section 13, i 2 c bus interface. figure c.8 (f) port 8 block diagram (pin p8 6 ) 701 c.9 port 9 block diagrams p9 0 reset wp9d: wp9: rp9: write to p9ddr write to port 9 read port 9 r q d c p9 0 ddr wp9d reset r qd c p9 0 dr wp9 rp9 irq 2 input irq2 enable irq enable register external trigger input a/d converter ecs 2 input hie stac hif internal data bus figure c.9 (a) port 9 block diagram (pin p9 0 ) 702 p9 1 reset internal data bus wp9d: wp9: rp9: write to p9ddr write to port 9 read port 9 r q d c p9 1 ddr wp9d reset r q d c p9 1 dr wp9 rp9 irq1 enable irq enable register irq 1 input hie stac hif eiow input figure c.9 (b) port 9 block diagram (pin p9 1 ) 703 p9 2 reset internal data bus wp9d: wp9: rp9: write to p9ddr write to port 9 read port 9 r q d c p9 2 ddr wp9d reset r q d c p9 2 dr wp9 rp9 irq0 enable irq enable register irq 0 input figure c.9 (c) port 9 block diagram (pin p9 2 ) 704 p9 n reset internal data bus wp9d: wp9: rp9: n = 3, 4, 5 write to p9ddr write to port 9 read port 9 r q d c p9 n ddr wp9d reset r q d c p9 n dr wp9 rp9 hardware standby mode 1 or 2 mode 3 rd output wr output as output mode 1 or 2 figure c.9 (d) port 9 block diagram (pins p9 3 , p9 4 , p9 5 ) 705 p9 6 reset wp9d: wp9: rp9: note: * set priority write to p9ddr write to port 9 read port 9 r s q d c p9 6 ddr wp9d rp9 hardware standby mode 1 or 2 * internal data bus figure c.9 (e) port 9 block diagram (pin p9 6 ) 706 p9 7 mode 1 or 2 reset wp9d: wp9: rp9: write to p9ddr write to port 9 read port 9 r q d c p9 7 ddr wp9d reset r q d c p9 7 dr wp9 rp9 wait input note: for a block diagram when the sda pin function is selected, see section 13, i 2 c bus interface. internal data bus wait input enable figure c.9 (f) port 9 block diagram (pin p9 7 ) 707 appendix d port states in each processing state table d.1 port states port name (multiplexed pin names) mode reset hardware standby mode software standby mode sleep mode program execution state (normal operation) p1 7 to p1 0 1 l t l keep * 1 a 7 to a 0 a 7 to a 0 2 t (ddr = 1) l (ddr = 0) keep address/ input port 3 keep i/o port p2 7 to p2 0 1 l t l keep * 1 a 15 to a 8 a 15 to a 8 2 t (ddr = 1) l (ddr = 0) keep address/ input port 3 keep i/o port p3 7 to p3 0 1t t t t d 7 to d 0 d 7 to d 0 2 3 keep keep i/o port p4 7 to p4 0 1 t t keep * 2 keep i/o port 2 3 p5 2 to p5 0 1 t t keep * 2 keep i/o port 2 3 p6 7 to p6 0 1 t t keep * 2 keep i/o port 2 3 p7 7 to p7 0 1 t t t t input port 2 3 708 port name (multiplexed pin names) mode reset hardware standby mode software standby mode sleep mode program execution state (normal operation) p8 6 to p8 0 1 t t keep * 2 keep i/o port 2 3 p9 7 / wait 1 t t t/keep * 2 t/keep wait / 2 i/o port 3 keep * 2 keep i/o port p9 6 / 1 clock t h clock clock 2 output output output 3 t (ddr = 1) h (ddr = 0) t (ddr = 1) clock output (ddr = 0) t (ddr = 1) clock output (ddr = 0) input port p9 5 to p9 3 ,1 h t h h as , wr , rd as , wr , rd 2 3 t keep keep i/o port p9 2 to p9 0 1 t t keep keep i/o port 2 3 legend: h: high level l: low level t: high impedance keep: input port becomes high-impedance (when ddr = 0 and pcr = 1, mos input pull-ups remain on), output port retains state notes: * 1 with address outputs, the last address accessed is retained. * 2 as on-chip supporting modules are initialized, becomes an i/o port determined by ddr and dr. 709 appendix e timing of transition to and recovery from hardware standby mode timing of transition to hardware standby mode (1) to retain ram contents when the rame bit in syscr is set to 1, drive the res signal low 10 system clock cycles before the stby signal goes low, as shown below. res must remain low until stby goes low (minimum delay from stby low to res high: 0 ns). stby res t 1 10 t cyc t 2 0 ns (2) when the rame bit in syscr is cleared to 0 or when it is not necessary to retain ram contents, res does not have to be driven low as in (1). timing of recovery from hardware standby mode: drive the res signal low approximately 100 ns before stby goes high. stby res t 100 ns t osc 710 appendix f option list please check off the appropriate applications and enter the necessary information. date of order customer department name rom code name lsi number (hitachi entry) 1. rom size hd6433334y 32 kbytes hd6433394 32 kbytes hd6433336y 48 kbytes hd6433396 48 kbytes hd6433337y 60 kbytes hd64333397 60 kbytes 2. system oscillator crystal oscillator f = mhz external clock f = mhz 3. power supply voltage/maximum operating frequency v cc = 4.5 v to 5.5 v (16 mhz max.) v cc = 4.0 v to 5.5 v (12 mhz max.) v cc = 2.7 v to 5.5 v (10 mhz max.) notes: 1. please select the power supply voltage/operating frequency version according to the power supply voltage to be used. example: for use at v cc = 4.5 v to 5.5 v/f = 10 mhz, select v cc = 4.5 v to 5.5 v (16 mhz max.). 2. please enter the power supply voltage and maximum operating frequency of the selected version in accordance with the single-chip microcomputer order specification . 711 rom code name lsi number (hitachi entry) 4. i 2 c bus option [h8/3337 series] i 2 c bus used i 2 c bus not used notes: 1. i 2 c bus used includes all cases where data transfer is performed by means of the scl and sda pins using the on-chip i 2 c bus interface function (hardware module). as long as the i 2 c bus interface function (hardware module) is used, various bus interfaces with different bus specifications and names are also included in i 2 c bus used . 2. if i 2 c bus not used is selected, values cannot be set in i 2 c bus interface related registers (iccr, icsr, icdr, and icmr). these registers return h ff if read. in the case of an emulator and the ztat and f-ztat versions, the i 2 c bus used option is taken as being selected. if the i 2 c bus not used option is selected, care must be taken to confirm that i 2 c bus interface related registers are not accessed. for (1) basic items and the microcomputer family item in the ?ingle-chip microcomputer ordering specifications sheet? enter an item selected from the table below in accordance with the combination of (1) and (4) above. when the ? 2 c bus used?option is selected, this should be indicated again in (1) basic items, special specifications (product specifications, marking specifications). i 2 c rom size i 2 c bus used i 2 c bus not used 32 kbytes hd6433334w hd6433334y 48 kbytes hd6433336w hd6433336y 60 kbytes hd6433337w hd6433337y 712 appendix g product code lineup table g.1 h8/3397 series, h8/3337 series, h8/3334yf-ztat, and h8/3337yf-ztat product code lineup product type product code mark code package (hitachi package code) h8/3397 mask rom standard hd6433397f hd6433397( *** )f 80-pin qfp (fp-80a) version products hd6433397tf hd6433397( *** )tf 80-pin tqfp (tfp-80c) hd6433397cp hd6433397( *** )cp 84-pin plcc (cp-84) h8/3396 mask rom standard hd6433396f hd6433396( *** )f 80-pin qfp (fp-80a) version products hd6433396tf hd6433396( *** )tf 80-pin tqfp (tfp80-c) hd6433396cp hd6433396( *** )cp 84-pin plcc (cp-84) h8/3394 mask rom standard hd6433394f hd6433394( *** )f 80-pin qfp (fp-80a) version products hd6433394tf hd6433394( *** )tf 80-pin tqfp (tfp80-c) hd6433394cp hd6433394( *** )cp 84-pin plcc (cp-84) h8/3337y flash dual-power- hd64f3337yf16 hd64f3337yf16 80-pin qfp (fp-80a) memory supply f-ztat hd64f3337yflh16 hd64f3337yf16 version version hd64f3337ytf16 hd64f3337ytf16 80-pin tqfp (tfp-80c) hd64f3337ytflh16 hd64f3337ytf16 hd63f3337ycp16 hd64f3337ycp16 84-pin plcc (cp-84) single-power- hd64f3337sf16 hd64f3337f16 80-pin qfp (fp-80a) supply f-ztat version hd64f3337stf16 hd64f3337tf16 80-pin tqfp (tfp-80c) prom ztat hd6473337yf16 hd6473337yf16 80-pin qfp (fp-80a) version version hd6473337ytf16 hd6473337ytf16 80-pin tqfp (tfp-80c) hd6473337ycp16 hd6473337ycp16 84-pin plcc (cp-84) mask rom standard hd6433337yf hd6433337y( *** )f 80-pin qfp (fp-80a) version products hd6433337ytf hd6433337y( *** )tf 80-pin tqfp (tfp-80c) hd6433337ycp hd6433337y( *** )cp 84-pin plcc (cp-84) mask rom with i 2 c hd6433337wf hd6433337w( *** )f 80-pin qfp (fp-80a) version interface hd6433337wtf hd6433337w( *** )tf 80-pin tqfp (tfp-80c) hd6433337wcp hd6433337w( *** )cp 84-pin plcc (cp-84) 713 product type product code mark code package (hitachi package code) h8/3336y mask rom standard hd6433336yf hd6433336y( *** )f 80-pin qfp (fp-80a) version products hd6433336ytf hd6433336y( *** )tf 84-pin tqfp (tfp-80c) hd6433336ycp hd6433336y( *** )cp 84-pin plcc (cp-84) with i 2 c bus hd6433336wf hd6433336w( *** )f 80-pin qfp (fp-80a) interface hd6433336wtf hd6433336w( *** )tf 80-pin tqfp (fp-80c) hd6433336wcp hd6433336w( *** )cp 80-pin lcc (cp-84) h8/3334y flash f-ztat hd64f3334yf16 hd64f3334yf16 80-pin qfp (fp-80a) memory version hd64f3334yflh16 hd64f3334yf16 version hd64f3334ytf16 hd64f3334ytf16 80-pin tqfp (tfp-80c) hd64f3334ytflh16 hd64f3334ytf16 hd64f3334ycp16 hd64f3334ycp16 84-pin plcc (cp-84) prom ztat hd6473334yf16 hd6473334yf16 80-pin qfp (fp-80a) version version hd6473334ytf16 hd6473334ytf16 80-pin tqfp (tfp-80c) hd6473334ycp16 hd6473334ycp16 84-pin plcc (cp-84) mask rom standard hd6433334yf hd6433334y( *** )f 80-pin qfp (fp-80a) version products hd6433334ytf hd6433334y( *** )tf 80-pin tqfp (tfp-80c) with i 2 c bus hd6433334ycp hd6433334y( *** )cp 84-pin plcc (cp-84) interface hd6433334wf hd6433334w( *** )f 80-pin qfp (fp-80a) hd6433334wtf hd6433334w( *** )tf 80-pin tqfp (tfp-80c) hd6433334wcp hd6433334w( *** )cp 84-pin plcc (cp-84) note: ( *** ) in the mark code for mask rom versions is the rom code. the i 2 c bus interface is an option. please note the following points when using this optional function. 1. notify your hitachi sales representative that you will be using an optional function. 2. with mask rom versions, optional functions can be used if the product code includes the letter w in place of the letter y (e.g. hd6433337wf, hd6433337wtf). 3. the product code is the same for ztat versions, but please be sure to notify hitachi if you are going to use this optional function. 714 appendix h package dimensions figure h.1 shows the dimensions of the fp-80a package. figure h.2 shows the dimensions of the tfp-80c package. figure h.3 shows the dimensions of the cp-84 package. hitachi code jedec jeita mass (reference value) fp-80a conforms 1.2 g *dimension including the plating thickness base material dimension 60 0 ? 8 0.10 0.12 m 17.2 0.3 41 61 80 1 20 40 21 17.2 0.3 *0.32 0.08 0.65 3.05 max 1.6 0.8 0.3 14 2.70 *0.17 0.05 0.10 + 0.15 ? 0.10 0.83 0.30 0.06 0.15 0.04 unit: mm figure h.1 package dimensions (fp-80a) 715 hitachi code jedec jeita mass (reference value) tfp-80c conforms 0.4 g *dimension including the plating thickness base material dimension 0.10 m 0.10 0.5 0.1 0 ? 8 1.20 max 14.0 0.2 0.5 12 14.0 0.2 60 41 120 80 61 21 40 *0.17 0.05 1.0 *0.22 0.05 0.10 0.10 1.00 1.25 0.20 0.04 0.15 0.04 unit: mm figure h.2 package dimensions (tfp-80c) 716 1.27 *0.42 0.10 29.28 28.20 0.50 28.20 0.50 4.40 0.20 2.55 0.15 0.10 53 33 54 74 75 84 1 11 12 32 0.75 30.23 + 0.12 ? 0.13 30.23 + 0.12 ? 0.13 1.94 0.90 0.38 0.08 0.20 m hitachi code jedec jeita mass (reference value) cp-84 conforms conforms 6.4 g *dimension including the plating thickness base material dimension unit: mm figure h.3 package dimensions (cp-84) h8/3397 series and h8/3337 series hardware manual publication date: 1st edition, september 1994 6th edition, march 2002 published by: business planning division semiconductor & integrated circuits hitachi, ltd. edited by: technical documentation group hitachi kodaira semiconductor co py ri g ht ? hitachi, ltd., 1994. all ri g hts reserved. printed in ja p an. |
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